JP3125764B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to reduction of noise of an input signal.

[0002]

2. Description of the Related Art Conventionally, a dynamic CMOS circuit has been known as a CMOS circuit capable of operating at high speed.
FIG. 2 is a circuit diagram showing an example of a conventional dynamic CMOS circuit. As shown, this dynamic CMO
The S circuit includes a p-channel MOS field effect transistor (hereinafter, referred to as a PMOS transistor) P0, n-channel MOS field effect transistors (hereinafter, referred to as NMOS transistors) N0, N1, and an inverter IV1.

In this dynamic CMOS circuit,
When the clock signal input from the clock input terminal CLK is at the H (high) level, both the PMOS transistor P0 and the NMOS transistor N0 are turned on. At this time, when the input signal input from the input terminal IN to the gate of the NMOS transistor N1 is at the H level, the NMOS transistor N1 is turned on, so that the charges accumulated in the dynamic node A are discharged to the ground. Then, the output signal output from the output terminal OUT via the inverter IV1 becomes H level.

On the other hand, when L is at the L (low) level, NM
When the OS transistor N1 is turned off,
Charge is accumulated in the dynamic node A, and the inverter I
The output signal output from the output terminal OUT via V1 becomes L level. Here, when noise is mixed in the input signal from the input terminal IN, the NMOS transistor N1 is turned on by the noise level.
For this reason, the charge stored in the dynamic node A is discharged to the ground via the ON-state NMOS transistors N1 and N0, and the potential level of the dynamic node A decreases. When this potential level exceeds the threshold level of inverter IV1, the output signal output from output terminal OUT changes from L level to H level.

[0005]

In a static CMOS circuit, a PMOS transistor and an NMOS transistor are used.
Since the input signal is received by the two transistors, the threshold level of the output signal is determined by the balance between the PMOS transistor and the NMOS transistor. On the other hand, in the above dynamic CMOS circuit, since the input signal is received only by the NMOS transistor, the threshold level of the NMOS transistor becomes the threshold level of the entire circuit (the input signal is received only by the PMOS transistor). The same applies to things). Therefore, conventionally, there has been a problem that a dynamic CMOS circuit is likely to cause a malfunction when noise is mixed in an input signal.

[0006] In order to prevent such a malfunction due to noise mixing in an input signal, a semiconductor logic circuit described in JP-A-10-112646 has been proposed. In this semiconductor logic circuit, as shown in FIG. 3, a circuit / NBL that outputs the inverted logic of the circuit NBL is provided, and feedback transistors MP13 and MP3 controlled by the output of the circuit / NBL are provided at the output of the circuit NBL. .

However, in this semiconductor logic circuit,
The generation of the output signal OUT itself due to noise is allowed, and the output signal OUT cannot be returned to a normal level until the noise mixed into the input signal disappears. Also, since the circuit / NBL with inverted logic and the feedback transistors MP13 and MP3 must be provided, the area on the semiconductor chip is required to be twice or more as compared with the case where such a malfunction prevention circuit is not provided. There was also a problem of becoming.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object to increase the noise margin of a logic circuit by adding a simple circuit.

[0009]

In order to achieve the above object, a logic circuit according to the present invention comprises a current path having one end connected to a power supply, the other end grounded, and a signal voltage supplied to a control terminal. A first transistor that is turned on or off depending on a level; and accumulates electric charge at a predetermined node from the power supply or discharges electric charge stored at a predetermined node according to the state of the first transistor. One end of a current path is connected to an input terminal for inputting a signal voltage to be supplied to the control terminal, and a signal line between the input terminal and a control terminal of the first transistor. An active element whose end is grounded and which is turned on or off according to the level of the signal voltage supplied to the control terminal.

In the above logic circuit, noise is mixed in a state where the signal voltage input from the input terminal is at a low level, and when the signal voltage is instantaneously at a high level, the active element is in a conductive state. Then, the charge due to the input signal voltage is discharged through the active element, so that the signal voltage supplied to the control terminal of the first transistor can be kept at a low level. As a result, the effect of mixing noise into the input signal can be reduced.

The logic circuit includes a clock input terminal for inputting a clock signal, one end of a current path connected to the power supply, and the other end connected to one end of a current path of the first transistor. A second transistor having one end of a current path of the transistor connected to the power supply, and a control terminal supplied with a clock signal input from the clock input terminal; and one end of the current path connected to the current of the first transistor. The other end of the road, the other end is grounded, and the first
And a third transistor whose other end of the current path of the transistor is grounded and whose control terminal is supplied with a clock signal input from the clock input terminal. In this case, the predetermined node is:
It is on a signal line connecting one end of the current path of the first transistor and the other end of the current path of the second transistor, and the second and third transistors are arranged in accordance with the level of the clock signal. One is set to a conductive state and the other is set to a non-conductive state.

In this case, the second and third transistors constitute a substantial CMOS structure, and a dynamic circuit in which electric charges are stored in a predetermined node while the level of the clock signal is either high or low. Be composed. The present invention is particularly effective because such a dynamic circuit is more susceptible to noise than a static circuit in which an input signal is supplied to control terminals of two transistors having different polarities.

In the above-mentioned logic circuit, the active element does not discharge all of the electric charge given to the signal line by the signal voltage from the other end of the current path, and
It is preferable that the resistance value in the conductive state is set so that the level of the signal voltage supplied to the control terminal of the transistor gradually increases to the level of the signal voltage supplied to the input terminal.

In the above-mentioned logic circuit, the active element may be constituted by, for example, an n-channel field effect transistor having a drain connected to the signal line and a source grounded. In this case, the logic circuit further includes an inverter circuit that inverts a level of a signal voltage on a signal line between a drain of the active element and a control terminal of the transistor and supplies the signal voltage to a gate of the n-channel field effect transistor. Can be provided.

In the above-mentioned logic circuit, a plurality of the first transistors may be provided, and a signal voltage may be supplied to a control terminal from an input terminal corresponding to each of the first transistors. In this case, the active element (n
A channel-type field-effect transistor) and / or an inverter circuit may be provided corresponding to each first transistor. Note that the plurality of first transistors may take any of a series and a parallel connection form.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a configuration of a dynamic CMOS circuit according to this embodiment. As shown, this dynamic CMOS circuit includes a p-channel MOS type field effect transistor (hereinafter, referred to as a PMOS transistor P0) and an n-channel MOS type field effect transistor (hereinafter, referred to as an NMOS transistor) N0, N
1, and N for noise reduction in addition to inverter IV1
A MOS transistor N2 and an inverter IV2 for controlling the MOS transistor N2 are provided.

The gate of the PMOS transistor P0 is connected to the clock input terminal CLK. When the clock signal input from the clock input terminal CLK is at the H (high) level (for example, 5 V), the PMOS transistor P0 is turned off (non-conductive). ), And is in the ON state (conduction state) at the L (low) level (for example, 0 V). The NMOS transistor N0 has a gate connected to the clock input terminal CLK, and is turned on when the clock signal input from the clock input terminal CLK is at the H level, and is turned off when the clock signal is at the L level.

The inverter IV2 inverts the level of the input signal from the input terminal IN, outputs the inverted signal, and supplies the inverted signal to the gate of the NMOS transistor N2. NMOS transistor N
2 turns on when the output signal of the inverter IV2 is at the H level, and turns off when the output signal is at the L level.
The drain of the NMOS transistor N2 is connected to the input terminal IN.
And the NMOS transistor N1 are connected to a signal line, and the source is grounded.

The gate of the NMOS transistor N1 is connected to a connection line from the input terminal IN. However,
The connection line between the input terminal IN and the gate of the NMOS transistor N1 is connected to the source of the NMOS transistor N2 and the input terminal of the inverter IV2. NM
The OS transistor N1 is turned on when an input signal input from the input terminal IN through this connection line is at an H level, and turned off when the input signal is at an L level.

The drain of the PMOS transistor P0 is connected to a voltage source, and the source is connected to the drain of the NMOS transistor N1. The source of the NMOS transistor N1 is connected to the NMOS transistor N0.
Connected to the drain of The source of the NMOS transistor N1 is grounded.

The inverter IV1 inverts the signal level of the connection line (dynamic node A) between the PMOS transistor P0 and the NMOS transistor N1 and outputs the inverted signal to the output terminal OUT.

The on-resistance of the NMOS transistor N2 changes from the input terminal IN to the NMO when the input signal input to the input terminal IN changes from L level to H level (when the input signal changes, the NMOS transistor N2 is ON).
The content is set such that substantially all charges are discharged to the ground via the S-transistor N2, and the size is appropriately set. On the other hand, the PMOS transistors P0 and NM
The ON resistance of the OS transistors N0 and N1 is set to a sufficiently small value.

The operation of the dynamic CMOS circuit according to this embodiment will be described below. Below,
A description will be given by dividing the cases according to the state of the level of the clock signal and the level of the input signal.

(1) When the clock signal is at L level and the input signal is at L level When the clock signal from the clock signal input terminal CLK is at L level, the PMOS transistor P0 is turned on and the NMOS transistor N0 is turned off. Becomes
In this state, if the input signal from the input terminal IN is at the L level, the NMOS transistor N1 is turned off. Thereby, the PMOS transistor P0 is supplied from the voltage source.
, The electric charge is accumulated in the dynamic node A, and the dynamic node A becomes H level. This is inverted by the inverter IV1, and the output signal output from the output terminal OUT becomes L level.

In this state, if noise is mixed into the input signal input from the input terminal IN and the input signal instantaneously goes to the H level, the NMOS which is still ON due to signal propagation delay A significant amount of charge is released to ground via transistor N2. For this reason,
The signal input to the gate of the NMOS transistor N1 is H
It takes some time to reach the level. However, usually, before the input signal to the gate of the NMOS transistor N1 reaches the H level, the noise disappears and the input signal input from the input terminal IN returns to the L level. Therefore, the NMOS transistor N1 can be turned on even if the noise is mixed and the input signal is momentarily turned to the H level.
The F state can be maintained. However, in this case, N
Even if the MOS transistor N1 is turned on, the NMO
Since the S transistor N0 is at the OFF level,
The charge stored in the dynamic node A is not discharged to the ground.

(2) When the clock signal is at L level and the input signal is at H level When the clock signal from the clock signal input terminal CLK is at L level, the PMOS transistor P0 is turned on and the NMOS transistor N0 is turned off. Becomes
In this state, when the input signal from the input terminal IN is at the H level, the NMOS transistor N1 is turned on. At this time, the NMOS transistor N0 in the OFF state
As a result, the electric charge stored in the dynamic node A is not discharged to the ground, and the dynamic node A goes to the H level. This is inverted by the inverter IV1, and the output signal output from the output terminal OUT becomes L level.

In this state, when noise is mixed into the input signal input from the input terminal IN and the level of the input signal momentarily becomes L level, the NMOS transistor N
1 is momentarily turned off. Also in this case, the charge accumulated in the dynamic node A is not discharged to the ground, and the dynamic node A remains at the H level. Therefore, there is no influence due to noise mixing in the input signal.

(3) When the clock signal is at H level and the input signal is at L level When the clock signal from the clock signal input terminal CLK is at L level, the PMOS transistor P0 is turned off and the NMOS transistor N0 is turned on. Becomes
In this state, if the input signal from the input terminal IN is at the L level, the NMOS transistor N1 is turned off. As a result, the electric charge accumulated in the dynamic node A is held without being discharged to the ground, and the dynamic node A becomes H level. This is inverted by the inverter IV1, and the output signal output from the output terminal OUT becomes L level.

In this state, when noise is mixed in the input signal input from the input terminal IN and the level of the input signal instantaneously becomes H level, the input signal is still in the ON state due to signal propagation delay. A significant amount of charge is discharged to ground via NMOS transistor N2. For this reason, it takes some time until the signal input to the gate of the NMOS transistor N1 becomes H level. However, normally, before the input signal to the gate of the NMOS transistor N1 reaches the H level, noise disappears, and the input signal input from the input terminal IN becomes low.
Return to level. Therefore, the NMOS transistor N1
Even if noise is mixed in, the OFF state can be maintained even if the input signal instantaneously goes to the H level, so that the charge accumulated in the dynamic node A does not have to be discharged to the ground. Thus, it is possible to operate without being affected by noise.

On the other hand, when the input signal input from the input terminal IN changes from the L level to the H level due to a state change without being affected by noise, the NMOS transistor N2 has a certain degree of ON resistance. The signal input to the gate of the NMOS transistor N1 becomes H level slightly after the rising timing of the input signal. As a result, the NMOS transistor N1 is turned on, and the electric charge accumulated in the dynamic node A is discharged to the ground, so that the dynamic node A can be set to the L level. For this reason, it becomes possible to operate normally as a dynamic CMOS circuit.

(4) When the clock signal is at H level and the input signal is at H level When the clock signal from the clock signal input terminal CLK is at L level, the PMOS transistor P0 is turned off and the NMOS transistor N0 is turned on. Becomes
In this state, when the input signal from the input terminal IN is at the H level, the NMOS transistor N1 is turned on. As a result, the electric charge stored in the dynamic node A is discharged to the ground via the NMOS transistors N1 and N0, and the dynamic node A becomes L level. This is inverted by the inverter IV1, and the output signal output from the output terminal OUT becomes H level.

In this state, when noise is mixed in the input signal input from the input terminal IN and the level of the input signal instantaneously becomes L level, the NMOS transistor N
1 is momentarily turned off. However, since the PMOS transistor P0 is in the OFF state, no charge is accumulated in the dynamic node A, and the dynamic node A remains at the L level. Therefore, there is no influence due to noise mixing in the input signal.

As described above, in the dynamic CMOS circuit according to this embodiment, noise is mixed when the input signal input from the input terminal IN is at the L level, and the input signal is instantaneously changed to the H level. However, a considerable part of the charge is discharged to the ground via the NMOS transistor N2 which is in the ON state. Therefore, N
The potential of the gate of the MOS transistor N1 does not go to the H level substantially at the same time as the noise is mixed in, but has some time. On the other hand, the noise level in such a case is usually
Since the level immediately returns to the L level, the NMOS transistor N1
Does not go to the H level, and the NMOS transistor N1 is not turned on by noise. Therefore, the electric charge accumulated in the dynamic node A is not discharged to the ground, and the level of the dynamic node A, that is, the level of the output signal output from the output terminal OUT is not affected by noise.

In the dynamic CMOS circuit according to this embodiment, the noise level of the input signal from the input terminal IN can be reduced only by adding the inverter IV2 and the NMOS transistor N2. Therefore, the area required when this dynamic CMOS circuit is formed on a semiconductor chip does not increase significantly as compared with the case where a circuit for reducing the noise level is not provided.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, when the clock signal from the clock input terminal CLK is at the H level and the input terminal IN
The NMOS transistor N2 and the inverter IV2 are provided as a circuit for reducing noise mixed into the input terminal IN when the input signal from the input terminal is at the L level.
On the other hand, as a circuit for reducing noise mixed into the input terminal IN, a PMOS transistor whose gate and drain are connected to a connection line between the input terminal IN and the NMOS transistor N0 and whose source is grounded is used. It may be provided.

In the above embodiment, the input signal from the input terminal IN has been input to the NMOS transistor N0. However, the present invention can also be applied to a dynamic circuit in which an input signal is input to a PMOS transistor. In this case, the logic is opposite to that of the circuit described in the above embodiment, and it is possible to reduce noise mixed into the input terminal when the clock signal is at the L level and the input signal is at the H level.

In the above embodiment, when the input terminal IN is 1
A description has been given of only one dynamic CMOS circuit. That is, the dynamic CMOS circuit in the above embodiment has only one input signal. However, the present invention can also be applied to a dynamic CMOS circuit having a plurality of input signals. In this case, a circuit for reducing noise mixed in from the input terminal as described above may be provided corresponding to each input signal.

In the above-described embodiment, the CMOS using the PMOS transistor P0 and the NMOS transistor N0 is used.
The dynamic CMOS circuit having the structure has been described as an example. However, the present invention can also be applied to a dynamic circuit having no CMOS structure.

In the above embodiment, the clock signal is L
The case where the present invention is applied to a dynamic circuit in which charges are stored in the dynamic node A at the time of the level has been described.
However, the present invention can be applied to, for example, a NOT circuit as shown in FIG. NO in FIG.
In the T circuit, when the input signal from the input terminal IN instantaneously changes from the L level to the H level due to the contamination of noise, electric charges are released via the NMOS transistor N2 which is in the ON state as described above. , The level of noise input to the gate of the NMOS transistor N1 is reduced. Similarly, the present invention can be applied to a NAND circuit as shown in FIG. 2B and a NOR circuit as shown in FIG. 2C.

[0042]

As described above, according to the logic circuit of the present invention, the noise margin for the input signal can be increased by adding a simple circuit.

[Brief description of the drawings]

FIG. 1 is a dynamic CM according to an embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of an OS circuit.

FIG. 2 is a circuit diagram showing a configuration of a NOT circuit according to a modification of the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional dynamic CMOS circuit.

FIG. 4 is a circuit diagram showing a configuration of a conventional dynamic CMOS circuit.

[Explanation of symbols]

A dynamic node CLK clock input terminal IN input terminal OUT output terminal N0 NMOS transistor (n-channel MOS field effect transistor) N1 NMOS transistor N2 NMOS transistor P1 PMOS transistor (p-channel MOS field effect transistor) IV1 inverter IV2 inverter

Claims (4)

(57) [Claims] A first transistor connected to a power supply at one end of the current path and grounded at the other end, the first transistor being turned on or off by a level of a signal voltage supplied to a control terminal; A logic circuit for accumulating electric charge at a predetermined node from the power supply or discharging electric charge stored at the predetermined node according to a state of the first transistor, wherein a signal voltage to be supplied to the control terminal is input. An input terminal, one end of a current path is connected to a signal line between the input terminal and the control terminal of the first transistor, the other end is grounded, and a signal voltage of the signal voltage supplied to the control terminal is A logic circuit comprising: an active element that is turned on or off according to a level. A clock input terminal for inputting a clock signal; one end of a current path connected to the power supply; the other end connected to one end of a current path of the first transistor; A second transistor having one end of a current path connected to the power supply and having a control terminal supplied with a clock signal input from the clock input terminal; one end of the current path being connected to the other of the current path of the first transistor; A third transistor connected to one end, the other end grounded, the other end of the current path of the first transistor grounded, and a control terminal supplied with a clock signal input from the clock input terminal; The predetermined node is on a signal line connecting one end of the current path of the first transistor and the other end of the current path of the second transistor; 3. The logic circuit according to claim 1, wherein one of the three transistors is turned on and the other is turned off in accordance with the level of the clock signal. 3. The level of a signal voltage supplied to a control terminal of the first transistor without discharging all of the electric charge given to the signal line by the signal voltage from the other end of the current path. 2. The resistance value of the conductive state is set so that the current value gradually increases to the level of the signal voltage supplied to the input terminal.
Or the logic circuit according to 2. 4. The active element comprises an n-channel field-effect transistor having a drain connected to the signal line and a source grounded, and having a source connected to a drain of the active element and a control terminal of the transistor. Invert the signal voltage level on the signal line,
4. The logic circuit according to claim 1, further comprising an inverter circuit that supplies a gate of the n-channel field effect transistor. 5.