JP3436210B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high speed / low power operation.

[0002]

[Prior Art] 1989 International Symposium on VLS Technology, Systems and Applications, Proceedings of Technical Papers (1989
May) Pages 188 to 192 (1989 International
Symposium on VLSI Technology, Systems and Applicat
ions, Proceedings of Technical Papers, pp.188-192
(May 1989)), the breakdown voltage of a MOS transistor decreases as it is miniaturized, so that the operating voltage must be lowered.

[0003]

In this case, in order to maintain the high speed operation, the MOS should be adjusted according to the decrease in the operating voltage.
The threshold voltage (V _T ) of the transistor also needs to be lowered. This is because the operating speed is governed by the effective gate voltage of the MOS transistor, that is, the value obtained by subtracting V _T from the operating voltage, and the higher this value, the higher the speed. However, when V _{T is set} to about 0.4 V or less, as described below, due to the subthreshold characteristic (tailing characteristic) of the MOS transistor, it is no longer possible to completely turn off the transistor, and a direct current flows. Occurs.

The conventional CMOS inverter shown in FIG. 28 will be described. Ideally, the N-channel MOS transistor M _N is turned off when the input signal IN is at a low level (= V _SS ), and the P-channel MO transistor is when the input signal IN is at a high level (= V _CC ).
The S-transistor M _P is turned off and no current flows in any case. However, V of MOS transistor
_{When T} becomes low, the subthreshold characteristic cannot be ignored.

As shown in FIG. 29, the drain current I _DS in the subthreshold region is proportional to the exponential function of the gate-source voltage V _GS and is represented by the following equation.

[0006]

[Equation 1]

Here, W is the channel width of the MOS transistor, I ₀ and W ₀ are the current value and channel width when defining V _T , and S is the tailing coefficient (the reciprocal of the slope of the V _GS -log I _DS characteristic). is there. Therefore, even if V _GS = 0, the subthreshold current

[0008]

[Equation 2]

Flows. Since the transistor in the off state in the CMOS inverter of FIG. 28 has V _GS = 0, the above current I _L flows from the high power supply voltage V _CC toward the low power supply voltage V _SS which is the ground potential in the non-operating state. Become.

[0010] The sub-threshold current, as shown in FIG. 29, 'Lowering the, I _L from I _L' V _T the threshold voltage from V _T exponentially increases in the.

As is clear from the above equation of Equation 2, in order to reduce the subthreshold current, V _T should be increased or S should be decreased. However, the former causes a decrease in speed due to a decrease in effective gate voltage. In particular, from the viewpoint of breakdown voltage, if the operating voltage is lowered along with the miniaturization, the speed decrease becomes remarkable, and the advantage of miniaturization cannot be utilized, which is not preferable. In addition, the latter is difficult for the following reasons as long as it is assumed to operate at room temperature.

The tailing coefficient S is expressed as follows by the capacitance C _OX of the gate insulating film and the capacitance C _D of the depletion layer under the gate.

[0013]

[Equation 3]

Here, k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. As is clear from the above equation, C _OX
S ≥ kT ln 10 / q regardless of whether C _D or C _D , and it is difficult to make it 60 mV or less at room temperature.

Due to the above-mentioned phenomenon, the substantial direct current of the semiconductor integrated circuit composed of a large number of MOS transistors remarkably increases. Especially at high temperature operation, V
This problem is exacerbated by the low _T and high S. In the future downsizing era of computers and the like where low power consumption is important, the increase of the subthreshold current is an essential problem.

On the other hand, although it is not for suppressing the increase of the subthreshold current, the eleventh method disclosed in JP-A-2-350
The figure discloses that another transistor is inserted between the source of the MOS transistor of the inverter and the power supply and the gate voltage thereof is controlled to control the operating current of the inverter to control the operating speed. . This is intended to suppress fluctuations in circuit performance due to process variations and temperature changes, and there is no disclosure that solves the above-mentioned problems when MOS transistors are miniaturized and the operating voltage is lowered.

An object of the present invention is to reduce the subthreshold current when a MOS transistor is miniaturized, and
An object is to provide a low power semiconductor integrated circuit.

[0018]

In order to achieve the above object, according to the present invention, a high threshold voltage MOS is provided between the source and the power supply of a low threshold voltage MOS transistor (for example, 0.1 V) forming an inverter. A transistor and a resistor are inserted in parallel, and when the high threshold voltage MOS transistor is on, a large current is supplied via this high threshold voltage MOS transistor, and when it is off, a small current is supplied via the resistor. These currents supply a large current when a high speed operation is required and a small current when a low power consumption is required.

Since high speed operation is required during normal operation, a large current is supplied from the current supply means to the MOS transistor circuit to enable high speed operation. At this time, MOS
Although a direct current flows through the transistor circuit as described above, it is acceptable because it is usually sufficiently smaller than the operating current, that is, the load charging / discharging current.

On the other hand, since low power consumption is required during standby, the supplied current is switched to a small current to suppress the subthreshold current. At this time, since the current is limited, the logic amplitude of the MOS transistor circuit is generally smaller than that at the time of supplying a large current, but it does not matter as long as the logic level can be guaranteed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described in more detail below with reference to the drawings.

[Embodiment 1] First, FIG. 1 is a preferred embodiment for explaining the principle of the present invention.

FIG. 1A is a circuit diagram of an inverter according to an embodiment of the present invention. In the figure, L is a CMOS inverter, which is composed of a P-channel MOS transistor M _P and an N-channel MOS transistor M _N. As described later, the present invention can be applied to not only an inverter but also a logic gate or a logic gate group such as NAND and NOR. However, for simplicity, the case of an inverter will be described here. S
_C and S _S are switches, and R _C and R _S are resistors, and the feature of this embodiment is that switches S _C and S are provided between the power supply terminals V _CL and V _SL of the inverter L and the power supplies V _CC and V _SS , respectively. _{The S} and the resistors R _C and R _S are inserted in parallel, which realizes the reduction of the subthreshold current as described below.

During a time period when high speed operation is required, the switches S _C and S _S are turned on and V _CC and V _SS are directly connected to the inverter L.
(Hereinafter, referred to as high-speed operation mode). M _P , M _N
If the threshold voltage (V _T ) is set low, high speed operation can be achieved. At this time, a subthreshold current flows through the inverter L as described above, but this is not a problem because it is usually sufficiently smaller than the operating current, that is, the load charging / discharging current.

On the other hand, during a time period when low power consumption is required, the switches S _C and S _S are turned off and power is supplied to the inverter through the resistors R _C and R _S (hereinafter referred to as the low power consumption mode). . The voltage drop due to the subthreshold current flowing through the resistor causes V _{CL to} fall below V _CC and V _{SL to} rise above V _SS . As shown in FIG.
Due to this voltage drop, the subthreshold current is reduced by the following two mechanisms. The M _N when the input signal IN is at the low level (V _SS ) will be described, but the same applies to M _P when the input signal IN is at the high level (V _CC ).

[0026] (i) because the source potential V _SL rises, takes a back gate bias _{V BS = V SS -V SL =} -V M,
The threshold voltage rises from V _T0 to V _T1 . The increase in the threshold voltage is

[0027]

[Equation 4]

[0028] This reduces the subthreshold current from I _L0 to I _L1 . The rate of decrease is

[0029]

[Equation 5]

It is Here, K is a substrate effect coefficient.
For example, V _M = 0.3V, K = 0.4√V, S = 100mV / deca
de, if 2ψ = 0.64V, the subthreshold current is 21
%.

[0031] (ii) Since the source potential V _SL rises, the gate-source voltage _{V GS = V SS -V SL =} -V M is negative. As a result, the subthreshold current is further increased to I _L1.
To I _L2 . The rate of decrease is

[0032]

[Equation 6]

It is For example, V _M = 0.3V, S = 100m
If V / decade, the subthreshold current is 0.1%
Is reduced to.

When the effects of (i) and (ii) are combined,

[0035]

[Equation 7]

It becomes For example, if V _M = 0.3V, 0.02%
become. Where V _M is the equation

[0037]

[Equation 8]

The solution of

The MOS transistor M of the inverter L
The back gates of _P and M _N are the respective sources (V _CL ,
Although it may be connected to V _SL ), in order to obtain the effect of (i), it is preferable to connect to V _CC and V _SS as shown in FIG.

FIG. 3 shows the effect of reducing the subthreshold current. This section describes ultra-high-integrated LSI for future ultra-low voltage operation.
Assuming that, the threshold voltage V _T0 when the back gate bias is 0 is 0.05 to 0.15 V, and the total channel width W of the transistors in the off state of the entire LSI is W = 100 m. The larger the resistance, the larger V _{M and the} larger the effect.

However, as shown in FIG. 1B, since the logical amplitude of the output signal OUT is smaller than the logical amplitude of the input signal IN, it is necessary to pay attention to the voltage level of the signal in the multi-stage connection. This will be described later.

Further, the present invention has a function of automatically compensating for variations in threshold voltage. That is, when the threshold voltage subthreshold current is large low voltage drop V _M due to resistance is increased, when the threshold voltage is high and the subthreshold current is small, V _M becomes smaller.
In either case, fluctuations in current are suppressed. As is clear from FIG. 3, the fluctuation of the subthreshold current is smaller as the resistance value is larger. For example, if the resistance value is set to 3 kΩ or more, the variation of the subthreshold current I _L can be suppressed within ± 20% even if the threshold voltage varies by ± 0.05V.

[Embodiment 2] Next, a specific method of realizing the switch and the resistor described in Embodiment 1 will be described. FIG. 4 shows an example in which both the switch and the resistor are realized by MOS transistors.

Switch MOS transistors M _C1 and M
_S1 is a MOS transistor having a large conductance, which corresponds to the switches S _C and S _S of FIG. 1, respectively. In the high speed operation mode, the signal φ _{C is set} to the low level and the signal φ _{S is set} to the high level to turn on M _C1 and M _S1 . φ _C ,
The voltage level of φ _S may be V _SS and V _CC , respectively,
In order to increase the conductance of M _C1 and M _S1 ,
φ _C may be lower than V _SS and φ _S may be higher than V _CC . The voltage for that is given from the outside of the chip or E
It may be generated by a well-known on-chip booster circuit in EPROM or DRAM.

In the low power consumption mode, conversely, by setting φ _C to a high level and φ _S to a low level, M _C1 , M
_S1 turns off. At this time, the current must be surely suppressed. For that purpose, there are the following two methods. The first method is to make φ _C higher than V _CC and φ _S lower than V _SS by an external voltage or an on-chip boost circuit. The second method is to use, as M _C1 and M _S1 , transistors having a higher threshold voltage (more enhancement) than that used in the inverter L. The first method has an advantage that a step for producing transistors having different threshold voltages is unnecessary. On the other hand, the second method is advantageous in terms of area because it does not require a terminal for receiving an external voltage or an on-chip booster circuit.

The MOS transistors M _C2 and M _S2 are MOS transistors having a small conductance and correspond to the resistors R _C and R _S of FIG. 1, respectively. The gates of these transistors are connected to V _SS and V _CC , respectively, and are always on. These transistors do not need to be turned off, so their threshold voltage can be low.

Next, the time zone to which the present invention is applied will be described. FIG. 5 shows an example of the timing of the signals φ _C and φ _S.

FIGS. 5A and 5B show a case where the present invention is applied to a memory LSI. The memory LSI is in an operating state when the chip enable signal CE (complementary signal) is at a low level, and is in a standby state when it is at a high level. In the case of FIG. 5 (a), the signal φ _C becomes low level in synchronization with the fall of CE_, and becomes high level slightly after the rise of CE_. The signal φ _S is the opposite. Therefore, in the figure, the time zone a is in the high-speed operation mode, and the time zone b is in the low power consumption mode. Generally, in a memory device using a large number of memory LSIs, a small number of LSIs are in an operating state, and a large number of LSs are used.
I is in a standby state. Therefore, reducing the power consumption of the LSI in the standby state greatly contributes to the reduction of the power consumption of the entire memory device. The reason for providing the delay from the rise of CE to the low power consumption mode is that LS is in between.
This is because the internal circuit of I is reset.

FIG. 5B shows an example in which the power consumption is further reduced. Here, the high speed operation mode is set only immediately after the change of CE. That is, immediately after CE goes low, data reading / writing is performed, and CE
Immediately after ￣ becomes high level, the internal circuit is reset, so the high-speed operation mode is set in these time zones and the low power consumption mode is set in other time zones. Although not shown here, the high-speed operation mode may be entered when the address signal changes.

FIG. 5C shows an example in which the present invention is applied to a microprocessor. In the normal operation state, the clock CL
K is applied. At this time, the signal φ _C is low level,
φ _S is at a high level, which is a high speed operation mode. When the microprocessor enters the standby state or the data holding state, the clock CLK is stopped and the signal BU goes high. In synchronization with this, φ _C becomes high level and φ _S becomes low level, and the low power consumption mode is set. As a result, the power consumption of the microprocessor is reduced, and it becomes possible to back up for a long time with a small capacity power source such as a battery.

FIG. 6 is an example of a device structure for realizing the circuit of FIG. Polysilicon 130 in this figure,
131, 132, and 133 are M _C2 , M _P , and
Corresponds to the gates of M _N and M _S2 (M _C1 and M _S1 are not listed here).

It should be noted that M _C2 and M _P share the same n-well 101 (connected to V _CC through n + diffusion layer 120). M _N and M _S2 likewise share a p-substrate (connected to V _SS ) 100. As can be seen, connecting the back gate of the MOS transistor to V _CC and V _SS not only achieves the effect of (i) above, but also in terms of layout area, compared to connecting it to the source. It is advantageous.

In the example shown here, the n-well is formed in the p-substrate, but conversely, the p-well may be formed in the n-substrate. Alternatively, ISC SCI, Digest of Technical Papers, 248.
Pages 249, February 1989 (ISSCC Digest of
A triple well structure as described in Technical Papers, pp.248-249, Feb.1989) may be used.

[Embodiment 3] FIG. 7 shows another method of realizing a switch and a resistor. The feature of this embodiment is that a current mirror circuit is used. That is, the MOS transistors M _C2 and M _C3 having the same threshold voltage form a so-called current mirror circuit sharing a gate and a source.
A current proportional to the current source I ₀ flows through _C2 , and its impedance is large. The same applies to M _S2 and M _S3 . Therefore, M _C2 and M _S2 can be regarded as high resistance.
The circuit CS including the current source I ₀ and M _C3 and M _S3 may be shared by a plurality of logic gates.

The current mirror circuit may be not only the circuit shown here but also other circuits. For example, a bipolar transistor may be used instead of the MOS transistor.

As described above, the method of realizing the switch and the resistor can be variously modified. In short, any means may be used as long as it allows a large current to flow during a time period when high speed operation is required and a small current during a time period when low power consumption is required. In the following drawings, for simplicity, the switches and resistors are used as shown in FIG.

[Embodiment 4] The back gate of the MOS transistor of the inverter is not limited to V _CC and V _SS , but may be connected to another power source, and its voltage may be variable. FIG. 8 shows an example thereof. Here, the back gates of M _P and M _N are connected to the power supplies V _WW and V _BB , respectively, and their back gate voltage values are changed during operation and during standby. As for V _BB, the time zone in which high-speed operation is required by shallow V _BB (or in extreme cases slightly positively) that enable high-speed operation by reducing the V _T of M _N. The time zone requiring low power consumption by increasing the V _T of M _N to deepen the V _BB, suppress the subthreshold current. As a result, the effect of (i) above is further enhanced. The V _BB has been described above,
V _WW is the same _except that the polarities of the voltages are reversed. In addition,
This type of back gate voltage generating circuit is disclosed in, for example, ISC SCI, Digest of Technical Papers, pages 254 to 255, 1985.
February (ISSCC Digest of Technical Papers, pp.254-25
5, Feb. 1985).

FIG. 9 is an example of a device structure for realizing the circuit of FIG. Here, the above-mentioned triple well structure is used. The n-well 105 (back gate of P-channel MOS transistor) is connected to V _WW via the n + diffusion layer 120, and the p-well 103 (back gate of N-channel MOS transistor) is connected to V _WW. V _BB via the p + diffusion layer 127
It is connected to the.

This triple well structure has the advantage that the back gate voltage can be set for each circuit because both P-channel and N-channel can be placed in independent wells for each circuit. For example, when a circuit in the operating state and a circuit in the standby state coexist in one LSI, the back gate voltage of the former can be made shallow and the back gate voltage of the latter can be made deep.

[Embodiment 5] Next, the case of an inverter array in which inverters are connected in multiple stages will be described. For simplicity,
First, the principle will be described in the case of two stages.

FIG. 10A is a circuit diagram when the CMOS inverters L ₁ and L ₂ are connected. Switches S _Ci and S _Si and resistors R _Ci and R _Si (i
= 1, 2) has been inserted.

In the high speed operation mode, all four switches are turned on and V _CC and V _SS are directly applied to the inverters L ₁ and L ₂ . If the threshold voltage (V _T ) of the MOS transistor of the inverter is set low, high speed operation can be achieved. On the other hand, in the low power consumption mode, all the four switches are turned off and power is supplied to the inverter through the resistors. Due to the voltage drop caused by the subthreshold current flowing through the resistor, V _CL1 and V _CL2 are lower than V _CC , and V _SL1 and V _SL2 are higher than V _SS .

The first stage inverter L ₁ is shown in FIG.
Similar to the case, the subthreshold current is reduced by the mechanisms (i) and (ii). However, as shown in FIG. 10B, the logical amplitude of the output N ₁ of L ₁ is smaller than the logical amplitude of the input signal IN. That is, IN is at a low level (= V
_{When SS} ), the voltage level of N ₁ becomes V _CL1 , and when IN is at a high level (= V _CC ), the voltage level of N ₁ becomes V _SL1 .
Since this becomes the input of the second stage inverter L ₂ , in order to reduce the subthreshold current of L ₂ , V _CC > V _CL1
It is desirable to set the resistance values such that> V _CL2 and V _SS <V _SL1 <V _SL2 . As a result, L ₂
The subthreshold current is reduced by the mechanisms (i) and (ii). When V _CL1 = V _CL2 and V _SL1 = V _SL2 , the effect (i) can be obtained but the effect (ii) cannot be obtained.

[Embodiment 6] The same applies to the case of the multistage connection shown in FIG. 11A, where V _CC > V _CL1 > V _CL2 >...> V
_CLk , V _SS <V _SL1 <V _SL2 <... <V _SLk is preferable. However, as shown in FIG. 11B, since the logical amplitude becomes smaller for each stage, a level conversion circuit is appropriately inserted to recover the amplitude. In this example, a level conversion circuit LC is added after the k-stage inverter so that the logical amplitude of the output signal OUT becomes the same as that of the input signal IN. This kind of level conversion circuit is described, for example, in Symposium on VLS L.S.K., Digest of Technical Papers, pages 82 to 83, June 1992 (Symposium on VLSI Circ).
uits, Digest of Technical Papers, pp.82-83, June 1
992).

The level conversion circuit LC is unnecessary in high speed operation. Because all the switches are on, V _CL1 = V _CL2 = ... = V _CLk = V _CC , V _SL1 = V
_{This is because SL2} = ... = V _SLk = V _SS and there is no decrease in logic amplitude. Therefore, when operating at high speed, the switch S
Delays can be avoided by turning on _LC and bypassing the level translation circuit.

[Embodiment 7] FIG. 12A shows another example of a multistage connected inverter array. In this example, the switch S _C ,
S _S and resistors R _C and R _S are shared by all the inverters L _{1 to} L _k, and the voltages V _CL and V _SL are common to L _{1 to} L _k . Therefore, as described in the explanation of FIG.
The effect of reducing the subthreshold current by the mechanism of (i) can be obtained, but the effect by (ii) cannot be obtained. Therefore, the effect of reducing the subthreshold current is smaller than that in the previous embodiment.

However, on the other hand, there is an advantage that the layout area of the switch and the resistor can be saved. In addition, FIG.
As shown in (b), the voltage levels of all signals (including input / output signals) are the same, and there is the feature that there is no decrease in logic amplitude as in the previous embodiment. Therefore, there is an advantage that a level conversion circuit is unnecessary and logic such as NAND and NOR can be easily assembled.

[Embodiment 8] Next, the case where the present invention is applied to a general combinational logic circuit will be described.

For example, consider the combinational logic circuit shown in FIG. To apply the present invention to this, first, the logic gates are divided into groups as shown in FIG. In this example, 15 logic gates L _{1 to} L ₁₅ are divided into three groups G ₁ , G ₂ and G _3.
It is divided into In grouping, the output signals of the logic gates included in the i-th group are input only to the logic gates of the (i + 1) th and subsequent groups.

Next, as shown in FIG. 14, a switch and a resistor are inserted between each group and the power source. The logic amplitude of the output signal of the logic gate is 1 as in the case of FIG.
Since each stage becomes smaller, the level conversion circuit groups GC ₁ and GC ₂ are inserted to restore the amplitude as shown in FIG.
Although not shown, the level conversion circuit groups GC ₁ and GC ₂ may be bypassed during high speed operation as in the case of FIG.

One of the characteristics of this embodiment is that the logic gates included in the same group share the resistance with the switch. In the example of FIG. 13, the three inverters included in the group G ₁ include the switches S _C1 and S _S1 and the resistor R 1.
_C1 and R _S1 are shared.

Another feature of this embodiment is that the groups before and after the level conversion circuit share the switch and the resistance. That is, the groups G ₁ and G _{k + 1} include the switches S _C1 , S _S1 and the resistors R _C1 , R _S1 and the groups G ₂ and G _k , respectively.
_{k + 2} includes switches S _C2 , S _S2 and resistors R _C2 , R _S2 , ...
.., groups G _k and G _2k share switches S _Ck , S _Sk and resistors R _Ck , R _Sk , respectively.

By thus sharing the switch and the resistance with a plurality of logic gates, it is possible to reduce the number of the switch and the resistance as a whole LSI and save the layout area.

[Embodiment 9] FIG. 15 shows another embodiment of the present invention. The embodiment of FIG. 15 differs from the previous embodiments in that voltage limiters (step-down circuit, step-up circuit) VC ₁ , V
That is, C ₂ , ..., VC _k , VS ₁ , VS ₂ , ..., VS _k are used.

When low power consumption is required, the switches T _{C1 to} T _Ck and T _{S1 to} T _Sk are switched to the illustrated side, and power is supplied to the logic gate group by the voltage limiter. The voltage limiters VC ₁ , VC ₂ , ..., VC _k operate as a step-down circuit on the power supply voltage V _CC side, and are lower than V _CC and are almost stabilized internal voltages V _CL1 , V _CL2 , ..., V _CLk. Occurs respectively. On the other hand, VS ₁ , VS ₂ , ..., VS _k are connected to the ground V _SS.
It operates as a booster circuit on the side and generates internal voltages V _SL1 , V _SL2 , ..., V _SLk that are higher than V _SS and are almost stabilized. The generated voltage is V _CC as in the previous embodiment.
＞ V _CL1 ＞ V _CL2 ＞ …… ＞ V _CLk , V _SS <V _SL1 <V _SL2 <
...... <V _SLk is better. A voltage limiter of this type is disclosed in Japanese Patent Laid-Open No. 2-246516.

On the contrary, when a high speed operation is required, the switch is switched to the side opposite to that shown in the drawing, and V _CC , V
_{Apply SS} directly to the group of logic gates to enable high speed operation. At this time, the voltage limiter is not necessary, so the operation may be stopped.

[Embodiments 10 and 11] In the above embodiments, circuits having no feedback such as inverter trains and combinational logic circuits were used, but the present invention can be applied to circuits having feedback. As an example, a case of a latch circuit shown in FIG. 16A in which two NAND gates are combined will be described.

A circuit diagram is shown in FIG. 2 NA
Switches S _C1 , S _S1 , S _C2 , S _S2 and resistors R _C1 , R _S1 , R _C2 , R _S2 are inserted between the ND gates L ₁ and L ₂ and the power supply Vcc and the ground Vss, respectively. V _CL1 ,
V _CL2 falls _below V _CC , V _{SL 1} and V _SL2 rise above V _SS , and the mechanism (i) reduces the subthreshold current.

FIG. 17 shows four M's used to latch information in order to further reduce the subthreshold current.
The threshold voltage V _T of the OS transistors M _P12 , M _P22 , M _N12 , and M _N22 is set to the other MOS transistors M _P11 , M _P21 ,
In this example, the threshold voltage is higher (more enhanced) than that of M _N11 and M _N21 . Another MO to which the input signal is applied
Since the threshold voltage V _T of the S transistors M _P11 , M _P21 , M _N11 and M _N21 remains low, high speed operation is possible.
In this case, the switch and the resistor on the V _SS side are unnecessary. This is because the high threshold voltage V _SS side transistors M _N12 , M
_This is because the current can be reliably suppressed by _N22 .

[Embodiments 12 and 13] In the embodiments so far, the subthreshold current can be reduced regardless of whether the input signal is at a low level or a high level. But the actual L
In SI, the time zone in which the subthreshold current reduction is required, for example, the level of a specific signal in a standby state is often known in advance. In such a case, the subthreshold current can be reduced with a simpler circuit.

FIG. 18 shows the input signal IN in the standby state.
Is an example of a circuit of an inverter array when it is known to be at a low level (“L”). Since IN is low, nodes N ₁ , N ₃ , N ₅ , ... Are high, N ₂ , N ₄ , N ₆ ,.
... becomes low level, M _P2 , M _P4 , ... Of the P channel MOS transistors are off, and M _N1 , M _N3 , ... Of the N channel MOS transistors are off. It is sufficient to insert the switches and resistors only in the sources of these off-state transistors. The subthreshold current flows because it is a transistor in the off state.

As shown in FIG. 19, the switch and the resistor may be shared by a plurality of inverters.

Although these embodiments have the restriction that the level of the input signal must be known, they have the advantage that the subthreshold current can be reduced with a simple circuit. As is clear from comparing FIGS. 18 and 19 with FIG. 11, the number of switches and resistors is reduced, and the level conversion circuit becomes unnecessary.

[Embodiments 14 and 15] If the level of the input signal in the standby state is known not only in the inverter but also in the logic gates such as NAND and NOR, the subthreshold current can be reduced by a simpler circuit. it can.

FIG. 20 shows an example of a 2-input NAND gate, and FIG. 21 shows an example of a 2-input NOR gate. Two input signals IN ₁
When IN and IN ₂ are both low level or both are high level, these gates are substantially equivalent to the inverter, and therefore the method described with reference to FIGS. 18 and 19 can be applied. The problem is when one input is low level (“L”) and the other input is high level (“H”) as shown.

In the case of the NAND gate of FIG. 20, the P-channel MOS transistor M _P12 and the N-channel MOS transistor M _N11 are off, but the output OUT is at a high level, so that the subthreshold current flows in M.
It is _N11 . Therefore, it suffices to insert a switch and a resistor on the V _SS side. On the contrary, in the case of the NOR gate in FIG. 21, it is the P-channel MOS transistor M _P14 that the subthreshold current flows. Therefore, it suffices to insert a switch and a resistor on the V _CC side.

20 and 21 show an example in which the present invention is applied to a 2-input logic gate, the same can be applied to a 3-input or higher logic gate. Of course, the switch and the resistor may be shared with other logic gates.

[Embodiment 16] FIG. 22 shows an example of a circuit in the clock inverter when it is known that the clock CLK ₁ is at a low level and the clock CLK ₂ is at a high level in the standby state. In this case, the MOS transistors M _P16 , M
_Since both _N16 are off, the output OUT will be high impedance and its voltage level will be determined by other circuitry (not shown) connected to OUT. Since the subthreshold current flows in which of the MOS transistors M _P16 and M _N16 depends on the voltage level, in this case, a switch and a resistor may be inserted on both the V _CC side and the V _SS side as shown in the figure.

[Embodiment 17] Even in the case of a general combinational logic circuit, if the level of the input signal is known in advance, the subthreshold current can be reduced by a simpler circuit. The combinational logic circuit shown in FIG. 13 will be described as an example.

FIG. 23 shows an example of the circuit configuration when the inputs IN _{1 to} IN ₆ of this circuit are all known to be low level.
For the inverters L _{1 to} L ₃ , L ₅ and L ₆ , switches and resistors are inserted on the V _SS side of L _{1 to} L ₃ and the V _CC side of L ₅ and L ₆ as in FIGS. 18 and 19. . The NOR gate L ₇ is substantially equivalent to an inverter because all the input signals are low level. Therefore, it suffices to insert a switch and a resistor on the V _SS side. Since one of the input signals of the NOR gate L ₄ is at a low level and the other is at a high level, a switch and a resistor are inserted on the V _CC side as in the case of FIG. 8 NANs
Of the D gates, only L ₁₂ has all three input signals at high levels and is equivalent to an inverter. Therefore, a switch and a resistor are inserted on the V _CC side. In other NAND gates, low level and high level input signals coexist, so that a switch and a resistor may be inserted on the V _SS side as in FIG.

As is apparent from the above description, a switch and a resistor may be inserted on the side of V _SS for the logic gate whose output is at the high level, and on the side of V _CC for the logic gate whose output is at the low level. . As shown in FIG. 23, the layout area can be saved by sharing these switches and resistors among a plurality of logic gates.

[Embodiment 18] Even for a circuit having feedback, if the signal level is known in advance, the subthreshold current can be reduced by a simpler circuit. FIG. 24 shows an example applied to the latch of FIG. 16 (a).

In a latch of this type, in the standby state, both the input signals IN ₁ and IN ₂ are normally at a high level, one of the output signals OUT ₁ and OUT ₂ is at a low level, and the other is at a high level. Holds 1-bit information. Figure 2
4 is an example of a circuit configuration when it is known that OUT ₁ is low level and OUT ₂ is high level. NAND gate L
₁ is equivalent to an inverter because the two input signals are both at high level, and a switch and a resistor are inserted on the V _CC side as in FIGS. 18 and 19. NAND gate L ₂ is
Since one of the input signals is at the low level and the other is at the high level, a switch and a resistor may be inserted on the V _SS side as in the case of FIG. Of course, these switches and resistors may be shared with other logic gates.

[Embodiment 19] FIG. 25 is an example in which the present invention is applied to a known data output buffer in a memory LSI or the like. In the standby state, the output enable signal OE is at low level, the outputs of the NAND gates L ₂₁ and L ₂₂ are at high level, and the output of the inverter L ₂₃ is at low level. Therefore, the two MOS transistors M _P20 and M _N20 forming the output stage L ₂₄ are both off, and the output DOUT has a high impedance.

FIG. 23 shows the logic gates L _{21 to} L ₂₃ .
In accordance with the policy described in the above description, the switch and the resistor may be inserted on the V _SS side or the V _CC side. For the output stage L ₂₄ , switches and resistors may be inserted on both the V _CC side and the V _SS side, as in the case of the clock inverter of FIG.

[Embodiment 20] FIG. 26 is an example in which the present invention is applied to a well-known data input buffer in a memory LSI or the like. In the figure, SB is a signal that goes high in the standby state. The outputs of the inverters L ₃₁ and L ₃₂ can be used for controlling the switches as φ _S and φ _C , respectively, as shown in FIGS. 4 and 7. L ₃₃ is a NAND gate, the inputs of which are φ _S and the data input signal D _IN . Since φ _S is at a low level in the standby state, D _IN
Regardless of the above, the output of L ₃₃ is high, and thus the output of the output d _IN of the inverter L ₃₄ is low. on the other hand,
In the operating state, SB is at a low level, so d _IN follows D _IN .

For the NAND gate L ₃₃ and the inverter L ₃₄ , the subthreshold current can be reduced by inserting a switch and a resistor on the V _SS side and the VCC side, respectively. This method cannot be used for the inverters L ₃₁ and L ₃₂ , but the subthreshold current can be reduced by increasing the threshold voltage of the MOS transistor. Since switching between the standby state and the operating state does not often require high speed, a MOS transistor having a high threshold voltage may be used.

The embodiments of FIGS. 18 to 25 have the advantage of being able to reduce the subthreshold current with a simple circuit, but are applicable if the signal level in the time zone where the subthreshold current reduction is required, for example, in the standby state is not known. There is a constraint that you cannot do it. Therefore, at this time, L
It is desirable to have as many levels of nodes in the SI as established. By using the input buffer of FIG. 26, the level of the signal d _{IN at} this time can be fixed at a low level. As a method of determining the level of the signal d _IN , other than this, for example, there is a method of defining a specification that “the data input terminal D _IN is set to a low level (or a high level) in the standby state”. .

Although the data input buffer has been described above, the same applies to the input buffers for address signals and other signals.

The embodiment of FIGS. 18 to 26 is a memory LSI.
It is suitable to be applied to. This is because, in the memory LSI, there are relatively many nodes whose high level or low level is known in the standby state, and the levels of most nodes can be fixed by using the input buffer of FIG. .

The embodiments of FIGS. 25 and 26 can be used not only as an input / output circuit for external terminals of an LSI chip, but also as a driver / receiver for an internal bus of a microprocessor, for example.

[Embodiment 21] The present invention has been so far carried out by CMO.
Although the embodiment applied to the S circuit has been described, the present invention can also be applied to a circuit composed of a single-polarity MOS transistor. FIG. 27 shows an example of a circuit composed of only N-channel MOS transistors. In the figure, PC is a precharge signal, and IN ₁ and IN ₂ are input signals.

In the standby state, that is, in the precharge state,
PC is at high level, IN ₁ and IN ₂ are at low level, and the output OUT is precharged to high level (= V _CC -V _T ). In operation, after the PC goes low, IN
₁ and IN _{2 go} high or stay low. If at least one of IN ₁ and IN ₂ goes high, OUT goes low, and if both stay low, OUT remains high. That is, this circuit is a circuit that outputs NOR of IN ₁ and IN ₂ .

In this circuit, the transistors that are turned off during standby are M _N41 and M _N42 on the V _SS side, and a subthreshold current flows through these transistors. Therefore, to apply the present invention to this circuit, a switch and a resistor may be inserted on the V _SS side as shown in the figure. It is not necessary on the V _CC side.

As described above, the present invention is extremely effective in reducing the power consumption of a MOS transistor circuit and a semiconductor integrated circuit composed of the MOS transistor circuit. Recently, the demand for low power consumption of semiconductor integrated circuits is particularly strong, and for example, Nikkei Electronics September 2, 1991, No. 106.
Pages 111 to 111 describe a microprocessor system having a low power backup mode. In the backup mode, the power consumption is reduced by stopping the clock and stopping the power supply to unnecessary parts. However, even the reduction of the subthreshold current is not considered. The present invention
For example, if applied to a resume circuit (power is supplied even in the backup mode), further lower power consumption can be realized.

[0106]

As described above, according to the present invention,
It is possible to realize a high-speed and low-power-consumption MOS transistor circuit and a semiconductor integrated circuit configured by the MOS transistor circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an inverter according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a principle of reducing a subthreshold current according to the present invention.

FIG. 3 is a diagram showing a subthreshold current reduction effect according to the present invention.

FIG. 4 is a circuit diagram of an inverter according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the timing of signals of the present invention.

FIG. 6 is a diagram showing a device structure of the present invention.

FIG. 7 is a circuit diagram of an inverter according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of an inverter according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a device structure of the present invention.

FIG. 10 is a diagram showing an inverter array according to a fifth embodiment of the present invention.

FIG. 11 is a diagram showing an inverter array according to a sixth embodiment of the present invention.

FIG. 12 is a diagram showing an inverter array according to a seventh embodiment of the present invention.

FIG. 13 is a diagram showing an example of grouping of combinational logic circuits to which the present invention is applied.

FIG. 14 is a diagram showing a combinational logic circuit according to an eighth embodiment of the present invention.

FIG. 15 is a diagram showing a combinational logic circuit according to a ninth embodiment of the present invention.

FIG. 16 is a diagram showing a latch according to the tenth embodiment of the present invention.

FIG. 17 is a circuit diagram of a latch according to an eleventh embodiment of the present invention.

FIG. 18 is a circuit diagram of an inverter array according to a twelfth embodiment of the present invention.

FIG. 19 is a circuit diagram of an inverter array according to a thirteenth embodiment of the present invention.

FIG. 20 is a circuit diagram of a NAND gate according to Example 14 of the present invention.

FIG. 21 is a circuit diagram of a NOR gate according to Embodiment 15 of the present invention.

FIG. 22 is a circuit diagram of a clock inverter according to a sixteenth embodiment of the present invention.

FIG. 23 is a circuit diagram of a combinational logic circuit according to a seventeenth embodiment of the present invention.

FIG. 24 is a circuit diagram of a latch according to an eighteenth embodiment of the present invention.

FIG. 25 is a circuit diagram of an output buffer according to a nineteenth embodiment of the present invention.

FIG. 26 is a circuit diagram of an input buffer according to a twentieth embodiment of the present invention.

FIG. 27 is a circuit diagram of an NMOS dynamic circuit according to a working example 21 of the invention.

FIG. 28 is a circuit diagram of a conventional CMOS inverter.

FIG. 29 is a diagram showing a subthreshold characteristic of a MOS transistor.

[Explanation of symbols]

L, L _{1 to} L _k ... Logic gate, G _{1 to} G _k ... Logic gate group, S _C , S _{C1 to} S _Ck , S _S , S _{S1 to} S _Sk ... switch,
R _C , R _{C1 to} R _Ck , R _S , R _{S1 to} R _Sk, ... Resistors.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-53-122354 (JP, A) JP-A-2-179121 (JP, A) JP-A-2-122726 (JP, A) JP-A-4- 156007 (JP, A) JP-A-53-15056 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/00 H03K 19/0948

Claims (8)

(57) [Claims] 1. A a first operating potential point, and a second operating potential point, the 1MOS transistor and the second conductivity type of a first conductivity type having a source-drain path between the first node and the second node, respectively Second MOS transistor, the first MOS transistor and the second MOS transistor are connected in series, the input node is connected to the gates of the first MOS transistor and the second MOS transistor, and the output node thereof is the first MOS transistor. A plurality of logic gates connected to the drain of the second MOS transistor, a first control circuit arranged between the first operating potential point and the first node, and receiving a first control signal; A second control circuit arranged between the operating potential point and the second node and receiving a second control signal; The output node of one of the logic gates of the gates is connected to the input node of another logic gate of the plurality of logic gates, and the first control circuit is configured so that the first control signal is in the first state. Occasionally, a current having a first current value is allowed to flow between the first operating potential point and the second operating potential point via the first node, and when the first control signal is in the second state. Limiting the current flowing between the first operating potential point and the second operating potential point via the first node to a second current value smaller than the first current value, and the second control circuit: When the second control signal is in the first state, a current having a third current value is allowed to flow between the first operating potential point and the second operating potential point via the second node, and When the second control signal is in the second state, the second node Then, the current flowing between the first operating potential point and the second operating potential point is limited to a fourth current value smaller than the third current value, and when the first control signal is in the first state, The second control signal takes the first state, the second control signal takes the second state when the first control signal is in the second state, and the absolute values of the threshold voltages of the first and second MOS transistors are 0. A semiconductor integrated circuit having a voltage of 4 V or less. 2. The first and second MOS transistors according to claim 1, wherein each of the first and second MOS transistors is a transistor through which a subthreshold current flows even when the gate-source voltage thereof is 0 V, and the first control signal is the first In the state, the charge / discharge current of the load flows between the first operating potential point and the second operating potential point via the first node, and when the first control signal is in the second state, The first control circuit limits the subthreshold current flowing between the first operating potential point and the second operating potential point via the first node to the second current value, and the second control signal is the first In the state, a charge / discharge current of the load flows between the first operating potential point and the second operating potential point via the second node, and when the second control signal is in the second state, 2 Control circuit is above The semiconductor integrated circuit limits the subthreshold current flowing between the second node via the first operating potential point and the second operating potential point to the fourth current value. 3. The first control circuit according to claim 1, wherein the first control circuit includes a third MOS transistor, the second control circuit includes a fourth MOS transistor, and the gate of the third MOS transistor includes the first MOS transistor. A control signal is received, a source / drain path of the third MOS transistor is connected between the first node and the first operating potential point, and a gate of the fourth MOS transistor receives the second control signal. A semiconductor integrated circuit in which a source / drain path of the 4MOS transistor is connected between the second node and the second operating potential point. 4. A first conductivity type first MOS transistor having a first operating potential point, a second operating potential point, and a source / drain path between the first node and the second operating potential point, respectively. A plurality of second conductivity type second MOS transistors, wherein the first MOS transistor and the second MOS transistor are connected in series, and the first output node is connected to the drains of the first MOS transistor and the second MOS transistor. A first logic gate, a third MOS transistor of a first conductivity type and a fourth MOS transistor of a second conductivity type each having a source / drain path between a second node and the first operating potential point; The transistor and the fourth MOS transistor are connected in series, and the second output node of the transistor is connected to the third MOS transistor. A plurality of second logic gates connected to the drain of the fourth MOS transistor, a first control circuit arranged between the first operating potential point and the first node, and receiving a first control signal, A second control circuit arranged between the second operating potential point and the second node and receiving a second control signal, wherein the first control circuit is configured such that when the first control signal is in the first state. , Allowing a current having a first current value to flow between the first operating potential point and the second operating potential point via the first node, and when the first control signal is in the second state, The current flowing between the first operating potential point and the second operating potential point via the first node is limited to a second current value smaller than the first current value, and the second control circuit is When the second control signal is in the first state, via the second node A current of three current values is allowed to flow between the first operating potential point and the second operating potential point, and when the second control signal is in the second state, the second control signal is passed through the second node. A current flowing between one operating potential point and the second operating potential point is limited to a fourth current value smaller than the third current value, and the plurality of first logic gates have the first control signal of the second control value.
In the state, it takes a first logic value, and the plurality of second logic gates receive the second control signal in the second
A semiconductor integrated circuit having a second logical value different from the first logical value when in the state, and the absolute value of the threshold voltage of the first to fourth MOS transistors is 0.4 V or less. 5. The transistor according to claim 4, wherein each of the first to fourth MOS transistors is a transistor through which a subthreshold current flows even if the gate-source voltage thereof is 0 V, and the first control signal is the first In the state, the charge / discharge current of the load flows between the first operating potential point and the second operating potential point via the first node, and when the first control signal is in the second state, The first control circuit limits the subthreshold current flowing between the first operating potential point and the second operating potential point via the first node to the second current value, and the second control signal is the first In the state, a charge / discharge current of the load flows between the first operating potential point and the second operating potential point via the second node, and when the second control signal is in the second state, 2 Control circuit is above The semiconductor integrated circuit limits the subthreshold current flowing between the second node via the first operating potential point and the second operating potential point to the fourth current value. 6. The first control circuit according to claim 1 or 2, wherein the first control circuit comprises a fifth MOS transistor, the second control circuit comprises a sixth MOS transistor, and the gate of the fifth MOS transistor comprises the first MOS transistor. The fifth MOS transistor receives a control signal, the source / drain path of the fifth MOS transistor is connected between the first node and the first operating potential point, and the gate of the sixth MOS transistor receives the second control signal. A semiconductor integrated circuit in which the source / drain path of the 6MOS transistor is connected between the second node and the second operating potential point. 7. The method according to claim 4, wherein the first operating potential point is higher in potential than the second operating potential point, and the level of the first logical value is the second logical value. Integrated circuit lower than the level of. 8. The method according to claim 4, wherein the first operating potential point is lower in potential than the second operating potential point, and the level of the first logical value is the second logical value. Integrated circuit higher than the level of.