JP4147174B2 - Power-on reset circuit - Google Patents

Description

  The present invention relates to a power-on reset circuit that is mounted on a semiconductor device and outputs a reset signal for resetting an internal circuit when power is turned on.

  In a circuit for storing volatile data such as a flip-flop with reset, it is necessary to set the circuit to an initial value when the power is first turned on. In addition, in an LSI having a nonvolatile memory such as a ferroelectric memory, it is necessary to be in a reset state when the power is turned on in order to prevent destruction of stored data due to unstable control signal input or data signal input when the power is turned on. . FIG. 14 shows the basic configuration of a conventional power-on reset circuit used for this purpose.

  The conventional power-on reset circuit shown in FIG. 14 includes a series circuit of a charging capacitor C0 and a current source IS0, and an inverter INV0 having a connection point between the charging capacitor C0 and the current source IS0 as an input. In order to set the level of the power-on reset signal POR when outputting the reset to the low level, the inverter INV1 is connected to the next stage of the inverter INV0. The current source IS0 controls a time constant for charging the charging capacitor C0 when the power is turned on, and may be constituted by a transistor or a resistance element.

  Immediately after the power is turned on, the potential of the upper electrode A point of the charging capacitor C0 is low level, the output C point of the inverter INV0 is high level, the power-on reset signal POR that is the output of the inverter INV1 is low level, and the reset is output Has been. Thereafter, the charging capacitor C0 is charged by the current source IS0, and when the potential at the upper electrode A point of the charging capacitor C0 becomes higher than the threshold voltage of the inverter INV0, the output of the inverter INV0 becomes low level, and the inverter INV1 The power-on reset signal POR, which is an output of, becomes a high level, and the reset is released.

  The power-on reset circuit shown in FIG. 14 has a minimum basic configuration, and many techniques for improving characteristics are disclosed. If the power-on reset signal POR at the time of reset output may be at a high level, the subsequent inverter INV1 is not necessary.

  For example, in the technique disclosed in Patent Document 1, in order to reliably output a reset signal even when the power source is turned on and off in a short time, an improvement for discharging the charge accumulated in the charging capacitor has been made. .

In the technique disclosed in Patent Document 2, a power supply voltage setting circuit is provided, and after the power supply voltage reaches the set voltage, charging to the charging capacitor is started so that the power supply voltage rises slowly. Also, the reset signal is surely output.
Japanese Unexamined Patent Publication No. 2003-110414 (page 3, FIG. 1) JP-A-9-270686 (page 3-4, FIG. 1)

  However, in the power-on reset circuit shown in FIG. 14, since the potential at the upper electrode A point of the charging capacitor C0 rises gently, a through current flows through the inverter INV0 for a long time. For this reason, the power consumption by a through current increases. Also, in applications such as a non-contact IC card that rectifies electromagnetic waves to obtain an internal power supply, the power supply voltage may drop sharply and the power-on reset signal POR may chatter.

  This problem will be described with reference to FIG. FIG. 15 shows a change in potential at each point (power supply VDD, point A, point C, POR) of the power-on reset circuit shown in FIG. 14 and a current flowing through the inverter INV0. FIG. 16 shows the DC characteristics of the output voltage with respect to the input voltage of the inverter circuit and the current flowing through the inverter.

  When the power is turned on, charging of the charging capacitor C0 by the current source IS0 is started, and the potential of the upper electrode A point rises according to a certain time constant as shown in FIG. The potential at the output C point of the inverter INV0 changes from the high level to the low level according to the output voltage characteristics shown in FIG. At this time, a current flows through the inverter INV0 according to the current characteristics shown in FIG. In order to ensure a sufficient reset period as in T0, it is necessary to sufficiently increase the time constant τ0 for charging the charging capacitor C0. Then, the potential at the upper electrode A point of the charging capacitor C0, that is, the input voltage of the inverter INV0 gradually rises as indicated by at1, and the output voltage of the inverter INV0 gradually falls as indicated by at2. , DC current flows through the inverter INV0 for a long time like T1.

  The power-on reset circuits in Patent Document 1 and Patent Document 2 described above have a configuration in which the capacitor upper electrode of the time constant circuit is connected to the input of the inverter, and includes the same problem.

  The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a power-on reset circuit capable of reducing current consumption.

  The present invention takes the following means in order to solve the above problems.

  (1) As a first solution, a power-on reset circuit according to the present invention includes a series circuit of a current source and a charging capacitor inserted between a power source and ground, and an upper electrode of the charging capacitor. An inverter connected to output a power-on reset signal, a delay switching element inserted between the upper electrode of the charging capacitor and the input of the inverter, and a gate for controlling the gate potential of the delay switching element And a potential control means.

  The effect | action by this structure is as follows. If the charging time constant of the charging capacitor is sufficiently increased in order to ensure a sufficient reset period, the potential of the upper electrode of the charging capacitor rises gradually. As it is, the time for the current to flow through the inverter becomes long. Therefore, a delay switching element whose gate is controlled by the gate potential control means is added. Until the charging capacitor is charged and the potential of the upper electrode thereof exceeds a predetermined value, the delay switching element is in an OFF state, and an increase in the input potential of the inverter is suppressed. When the potential of the upper electrode of the charging capacitor exceeds a predetermined value, the delay switching element is inverted to the ON state, and the input potential of the inverter starts to rise.

  As described above, the delay switching element ensures a predetermined delay between the start of charging the charging capacitor and the start of the rise of the inverter input potential. The input potential of the inverter rises sharply. As a result, the time during which current flows through the inverter is shortened, and the current flowing through the inverter can be reduced.

  (2) As a second solution, a power-on reset circuit according to the present invention is the above-described first solution, wherein the gate potential control device is configured as follows. The gate potential control means comprises a current source and one or more voltage drop diodes connected in series between a power supply and ground, and a connection point between the current source and the voltage drop diode or the diode One of the connection points is connected to the gate of the delay switching element.

  An output voltage of the gate potential control means is generated by a voltage drop corresponding to the forward voltage of the voltage drop diode, and this output voltage is applied to the gate of the delay switching element. When the potential of the upper electrode of the charging capacitor becomes higher than the voltage obtained by adding the threshold voltage of the delay switching element to the output voltage of the gate potential control means, the delay switching element becomes conductive. By adjusting the number of voltage drop diodes or the forward voltage, the conduction timing of the delay switching element can be easily controlled.

  (3) As a third solution, a power-on reset circuit according to the present invention is the above-described second solution, wherein the gate potential control unit is configured as follows. That is, instead of the voltage drop diode, a transistor having a gate and a drain connected thereto is used.

  By connecting the gate and drain of a transistor to each other, the transistor can be formed into a diode. By using transistors as constituent elements, the degree of integration of the semiconductor device is increased.

  (4) As a fourth solving means, in the power-on reset circuit according to the present invention, in the second and third solving means, a current blocking switching element is further connected in series to the gate potential control means, and the current The gate of the switching element for interruption is connected to the output of the inverter.

  When the delay switching element is turned on, the output of the inverter is inverted and the reset is released, the current interrupting switching element is interrupted accordingly, and no current flows through the gate potential control means. This can further reduce current consumption.

  (5) As a fifth solution, the power-on reset circuit according to the present invention is the switching circuit for accelerating charging between the upper electrode of the charging capacitor and the power supply voltage in the first to fourth solutions. An element is inserted, and the gate of the charging acceleration switching element is connected to the output of the inverter.

  In the process in which the delay switching element is turned on and the output of the inverter is going to invert, the charging acceleration switching element is turned on, and the charging of the charging capacitor is accelerated accordingly. Therefore, the time during which current flows through the inverter is further shortened, and current consumption can be further reduced. Further, the conduction of the charging acceleration switching element lowers the impedance of the charging path of the charging capacitor, so that the inverter input potential instantaneously follows the power supply fluctuation even when the power supply voltage fluctuates. As a result, chattering of the power-on reset signal that may occur when the power supply fluctuates can be suppressed.

  (6) As a sixth solving means, in the power-on reset circuit according to the present invention, in the first to fourth solving means, a charging acceleration switching element is further inserted between the power source and the input of the inverter. The gate of the switching element for acceleration of charge is connected to the output of the inverter. The operational effect is the same as (5) except that the connection position of the charge accelerating switching element is different from the above (5).

  (7) As a seventh solving means, in the power-on reset circuit according to the present invention, in the first to sixth solving means, a potential stabilizing capacitor is further inserted between the input of the inverter and the ground. Is.

  Since the delay switching element is turned off when the power is turned on, the input potential of the inverter is floating and unstable. Therefore, a potential stabilizing capacitor can be inserted between the input of the inverter and the ground to stabilize the input potential of the inverter.

  (8) As an eighth solving means, the power-on reset circuit according to the present invention is the above first to seventh solving means, further comprising an upper electrode of the charging capacitor and the ground, and the inverter. Discharging switching elements inserted between the input and the ground, respectively, and discharging control means for detecting a decrease in power supply voltage and controlling the gate potentials of both discharging switching elements.

  When the discharge control means detects a drop in the power supply voltage, it conducts both discharge switching elements, discharges the charging capacitor, and discharges and initializes the parasitic capacitance of the inverter input or the potential stabilizing capacitor. As a result, even when the power supply voltage is turned on and off in a short time, the electric charge is sufficiently discharged by the initialization, so that the output operation of the power-on reset signal can be stably started.

  (9) As a ninth solving means, the power-on reset circuit according to the present invention is the charging accelerating switching element according to the eighth solving means, further connected in series between the power source and the input of the inverter. And a switching element for accelerating stop, the gate of the switching element for accelerating charging is connected to the output of the inverter, and the gate of the switching element for accelerating stop is controlled by the discharge control means. .

  Similar to the sixth solving means, the reduction of current consumption can be promoted by shortening the time for the current to flow to the inverter by the action of the charge accelerating switching element. It is possible to instantaneously follow the inverter input potential when the power supply voltage fluctuates, and to suppress chattering of the power-on reset signal that may occur when the power supply fluctuates. Nevertheless, when the power supply voltage is lowered, turning off the acceleration stopping switching element prevents the effect of the charging acceleration switching element, thereby ensuring the initialization by the conduction of the discharging switching element.

  (10) As a tenth solution, the power-on reset circuit according to the present invention may further include a power-on reset circuit between the upper electrode of the charging capacitor and the input of the delay switching element in the eighth and ninth solutions. A charging suppression diode is inserted.

  When the power is turned off and the power supply voltage falls below the threshold voltage of the delay switching element, the charge stored in the charging capacitor is charged to the parasitic capacitance of the inverter input or the potential stabilization capacitor. It can be suppressed by the forward voltage barrier of the suppression diode. Thereby, the input of the inverter is sufficiently discharged even when the power is turned on again, and the output operation of the power-on reset signal can be started stably.

  (11) As an eleventh solution, a power-on reset circuit according to the present invention uses a transistor having a gate and drain connected instead of the charge suppression diode in the tenth solution.

  By connecting the gate and drain of a transistor to each other, the transistor can be formed into a diode. By using transistors as constituent elements, the degree of integration of the semiconductor device is increased.

  (12) As a twelfth solving means, the power-on reset circuit according to the present invention is characterized in that, in the eighth to eleventh solving means, the impedance is further reduced between the upper electrode of the charging capacitor and the input of the inverter. Switching element is inserted, and the gate of the impedance reduction switching element and the output of the inverter are connected.

  In the process in which the delay switching element is turned on and the output of the inverter is going to be inverted, the impedance reduction switching element is turned on and connected in parallel with the delay switching element. As a result, the impedance between the upper electrode of the charging capacitor and the input terminal of the inverter is reduced, and the inversion of the inverter is speeded up. Accordingly, it is possible to further reduce the current consumption by shortening the time during which the current flows through the inverter, and to suppress chattering due to the threshold voltage fluctuation of the inverter when the power supply fluctuates.

  According to the present invention, when the output of the inverter changes by connecting the inverter with the upper electrode of the charging capacitor charged by the current source via the delay switching element controlled by the gate potential control means. The current flowing through can be reduced. Further, chattering of the power-on reset signal due to a change in the threshold voltage of the inverter when the power supply voltage fluctuates can be suppressed.

  Embodiments of a power-on reset circuit according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a power-on reset circuit according to the first embodiment of the present invention. In the power-on reset circuit shown in the figure, a series circuit of a current source IS0 and a charging capacitor C0 is inserted between a power supply VDD and ground, and a delay switching element is provided at the upper electrode A point of the charging capacitor C0. The input B point of the inverter INV0 that outputs the power-on reset signal is connected via the PMOS transistor P0, and the input of the inverter INV1 that outputs the power-on reset signal POR is connected to the output C point of the inverter INV0. The PMOS transistor P0 as a delay switching element has its source connected to the upper electrode A point of the charging capacitor C0, its drain connected to the input B point of the inverter INV0, and the gate potential of the transistor P0 as a gate potential control circuit. 1 to control. The current source IS0 is composed of a resistance element and a transistor. The difference from the conventional circuit shown in FIG. 14 described above is that the transistor P0 whose gate is controlled by the gate potential control circuit 1 between the upper electrode A point of the charging capacitor C0 and the input B point of the inverter INV0. The point is inserted.

  The operation of the power-on reset circuit of this embodiment will be described with reference to FIG. FIG. 2 shows a change in potential at each point (power supply VDD, point A, point B, point C, POR) of the power-on reset circuit shown in FIG. 1, and a current flowing through the inverter INV0.

  Immediately after the power is turned on, the potential of the upper electrode A point of the charging capacitor C0 is low level, the input B point of the inverter INV0 is low level, the output C point of the inverter INV0 is high level, and the power on that is the output of the inverter INV1 The reset signal POR becomes low level, and reset is output.

  Thereafter, the charging capacitor C0 is charged by the current source IS0, and the potential of the upper electrode A point of the charging capacitor C0 gradually rises. The output potential of the gate potential control circuit 1 is VD, and the threshold voltage of the PMOS transistor P0 is Vtp. The PMOS transistor P0 is off until the potential at the point A becomes higher than VD + | Vtp |, and the potential at the point B does not change. When the potential at the point A becomes higher than VD + | Vtp |, the PMOS transistor P0 is turned on, and the point B rapidly rises to a potential of approximately VD + | Vtp |. This is the delay action of the PMOS transistor P0.

  When the potential at point B becomes higher than the threshold voltage of the inverter INV0, the output of the inverter INV0 becomes low level, the power-on reset signal POR that is the output of the inverter INV1 becomes high level, and the reset is released.

  According to the present embodiment, by adjusting the output potential VD of the gate potential control circuit 1 so that VD + | Vtp | becomes higher than the threshold voltage of the inverter INV0, the potential at the point B is reduced by the inverter INV0. The time until it becomes higher than the threshold voltage can be shortened. That is, the charging time constant τ0 of the charging capacitor C0 is sufficiently large to ensure a sufficient reset period as in T0, and the potential at the upper electrode A point of the charging capacitor C0 is gradually increased as indicated by at1. It is rising. Nevertheless, the input point B of the inverter INV0 rises steeply as indicated by at3. As a result, as indicated by T2, the time during which current flows through the inverter INV0 is shortened, and the current flowing through the inverter INV0 can be reduced.

  Further, chattering of the power-on reset signal POR caused by the change of the threshold voltage of the inverter INV0 when the power supply voltage fluctuates can be suppressed. This is effective in ensuring stable operation in applications such as a non-contact IC card that rectifies electromagnetic waves to obtain an internal power supply.

(Embodiment 2)
The second embodiment of the present invention relates to a specific configuration of the gate potential control circuit 1. FIG. 3 is a circuit diagram showing a configuration of a power-on reset circuit according to the second embodiment of the present invention. The gate potential control circuit 1 includes a current source IS1 and two voltage drop diodes D0 and D1 connected in series between the power supply VDD and the ground. The connection point between the current source IS1 and the voltage drop diode D0 is used for delay. In this configuration, the switching transistor is connected to the gate of the PMOS transistor P0.

  In this embodiment, two voltage drop diodes are used, but one or three or more voltage drop diodes may be used. In this embodiment, the output of the gate potential control circuit 1 is a connection point between the series-connected current source IS1 and the voltage drop diode D0, but the other connection point of the series-connected voltage drop diode is used as an output. Also good.

  In the case of the illustrated example, the output voltage VD of the gate potential control circuit 1 is generated by the voltage drop corresponding to the forward voltage of the two voltage drop diodes D0 and D1, and this output voltage VD is applied to the gate of the PMOS transistor P0. ing. When the potential of the upper electrode A of the charging capacitor C0 becomes higher than the voltage VD + | Vtp | obtained by adding the threshold voltage | Vtp | of the PMOS transistor P0 to the output voltage VD of the gate potential control circuit 1, the PMOS transistor P0 Turn on. Adjustment of the number of voltage drop diodes or the forward voltage makes it easy to control the on-timing of the PMOS transistor P0.

(Embodiment 3)
The third embodiment of the present invention also relates to a specific configuration of the gate potential control circuit 1. FIG. 4 is a circuit diagram showing a configuration of a power-on reset circuit according to Embodiment 3 of the present invention. The gate potential control circuit 1 includes a current source IS1, a PMOS transistor P1, and an NMOS transistor N0 connected in series between the power supply VDD and the ground. The gates of the transistors P1 and N0 are connected to the connection point between the transistors P1 and N0. The connection point between the current source IS1 and the PMOS transistor P1 is connected to the gate of the PMOS transistor P0. In FIG. 3 of the second embodiment, this is obtained by using a PMOS transistor P1 and an NMOS transistor N0 in place of the voltage drop diodes D0 and D1, and forming a diode by connecting their gates and drains to each other. Equivalent to.

  In this embodiment, one PMOS transistor and one NMOS transistor are used. However, the number of PMOS transistors and NMOS transistors and the order of connection may be changed. Since the constituent elements are transistors, the degree of integration of the semiconductor device increases.

(Embodiment 4)
In the fourth embodiment of the present invention, the current consumption is further reduced in the second embodiment. FIG. 5 is a circuit diagram showing a configuration of a power-on reset circuit according to the fourth embodiment of the present invention. The difference from the second embodiment shown in FIG. 3 is that a current source IS1 and voltage drop diodes D0 and D1 in the gate potential control circuit 1 are further connected in series to an NMOS transistor N1 as a current cutoff switching element. It is a point that has been. The gate of the NMOS transistor N1 is connected to the output C point of the inverter INV0.

  According to this embodiment, the point A, the point B, and the POR signal are at the low level immediately after the power is turned on, and the point C is at the high level. Therefore, the NMOS transistor N1 is turned on, but the charging capacitor C0 is charged. After the reset signal is released, that is, after the POR signal becomes high level, the point C is at low level and the NMOS transistor N1 is turned off. Thereby, it is possible to prevent the DC current from flowing through the gate potential control circuit 1 after the reset signal is released. Thereby, reduction of current consumption can be promoted.

  In this embodiment, the NMOS transistor N1 is inserted between the voltage drop diode D1 and the ground. However, the NMOS transistor may be inserted at any connection point of the series connection circuit of the current source IS1 and the voltage drop diode. Good. Further, a configuration may be adopted in which a PMOS transistor is inserted instead of an NMOS transistor, and its gate is connected to the output of the inverter INV1.

  The configuration of the present embodiment may be applied to the third embodiment shown in FIG.

(Embodiment 5)
In the fifth embodiment of the present invention, the current consumption is further reduced and the fluctuation of the power supply voltage is dealt with in the second embodiment. FIG. 6 is a circuit diagram showing a configuration of a power-on reset circuit according to the fifth embodiment of the present invention. The difference from the second embodiment shown in FIG. 3 is that a PMOS transistor P2 as a charge accelerating switching element is connected between the power supply VDD and the upper electrode A point of the charging capacitor C0, and the gate of the PMOS transistor P2 is connected. Is connected to the output of the inverter INV0.

  According to this embodiment, after the power is turned on, the charging capacitor C0 is charged, the potential at the point B becomes higher than the threshold voltage of the inverter INV0, and the output of the inverter INV0 becomes low level, the PMOS transistor P2 is turned on. Thus, charging of the charging capacitor C0 is accelerated. As a result, the time during which current flows through the inverter INV0 is further shortened, and current consumption can be further reduced.

  Further, when the PMOS transistor P2 is on, the impedance of the path for charging the charging capacitor C0 is low, so that the potential at the point B immediately follows the power supply fluctuation even when the power supply voltage fluctuates. Therefore, chattering of a power-on reset signal that may occur when the power supply fluctuates can be suppressed.

  Although not shown in this embodiment, a capacitor is connected between the power supply VDD and the PMOS transistor P2 in order to prevent the PMOS transistor P2 from being turned on immediately after the power is turned on. And the point C may be raised.

  The configuration of the present embodiment may be applied to the first embodiment shown in FIG. 1, or may be applied to the third embodiment shown in FIG. 4 and the fourth embodiment shown in FIG.

(Embodiment 6)
The sixth embodiment of the present invention corresponds to a modification of the fifth embodiment. FIG. 7 is a circuit diagram showing a configuration of a power-on reset circuit according to the sixth embodiment of the present invention. The difference from the second embodiment shown in FIG. 3 is that a PMOS transistor P3 as a charge accelerating switching element is connected between the power supply VDD and the input B point of the inverter INV0, and the gate of the PMOS transistor P3 is connected to the inverter INV0. Is connected to the output.

  The effect expected by this embodiment is the same as the effect expected in the fifth embodiment shown in FIG. In other words, the time during which current flows through the inverter INV0 is shortened, and current consumption can be further reduced. Further, chattering of a power-on reset signal that may occur when the power supply fluctuates can be suppressed.

  In order to prevent the PMOS transistor P2 from turning on immediately after the power is turned on, a capacitor is connected between the power supply VDD and the PMOS transistor P3, and when the power supply voltage rises, the point C is coupled with the power supply VDD. You may make it rise.

  The configuration of the present embodiment may be applied to the first embodiment shown in FIG. 1, or may be applied to the third embodiment shown in FIG. 4 and the fourth embodiment shown in FIG.

(Embodiment 7)
The seventh embodiment of the present invention is to further stabilize the operation in the second embodiment. FIG. 8 is a circuit diagram showing a configuration of a power-on reset circuit according to the seventh embodiment of the present invention. The difference from the second embodiment shown in FIG. 3 is that a potential stabilizing capacitor C1 is connected between the input B point of the inverter INV0 and the ground.

  According to this embodiment, when the power is turned on, the potential at the input point B of the inverter INV0 that is in a floating state can be stabilized because the PMOS transistor P0 that is a delay switching element is turned off. As a result, it is possible to prevent the potential from fluctuating due to the coupling of the point B with the power supply voltage due to the parasitic capacitance when the power is turned on and causing malfunction.

  The configuration of the present embodiment may be applied to the first embodiment shown in FIG. 1, or the third embodiment shown in FIG. 4, the fourth embodiment shown in FIG. 5, and the embodiment shown in FIG. You may apply to Embodiment 5 and Embodiment 6 shown in FIG.

(Embodiment 8)
In the eighth embodiment of the present invention, the output operation of the power-on reset signal can be stably started even when the power supply voltage is turned off and on in a short time. FIG. 9 is a circuit diagram showing a configuration of a power-on reset circuit according to the eighth embodiment of the present invention. The difference from the seventh embodiment shown in FIG. 8 is that an NMOS transistor N2 as a discharging switching element for discharging the charge of the charging capacitor C0 when the power supply voltage is lowered is connected between the point A and the ground. Similarly, an NMOS transistor N3 as a discharge switching element for discharging the electric charge of the potential stabilizing capacitor C1 when the power supply voltage is lowered is connected between the point B and the ground, and the gate potentials of both the NMOS transistors N2 and N3 are connected. The discharge control circuit 2 to be controlled is provided.

  The discharge control circuit 2 outputs a high level when detecting a drop in the power supply voltage, turns on the NMOS transistors N2 and N3, and discharges the charge of the charging capacitor C0 and the potential stabilization capacitor C1. According to this embodiment, even when the power supply voltage is turned off in a short time, the charge capacitor C0 and the potential stabilization capacitor C1 are sufficiently discharged, so that the output operation of the power-on reset signal can be stably performed. Can start.

  The configuration of the present embodiment may be applied to the first embodiment shown in FIG. 1, or the second embodiment shown in FIG. 3, the third embodiment shown in FIG. 4, and the embodiment shown in FIG. You may apply to Embodiment 4, Embodiment 5 shown in FIG. 6, and Embodiment 6 shown in FIG.

(Embodiment 9)
In the ninth embodiment of the present invention, in addition to current reduction and chattering suppression, initialization at the time of power supply voltage drop is ensured. FIG. 10 is a circuit diagram showing a configuration of a power-on reset circuit according to the ninth embodiment of the present invention. The difference from the eighth embodiment shown in FIG. 9 is that a PMOS transistor P4 as a charging acceleration switching element and a PMOS transistor P5 as an acceleration stopping switching element are provided between a power supply voltage and an input point B of the inverter. The PMOS transistor P4 is connected in series, the gate of the PMOS transistor P4 is connected to the output of the inverter INV0, and the gate of the PMOS transistor P5 is connected to the output of the discharge control circuit 2.

  The effect of the PMOS transistor P4, which is the charge accelerating switching element, is the same as the effect of the PMOS transistor P3 in the sixth embodiment shown in FIG. 7, and the impedance of the path for charging the charging capacitor C0 is lowered after reset is released. By rapidly charging the charging capacitor C0, the current flowing through the inverter INV0 is reduced and chattering of the power-on reset signal is suppressed.

  When the power supply voltage drop is detected and the output of the discharge control circuit 2 becomes high level, the PMOS transistor P5, which is an acceleration stop switching element, is turned off, so that no current flows through the PMOS transistor P4, and the NMOS transistor N2 , N3 can discharge the capacitor, that is, initialize it reliably.

  The drain of the PMOS transistor P5 may be connected to the upper electrode A of the charging capacitor C0.

(Embodiment 10)
The tenth embodiment of the present invention stably starts the output operation of the power-on reset signal even when the power is turned on again in the eighth embodiment. FIG. 11 is a circuit diagram showing a configuration of a power-on reset circuit according to the tenth embodiment of the present invention. The difference from the eighth embodiment shown in FIG. 9 is that a charging suppression diode D2 is connected between the upper electrode of the charging capacitor C0 and the PMOS transistor P0 which is a delay switching element.

  According to this embodiment, when the power supply is turned off and the power supply VDD becomes equal to or lower than the threshold voltage of the transistor, the charge stored in the charging capacitor C0 is parasitic on the potential stabilizing capacitor C1 or the point B. Can be suppressed by the forward voltage barrier of the charge suppression diode D2. As a result, the input B point of the inverter INV0 is sufficiently discharged even when the power is turned on again, and the output operation of the power-on reset signal can be started stably.

  The configuration of the present embodiment may be applied to the first embodiment shown in FIG. 1, or the second embodiment shown in FIG. 3, the third embodiment shown in FIG. 4, and the embodiment shown in FIG. You may apply to Embodiment 4, Embodiment 5 shown in FIG. 6, Embodiment 6 shown in FIG. 7, and Embodiment 7 shown in FIG.

(Embodiment 11)
The eleventh embodiment of the present invention corresponds to a modification of the tenth embodiment. FIG. 12 is a circuit diagram showing a configuration of a power-on reset circuit according to the eleventh embodiment of the present invention. The difference from the tenth embodiment shown in FIG. 11 is that an NMOS transistor N4 is used in place of the charge suppression diode D2, and the gate of the NMOS transistor N4 is connected to the point A. This corresponds to a diode formed by connecting the gate and drain of the NMOS transistor N4 to each other. The effect expected in the present embodiment is the same as that of the tenth embodiment shown in FIG. 11, and since the constituent elements are transistors, the degree of integration of the semiconductor device increases.

(Embodiment 12)
FIG. 13 is a circuit diagram showing a configuration of a power-on reset circuit according to the twelfth embodiment of the present invention. The difference from the tenth embodiment shown in FIG. 11 is that a PMOS transistor P6 as an impedance reduction switching element is connected between the upper electrode A point of the charging capacitor C0 and the input B point of the inverter INV0, and the PMOS transistor The point is that the gate of the transistor P6 is connected to the output of the inverter INV0.

  According to this embodiment, after the power is turned on, the charging capacitor C0 is charged, the potential at the point A rises, reaches the potential at which the PMOS transistor P0 is turned on, then the potential at the point B rises, and the potential at the point B Becomes higher than the threshold voltage of the inverter INV0 and the output of the inverter INV0 becomes low level, the PMOS transistor P6 is turned on, and the point A and the point B are conductive with low impedance due to the parallel connection with the PMOS transistor P0. To do. If the potential difference between points A and B before conduction is VAB, the potential at point B after conduction is a potential obtained by superimposing the potential divided by VAB by charging capacitor C0 and capacitor C1. As a result, the potential at the point B suddenly becomes higher than the threshold voltage of the inverter INV0, the consumption current is reduced by shortening the time during which the current flows to the inverter INV0, and the chattering is caused by the fluctuation of the inverter threshold voltage when the power supply fluctuates. Can be expected.

  The configuration of the present embodiment may be applied to the first embodiment shown in FIG. 1, or the second embodiment shown in FIG. 3, the third embodiment shown in FIG. 4, and the embodiment shown in FIG. Applied to the fourth embodiment, the fifth embodiment shown in FIG. 6, the sixth embodiment shown in FIG. 7, the seventh embodiment shown in FIG. 8, the eighth embodiment shown in FIG. 9, and the ninth embodiment shown in FIG. May be.

  In any of the above embodiments, the subsequent inverter INV1 may be omitted.

  The power-on reset circuit of the present invention is characterized by preventing a current from flowing through an inverter in the circuit for a long time, and is useful for all semiconductor devices that require a power-on reset. In applications where RF power feeding is performed, such as a non-contact IC card or RFID, it is particularly useful because it can prevent fluctuations in the power source due to large current consumption.

The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 1 of this invention Waveform diagram illustrating the operation of the power-on reset circuit of the first embodiment The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 2 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 3 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 4 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 5 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 6 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 7 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 8 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 9 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 10 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 11 of this invention The circuit diagram which shows the structure of the power-on reset circuit in Embodiment 12 of this invention Circuit diagram showing the configuration of a power-on reset circuit in the prior art Waveform diagram for explaining the operation of a conventional power-on reset circuit The figure explaining the characteristic of the inverter of the power-on reset circuit of a prior art

Explanation of symbols

1 Gate Potential Control Circuit 2 Discharge Control Circuit IS0, IS1 Current Source C0 Charging Capacitor C1 Potential Stabilization Capacitor P0 PMOS Transistor as Delay Switching Element P1 Diodeized PMOS Transistors P2, P3, P4 Charging Acceleration Switching Elements PMOS transistor P5 PMOS transistor as an acceleration stop switching element P6 PMOS transistor as an impedance reduction switching element N0 Diodeed NMOS transistor N1 NMOS transistor as a current blocking switching element N2, N3 NMOS as a discharging switching element Transistor N4 Diode NMOS transistor D0, D1 Voltage drop diode D2 Charge suppression diode INV0, INV1 inverter

Claims (12)

A series circuit of a current source and a charging capacitor inserted between the power source and ground;
An inverter connected to the upper electrode of the charging capacitor and outputting a power-on reset signal;
A delay switching element inserted between the upper electrode of the charging capacitor and the input of the inverter;
A power-on reset circuit comprising gate potential control means for controlling the gate potential of the delay switching element. The gate potential control means includes a current source and one or more voltage drop diodes connected in series between a power supply and ground, and a connection point between the current sources and the voltage drop diodes or between the diodes. The power-on reset circuit according to claim 1, wherein any one of the connection points is connected to a gate of the delay switching element. The power-on reset circuit according to claim 2, wherein a transistor having a gate and a drain connected is used instead of the voltage drop diode. 4. The power-on reset circuit according to claim 2, further comprising a current blocking switching element connected in series to the gate potential control means, wherein a gate of the current blocking switching element is connected to an output of the inverter. 5. . 5. The charging acceleration switching element is inserted between the upper electrode of the charging capacitor and the power source, and the gate of the charging acceleration switching element is connected to the output of the inverter. A power-on reset circuit according to any one of the above. Furthermore, the charge acceleration switching element is inserted between the power supply and the input of the inverter, and the gate of the charge acceleration switching element is connected to the output of the inverter. The power-on reset circuit described in 1. 7. The power-on reset circuit according to claim 1, further comprising a potential stabilization capacitor inserted between the input of the inverter and the ground. Further, a discharging switching element inserted between the upper electrode of the charging capacitor and the ground, and between the input and the ground of the inverter,
The power-on reset circuit according to any one of claims 1 to 7, further comprising discharge control means for detecting a decrease in power supply voltage and controlling the gate potential of the switching elements for both discharges. Further, the charging acceleration switching element and the acceleration stopping switching element connected in series between the power source and the input of the inverter,
A gate of the charging acceleration switching element is connected to an output of the inverter;
The power-on reset circuit according to claim 8, wherein a gate of the acceleration stop switching element is controlled by the discharge control means. 10. The power-on reset circuit according to claim 8, wherein a charge suppression diode is further inserted between the upper electrode of the charging capacitor and the input of the delay switching element. 11. The power-on reset circuit according to claim 10, wherein a transistor having a gate and a drain connected is used in place of the charging suppression diode. Furthermore, the impedance reduction switching element is inserted between the upper electrode of the charging capacitor and the input of the inverter, and the gate of the impedance reduction switching element and the output of the inverter are connected. Item 12. A power-on reset circuit according to any one of Items 11 to 11.

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