JP2006074210A - Reset circuit of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reset circuit avoiding various factors for obstructing sufficient initialization of a semiconductor integrated circuit device when power voltage fluctuates due to power supply and replacement of a power source such as malfunction at power re-supply time by charge remaining in a capacitor in the reset circuit, malfunction due to fluctuation in power voltage, length of rise time and speed and malfunction due to charge which has been already accumulated in the semiconductor integrated circuit device at power-on time. <P>SOLUTION: The reset circuit is provided with: a voltage dividing circuit having a first conduction-type first MOS transistor MP11 of which the one end is connected to a first power terminal VDD and a second conduction-type second MOS transistor MN11 of which the one end is connected to the other end of the first MOS transistor MP11 and of which the other end is connected to a second power terminal VSS; and a CMOS logic circuit INV11 outputting a reset signal based on voltage appearing in a connection point A of the first and second MOS transistors MP11 and MN11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reset circuit, and more particularly to a reset circuit built in a semiconductor integrated circuit device and mainly used for power-on reset.

  FIG. 13 shows an example of a conventional power-on reset circuit. As shown in FIG. 13, a P-type MOS transistor MP1 and a capacitor C are connected in series via a connection node A between the terminal of the high-voltage side power supply VDD and the terminal of the grounded power supply VSS. . Connection node A is connected to power-on reset signal input terminal B of a semiconductor integrated circuit device (not shown) via inverter INV1. The gate terminal of the MOS transistor MP1 is grounded, and the source terminal is connected to the bulk. The MOS transistor MP1 has a channel length longer than the channel width so as to increase the resistance during conduction, and a high-voltage conduction is achieved by applying a VDD voltage to the source terminal and a ground voltage to the gate. It is set to be in a state.

  The operation of the circuit of FIG. 13 will be described below with reference to FIG. In FIG. 14, the solid line indicates the VDD voltage waveform, the alternate long and short dash line indicates the voltage waveform at the connection node A of the circuit of FIG. 13, and the broken line indicates the voltage waveform at the connection node B. Further, it is assumed that the threshold value of logic inversion with respect to the input level of the inverter INV1, that is, the circuit threshold value α is set as the value shown in FIG. 14, and the capacitor C has no accumulated charge in the initial state where it is not connected to the power source. And Therefore, the voltage at the connection node A is also zero at the beginning.

  In FIG. 14, when the VDD voltage rises at t0 by power-on, the VDD voltage rises substantially linearly. The VSS voltage is fixed at zero. Since this VDD-VSS voltage is also applied to the power supply terminal of the inverter INV1, during the period (1) from t0 to t1, the inverter INV1 has an input voltage at that time, that is, a voltage at the connection node A, for example, (1/2). When xVDD is a circuit threshold = α, it is determined that the L level is equal to or lower than the circuit threshold α. As a result, the output voltage of the inverter INV1 becomes H level at the connection node B. Since the H level signal of the connection node B is supplied as a power-on reset signal to the semiconductor integrated circuit device, this period (1) is the power-on reset period of the semiconductor integrated circuit device, and initialization is performed.

  On the other hand, since the P-type MOS transistor MP1 is set so as to have a high resistance even when conducting, the capacitor C is charged slowly, and the voltage at the connection node A is higher than the VDD voltage as shown by a one-dot chain line. It rises nonlinearly with a delay, and reaches the circuit threshold value α of the inverter INV1 at t1. As a result, an H level input is given to the inverter INV1 at time t1, and an inverted output of L level is obtained at the connection node B at the output end. As a result, the reset, that is, initialization at the time of power-on of the semiconductor integrated circuit device is completed.

  In addition, when the power supply is cut off at t2 after the reset operation is completed, the VDD voltage decreases linearly. On the other hand, since the potential of the connection node A is held by the charge of the capacitor C, the source potential of the MOS transistor MP1 becomes lower than the potential of the connection node A. As a result, the charge of the capacitor C is discharged through the MOS transistor MP1, and decreases at a slightly slower rate than the decrease of the VDD voltage. This voltage drop is performed relatively quickly while the gate-source voltage Vgs of the transistor MP1 is greater than the threshold voltage Vth of the MOS transistor MP1, but when the voltage is near the threshold voltage Vth, the voltage drop speed is slowed and then substantially constant. Is held at a voltage of. At this time, the voltage of the connection node A is D as shown in FIG. This is a voltage resulting from the charge remaining in the capacitor C. On the other hand, the power supply voltage VDD continues to decrease at a constant rate and becomes zero at t3.

  In this state, for example, when the power is turned on again at t3, the VDD voltage rises again from zero. However, since there is residual charge in the capacitor C, the voltage at the connection node A is higher than the circuit threshold value α of the inverter INV1. Will rise from. Since this voltage D is supplied as an input voltage to the inverter INV1, there is no period for determining that the input voltage is at the L level when the inverter INV1 is set to the operating state by turning on the power again. It is determined that the input is given. Therefore, the circuit shown in FIG. 13 cannot supply a power-on reset signal to the semiconductor integrated circuit device, resulting in malfunction.

  In addition to these problems, semiconductors at the time of power-on such as problems caused by the length and speed of the rise time of the power supply voltage, problems caused by the remaining and accumulated charge in the semiconductor integrated circuit device itself after power off, etc. There are various problems that adversely affect the resetting of integrated circuit devices.

As a conventional starter circuit or power-on reset circuit when power is turned on, for example, there is one described in Patent Document 1 or Patent Document 2 below. However, even in the circuits disclosed in these patent documents, an effective solution is provided for various problems caused by fluctuations in power supply voltage, rise and fall times, speed, or charges already remaining in the circuit at power-on. It hasn't been done yet.
JP 05-136671 A Japanese Patent Laid-Open No. 06-196989

  SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor integrated circuit device itself at the time of malfunction when power is turned on again due to electric charge remaining in the capacitor in the reset circuit, malfunction due to fluctuations in power supply voltage, rise and fall times, speed, or power on. It is an object of the present invention to provide a reset circuit capable of avoiding various factors that hinder the good initialization of a semiconductor integrated circuit device when the power is turned on or the power is consumed, such as a malfunction caused by charges accumulated in the semiconductor device.

  According to the first embodiment of the present invention, a first conductivity type first MOS transistor having one end connected to the first power supply terminal, one end connected to the other end of the first MOS transistor, and the other end connected to the second power source terminal. And a CMOS logic circuit that outputs a reset signal based on a voltage appearing at a connection node of the first and second MOS transistors. A reset circuit is provided.

  According to the second embodiment of the present invention, a first conductivity type first MOS transistor having one end connected to the first power supply terminal, one end connected to the other end of the first MOS transistor, and the other end connected to the first power supply terminal. A capacitor connected to the two power supply terminals, a CMOS logic circuit that outputs a reset signal based on a voltage appearing at a connection node between the first MOS transistor and the capacitor, and a second conductivity type second circuit connected in parallel with the capacitor. There is provided a reset circuit comprising a 2MOS transistor and a voltage detection circuit for supplying a conduction signal to the gate of the second MOS transistor when the power supply voltage reaches a predetermined value.

  According to the present invention, the power supply is not affected by the residual charge in the circuit, regardless of the fluctuation of the power supply voltage, the rise and fall time, the speed, or the stored charge in the semiconductor integrated circuit device. Even when the power is turned on again, a reset signal can be reliably supplied to the semiconductor integrated circuit device, and a reset circuit that can reliably initialize the semiconductor integrated circuit device when the power is turned on can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 shows the configuration of the reset circuit of the first embodiment. As shown in FIG. 1, a P-type MOS transistor MP11 and an N-type MOS transistor MN11 are connected in series via a connection node A between a high-voltage side VDD power supply terminal and a grounded VSS power supply terminal. Is done. The gate terminal of the MOS transistor MP11 is grounded, and the source terminal is connected to the bulk. The MOS transistor MP11 is formed to have a long channel length with respect to a narrow channel width, and is set to be in a high resistance conductive state by applying a VDD voltage to the source terminal. Similarly, the gate terminal of the MOS transistor MN11 is connected to the connection node A, and the source terminal is connected to the bulk. As will be described later, the MOS transistor MN11 does not conduct until the voltage at the connection node A reaches a predetermined threshold value. After reaching this threshold value, the MOS transistor MN11 conducts and allows a current to flow toward the VSS power supply terminal. The node A operates so as to keep the voltage at a substantially constant value.

  The connection node A is connected to a connection node C serving as a reset signal input terminal of a semiconductor integrated circuit device (not shown) through a CMOS inverter INV11, a connection node B, and a CMOS inverter INV12 in this order. Each of these inverters INV11 and INV12 is an inverter which is a CMOS type logic circuit formed by combining a P-type MOS transistor and an N-type MOS transistor. The front-stage inverter INV11 is a circuit for performing a logical operation based on the voltage at the connection node A to form a reset signal, and the rear-stage inverter INV12 functions as a buffer circuit used as necessary. The circuit shown in FIG. 1 is integrally formed on a semiconductor chip on which a semiconductor integrated circuit device (not shown) is formed.

  The operation of the circuit of FIG. 1 will be described below with reference to FIGS. 2 (a) and 2 (b). In FIG. 2A, the solid line indicates the VDD voltage waveform, the alternate long and short dash line indicates the voltage waveform of the connection node A, the alternate long and two short dashes line indicates the circuit threshold value of the inverter INV11, and the broken line indicates the voltage waveform of the connection node B. The dotted line in FIG. 2B shows the voltage waveform at the connection node C. Further, it is assumed that the voltage at the connection node A is zero at the first power-on.

In FIG. 2A, when the power is turned on at time t0 and the VDD voltage rises, the VDD voltage rises substantially linearly as shown by the solid line. On the other hand, the VSS voltage is held at zero. Although not shown, it is assumed that the power supply voltage of VDD-VSS is also applied to the power supply terminal of the inverter INV11. In the period (11) from t0 to t1, the circuit threshold voltage of the inverter INV11 rises as 1/2 of the VDD power supply voltage as shown by the two-dot chain line, but the voltage at the connection node A is set as an operation threshold, for example. ,
(1/2) × VDD = α
The apparent logical input voltage is at L level. Similarly, since the power supply voltage applied to the inverter INV11 does not reach the H level, the logic output is also held at the L level output state from t0 to t1 as shown by the broken line in FIG. Is done.

  On the other hand, the potential of the connection node A rises as indicated by the alternate long and short dash line through the MOS transistor MP11 set to a high resistance. For this reason, the drain and gate voltages of the MOS transistor MN11 rise. When this voltage reaches the threshold value of the MOS transistor MN11, it becomes conductive. Here, it is assumed that this threshold is set to a value close to α. Therefore, when the MOS transistor MN11 is turned on, the voltage at the connection node A is held at about α. That is, the series circuit of the MOS transistors MP11 and MN11 substantially operates as a resistance voltage dividing circuit, and the voltage at the connection node A finally becomes a divided voltage determined by both resistors and the power supply voltage VDD. That is, the voltage of the node A takes a substantially constant value α before t1 as indicated by the alternate long and short dash line.

  Since the value α is set as the operation threshold value of the inverter INV11, the power supply voltage VDD increases linearly as shown in FIG. 2A, and the circuit threshold value indicated by the two-dot chain line reaches the value α. As a result, at time t1, the inverter INV11 is given a logic input of L level at the normal power supply voltage, and an inverted output of H level is obtained at the connection node B on the output side. Therefore, since the input of the inverter INV12 becomes H level at the connection node C, the output changes to L level as shown in FIG. 2B, and at this time, the power-on reset operation to the semiconductor integrated circuit is completed. . In the period (12) from time t1 to time t3, the conduction resistances of the MOS transistors MP11 and MN11 are held at substantially constant values, and the input level of the inverter INV11 is held at L.

  After t2, the power supply voltage VDD is kept constant. Within this period (12), for example, when the VDD power supply is shut off at t2s, the VDD voltage decreases linearly as shown by the solid line. At the same time, the circuit threshold value of the inverter INV11 also drops as shown by the two-dot chain line. Here, due to the threshold value of the MOS transistor MN11, the voltage at the connection node A is maintained at a substantially constant value for a certain period of time even if the power supply voltage VDD decreases. When the circuit threshold value of the inverter INV11 indicated by the two-dot chain line reaches the value α at t3, the operation threshold value α becomes lower than the voltage of the connection node A, and the inverter input apparently becomes the H level. Therefore, the output voltage of the inverter INV11 changes to the L level as shown by the broken line in FIG. 2A along the supplied VDD voltage. Therefore, the output of the inverter INV12 rises to the H level at time t3 as shown in FIG. The semiconductor integrated circuit is reset again by this H level output. This reset operation starts at t3 in the period (13), and ends at t4 when the VDD voltage becomes substantially zero.

  The operation after t4 is related to the power-on again. The operation in the period (14) from t4 to t5 is the same as the operation in the period (11) at the time of the first input. When the power-on reset operation ends at t5, the output of the inverter INV12 becomes L level, and the operation of the power-on reset circuit is not performed. Note that after t4, the VDD voltage is maintained at a steady value without being cut off after the power is turned on.

  As described above, in the first embodiment, the semiconductor integrated device can be satisfactorily initialized even when the power is turned on without being affected by the residual charge in the circuit even when the power is turned on, turned off, and turned on again. .

Second Embodiment
Next, the circuit configuration of the second embodiment will be described with reference to FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. The embodiment of FIG. 3 differs from the embodiment of FIG. 1 in that another N-type MOS transistor MN12 is connected between the connection node A and the VSS power supply terminal in parallel with the N-type MOS transistor MN11. And that the gate of the MOS transistor MN12 is connected to the connection node B on the output side of the inverter INV11, and the other points are the same. The source of the MOS transistor MN12 is connected to the bulk like the MOS transistor MN11.

  The operation when the power supply VDD-VSS is turned on, off, and turned on again in the circuit of FIG. 3 will be described below with reference to FIGS. 4 (a) and 4 (b). In the circuit of FIG. 3 as well, the circuit threshold value α when the logic of the inverter INV11 is inverted is (1/2) × VDD. After the power is turned on at t0, the circuit threshold value of the inverter INV11 increases in conjunction with the power supply voltage VDD as indicated by a two-dot chain line. It is assumed that the potential of the connection node A in the steady state is set to substantially the same value as the operation threshold value α.

  When power is turned on at time t0 in FIG. 4A, the VDD power supply voltage rises substantially linearly as shown by the solid line. In the case of the circuit of FIG. 3, two MOS transistors MN11 and MN12 are connected in parallel between the connection node A and the VSS power supply. However, the rise in the potential of the connection node A is the same as in the embodiment of FIG. Similarly, it is mainly determined by the MOS transistor MN11. The operation of the MOS transistor MN12 is determined by the output voltage of the inverter INV11, that is, the voltage of the connection node B. In the period (11) up to the time point t1, the output of the inverter INV12 rises together with the VDD power supply voltage as shown in FIG. 4B, as in the embodiment of FIG. What is different from FIG. 1 is the voltage waveform of the connection node A, which will be described below.

  Until the time point t1, the voltage at the connection node A indicated by the alternate long and short dash line is higher than the circuit threshold voltage of the inverter INV11 indicated by the alternate long and two short dashes line, so that it is apparently at the H level, and the output voltage of the inverter INV11 is within the period (11). Held at the L level. Therefore, the output of the inverter INV12 becomes H level during this period (11), and a power-on reset signal is supplied to the semiconductor integrated circuit device as shown by a dotted line in FIG.

  At t1, since the circuit threshold value of the two-dot chain line inverter INV11 reaches α, the output voltage shifts to the H level as shown by the broken line. When the power supply voltage reaches the normal logic operation voltage, the voltage at the connection node B becomes substantially the power supply voltage VDD, and the output of the inverter INV12 also becomes the L level within the period (12) as shown in FIG. 4B. . At the same time, since the H level voltage higher than the threshold voltage is supplied to the gate of the MOS transistor MN12, the MOS transistor MN12 becomes conductive, and the voltage at the connection node A is t1 as shown by the one-dot chain line in FIG. At about VSS power supply voltage. As a result, the input of the inverter INV11 becomes an L level value equal to or lower than (1/2) × VDD, the output is held at the H level, and the output of the inverter INV12 becomes the L level.

  It is assumed that the VDD power supply is cut off at time t2. As a result, the VDD power supply voltage decreases linearly as indicated by the solid line, and the voltage at the connection node B indicated by the broken line also decreases similarly to the VDD power supply voltage.

  At the time t3, in the embodiment of FIG. 1, the output of the inverter INV11 is inverted from the H level to the L level. However, in the embodiment of FIG. 3, the voltage at the connection node A is approximately the VSS voltage, so the inverter INV11 is inverted. However, the voltage at the connection node B similarly decreases until the VDD power supply voltage becomes substantially zero at time t4. Therefore, in the embodiment of FIG. 4, even if the power supply voltage VDD is cut off after the power is turned on, the power-on reset operation is not performed in the periods (12) and (13). When the power supply VDD is turned on again at t4, a power-on reset signal is generated in the period (14) as in the first turning on of the period (11).

<Third Embodiment>
The embodiment shown in FIG. 5 differs from the embodiment shown in FIG. 1 in that a Schmitt inverter SMT1 that is a CMOS Schmitt circuit is used instead of the inverter INV11 connected between the connection nodes A and B in FIG. Only. Other configurations are the same as those in FIG.

  The Schmitt inverter SMT1 has a hysteresis characteristic with respect to its input voltage. For example, it is assumed that the Schmitt inverter SMT1 causes output inversion at the circuit threshold value α when the power supply voltage VDD is increased as shown by the solid line in FIG. After the power-on reset is performed, for example, it is assumed that noise is generated at the VDD power supply terminal and is reduced to the voltage at t3 in FIG. In the case of the inverter INV11 of FIG. 1, inversion occurs here, and a reset signal is generated again. However, since the Schmitt inverter SMT1 is used in the embodiment of FIG. 5, when the voltage drops, the circuit threshold decreases from the time of the voltage rise and operates so that no inversion occurs to a lower voltage. Therefore, even if the power supply voltage VDD temporarily decreases to a voltage corresponding to the value of the power supply voltage VDD at time t3 in FIG. 2A due to noise, it is possible to prevent generation of a useless reset signal.

<Fourth embodiment>
The embodiment shown in FIG. 6 uses a Schmitt inverter SMT1 instead of the inverter INV11 in the second embodiment shown in FIG. Other configurations are the same as those in FIG.

In the case of the embodiment of FIG. 6, even when the power supply voltage VDD temporarily decreases to a voltage similar to that at the time t4 shown in FIG. Generation of useless reset signals can be prevented.

<Fifth Embodiment>
FIG. 7 shows a circuit configuration of still another embodiment. In FIG. 7, a series circuit of a P-type MOS transistor MP11 and an N-type MOS transistor MN11 is connected between the VDD power supply terminal and the VSS power supply terminal as in the embodiment of FIG. The gate, source and bulk of the MOS transistor MP11 are connected to the VDD power supply terminal, the gate is connected to the drain of the MOS transistor MN11, and the bulk is connected to the VSS power supply terminal. Furthermore, a series circuit of another MOS transistor MP12 and a diode DIO is connected in parallel to this series circuit. The source of the MOS transistor MP12 is connected to the VDD power supply terminal and the bulk, and the gate is connected to a connection node D between the drains of the MOS transistors MP11 and MN11. The connection node A between the MOS transistor MP12 and the anode end of the diode DIO is connected to the input terminal of the inverter INV11, and the cathode end of the diode DIO is connected to the VSS power supply terminal. The connection node B on the output side of the inverter INV11 is connected to the power-on reset signal output terminal C via the inverter INV12.

  In this embodiment, when the power is turned on, a voltage having a certain voltage difference from the VDD power supply voltage is generated at the connection node D between the drains of the transistors MP11 and MN11. This voltage has a certain voltage difference from the VDD power supply voltage. Since this voltage is applied to the gate of the transistor MP12, the gate-source voltage Vgs of the transistor MP12 is constant. As a result, the circuit constituted by the transistors MP11, MP12, and MN11 operates as the constant current source Ic. The formed constant current flows from the transistor MP12 through the connection node A through the diode DIO. Therefore, a constant voltage is generated at the connection node A in a steady state and supplied as an input of the inverter INV11.

  Usually, since the MOS transistor and the diode have opposite temperature characteristics, the voltage obtained at the connection node A is not affected by the temperature change.

  In the circuit shown in FIG. 7, when the power supply voltage VDD-VSS is turned on, the voltage indicated by the alternate long and short dash line is applied to the connection node A in the period (11) of FIG. 2A as in the embodiment of FIG. appear. This voltage is supplied to the inverter INV11, and a power-on reset signal is generated at the node C as shown in FIG. 2B when the power is turned on as in the embodiment of FIG. The semiconductor integrated circuit device connected to the node C is initialized by this power-on reset signal.

  Thereafter, the power supply is in a steady state. In this state, when the power supply voltage fluctuates due to an instantaneous power failure phenomenon or disturbance noise in the power supply, a reset signal is generated when the power supply is cut off as shown in the period (13) in FIG. As in (14), the power-on reset signal when the power is turned on again is surely generated. At this time, as described above, since the transistor MP12 and the diode DIO have opposite temperature characteristics, the embodiment of FIG. 7 can obtain a stable circuit operation that is not affected by the temperature change.

<Sixth Embodiment>
In the embodiment shown in FIG. 1, a series circuit of a P-type MOS transistor MP11 and an N-type MOS transistor MN11 is used to generate a constant voltage at the connection node A. However, the transistor MP11 is replaced with a resistance element. It is also possible to do. FIG. 8 shows a circuit configuration of an example of the embodiment, and a resistance element R is connected between the VDD power supply terminal and the connection node A. Other configurations are the same as those of the embodiment of FIG.

  As described above, even when the resistance element R is used as a voltage dividing element, a power-on reset signal can be obtained when the power is turned on as in FIG. 1, and a reset signal can also be formed when the power is turned off.

<Seventh embodiment>
FIG. 9 shows a circuit configuration of still another embodiment. In FIG. 9, the source and bulk of the MOS transistor MP11 are connected to the VDD power supply terminal, the gate is connected to the VSS power supply terminal, and the drain is connected to the VSS power supply terminal via the capacitor C. Here, the capacitance of the capacitor C is set to a small value of 10 pF or less, for example. A connection node A between the transistor MP11 and the capacitor C is connected to the input terminal of the Schmitt inverter SMT1 and the drain of the MOS transistor MN13. A CMOS inverter can be used instead of the Schmitt inverter SMT1. The output terminal of the Schmitt inverter SMT1 is supplied via the connection node B as one input of the CMOS type OR circuit OR1. The source and bulk of the transistor MN13 are connected to the VSS power supply terminal, and the gate is connected to the output terminal VDOUT of the voltage detection circuit VD. This output terminal VDOUT is further connected to the other input terminal of the OR circuit OR1. The output of the OR circuit OR1 is supplied as a reset input of a semiconductor integrated circuit device (not shown).

  In the circuit of FIG. 9, when the power supply VDD-VSS is turned on, the transistor MP11 is brought into a high resistance conductive state because the VSS power supply voltage of the ground potential is supplied to the gate. The capacitor C is charged by the current flowing through the transistor MP11, and the voltage at the connection node A rises.

  Here, when the rise of the VDD voltage is fast, as shown in FIG. 10A, the VDD voltage rises substantially linearly in a short time, for example, about 50 μsec from t0 to t1, and is the highest given by the power supply voltage VDD. Reach voltage value. Thereafter, when the VDD power source is a battery having a relatively small capacity, an operation in the case where the value of the VDD power source voltage gradually decreases as time elapses due to battery consumption will be described.

The voltage at the connection node A rises with a slight delay from the rise of the power supply voltage VDD as indicated by a broken line, and reaches the value α at t1. This value α is, for example, half of the VDD power supply voltage,
(1/2) × VDD = α
And a value substantially equal to the circuit threshold value of the Schmitt inverter STM1.

  Therefore, during the period from t0 to t1, the Schmitt inverter SMT1 determines that the input is L level because the voltage of the connection node A is equal to or less than the circuit threshold value α, and outputs an H level signal to the output terminal B. .

  At this time, when the VDD power supply voltage rises, the voltage detection circuit VD is in an indefinite state whether its output VDOUT becomes H level or L level because the internal state of the circuit is not stable. However, the H level of the connection node B is effective because it is output via the OR circuit OR1. Therefore, the H level signal obtained from the OR circuit OR1 is effective as a reset signal for initializing the semiconductor integrated circuit device.

  For example, as shown in FIG. 10A, the voltage detection circuit VD detects this when the VDD power supply voltage has dropped to a voltage Vd slightly higher than the circuit threshold value α of the Schmitt inverter SMT1 (t2), and outputs an H level output. VDOUT is output. When this H-level output VDOUT is supplied to the gate, the transistor MN13 conducts, discharges the charge in the capacitor C, and the voltage at the connection node A becomes the ground voltage VSS as shown by the broken line in FIG. To fall. The Schmitt inverter SMT1 can quickly output the H level to the connection node B in accordance with the L level, and malfunctions due to the charge remaining in the capacitor do not occur unlike the conventional case. As the reset signal OROUT, as shown in FIG. 10B, since the detection output VDOUT from the voltage detection circuit VD is output via the OR circuit OR1 at the time t2, it can also be used. This reset operation is similarly performed when the VDD power supply is temporarily cut off and the voltage drops below the detection voltage Vd.

  When the worn battery is replaced with a new one and the power is turned on at t3, the VDD power supply voltage rises rapidly to the rated voltage VDD substantially linearly as shown in FIG. Thus, a reset signal is formed in the same manner as from t0 to t1, and is supplied to the semiconductor integrated circuit device.

  Next, with reference to FIG. 11, the operation of the circuit shown in FIG. 9 when the rise after power-on is as slow as about 50 msec will be described. When power is turned on at t1, the VDD power supply voltage rises substantially linearly. At this time, the voltage at the connection node A rises slightly after the charging period of the capacitor C as shown by the broken line in FIG. 11A, but rises at the same speed as the VDD voltage when the charging of the capacitor C is completed. To do. During this time, the rise of the VDD voltage is monitored by the voltage detection circuit VD, and the detection output VDOUT is output until the detection voltage Vd is reached at t1. This detection output VDOUT is obtained as an output OROUT as a reset signal via the OR circuit OR1. The reset is completed when the voltage drops to zero, that is, the VSS voltage at t1.

  The VDD voltage still rises and reaches the rated voltage at t2. During this time, since the detection output VDOUT is not output, the transistor MN13 remains off, and the voltage at the connection node A rises in the same course as the VDD voltage. At this time, the time from turning on the power at t0 to reaching the VDD rated voltage at t2 is as slow as about 50 msec, for example.

  It is assumed that the semiconductor integrated circuit device is lowered to the detection voltage Vd at time t3 due to battery consumption, disturbance noise, or temporary power supply interruption while the semiconductor integrated circuit device is operating at the VDD voltage. The output VDOUT from the voltage detection circuit VD that has detected this is output as a reset signal via the OR circuit OR1. At the same time, the transistor MN13 is turned on by the output VDOUT, the charge of the capacitor C is discharged through the transistor MN13, and the voltage at the connection node A is reduced to the VSS voltage as shown by the broken line in FIG. To do.

  It is assumed that the power is cut off at time t4, the consumable battery is replaced with a new one, and the power is turned on again at time t5. The subsequent increase in the VDD voltage, the output of the reset signal by the output VDOUT from the voltage detection circuit VD until time t6, the stop of the reset signal after t6, etc. are the same as the operation from the time t0 to t1 when the power is first turned on. Become.

<Eighth Embodiment>
The circuit of the embodiment shown in FIG. 12 shows a case where the potential of the VDD-VSS power supply in the embodiment shown in FIG. 9 is reversed. In the embodiment of FIG. 12, the VDD power supply voltage is a ground voltage, and the VSS power supply voltage is a negative voltage with respect to the ground voltage. This voltage is supplied to the circuit of FIG. 12 and also to the semiconductor integrated circuit device to be initialized when the power is turned on.

  In FIG. 12, a capacitor C and an N-type MOS transistor MN11 are connected in series via a connection node A between a grounded VDD power supply terminal and a negative VSS power supply terminal. The gate of the transistor MN11 is grounded and is set to a normally conductive state with a high resistance. The MOS transistor MN13 is connected in parallel with the capacitor C between the VDD power supply terminal and the connection node A, and its bulk is connected to the negative VSS power supply terminal and is always set to an off state. The connection node A is connected to the Schmitt inverter SMT1, and its output is supplied to the OR circuit OR1 via the connection node B. The output VDOUT of the voltage detection circuit VD is supplied to the gate of the transistor MN13 and the OR circuit OR1. The output OROUT of the OR circuit OR1 is supplied as a reset signal to a semiconductor integrated circuit device (not shown).

  Hereinafter, the operation of the embodiment of FIG. 12 will be described. When the power is turned on, the transistor MN11 becomes conductive and the capacitor C is charged to the negative power supply voltage VSS. When the power supply rises slowly, the voltage detection circuit VD operates, the output VDOUT is supplied to the OR circuit OR1, and the output OROUT is output as a reset signal. When the power supply rises quickly, the voltage detection circuit VD cannot respond and the output cannot be used as a reset signal. In this case, the Schmitt inverter SMT1 detects a voltage change at the connection node A as an H level input from the relationship with the circuit threshold, and outputs an L level reset signal via the OR circuit OR1. The voltage detection circuit VD functions with respect to a decrease in the VSS power supply voltage due to battery consumption, noise, and the like, and outputs the detection output Vd as a reset signal as in the embodiment of FIG.

  In the embodiment of FIGS. 9 and 12, the reset signal can be generated without being influenced by the residual charge in the circuit, and the reset signal is generated even when a new battery is inserted when a battery is used as a power source. Such a malfunction that the semiconductor integrated circuit device cannot be initialized because it cannot be performed can be prevented.

The figure which shows the circuit structure of one Embodiment of this invention. FIG. 2 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 1. The figure which shows the circuit structure of other embodiment of this invention. FIG. 4 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 3. The figure which shows the circuit structure of further another embodiment of this invention. The figure which shows the circuit structure of further another embodiment of this invention. The figure which shows the circuit structure of further another embodiment of this invention. The figure which shows the circuit structure of further another embodiment of this invention. The figure which shows the circuit structure of further another embodiment of this invention. FIG. 10 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 9. FIG. 10 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 9. The figure which shows the circuit structure of further another embodiment of this invention. The figure which shows the circuit structure of the conventional power-on reset circuit. FIG. 14 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 13.

Explanation of symbols

  VDD, VSS: power supply terminal, MP11: P-type MOS transistor, MN11 ... N-type MOS transistor, A, B, C ... connection node, INV11 ... CMOS inverter for generating reset signal, INV12 ... CMOS inverter for buffer, MN12 ... N-type MOS transistor, SMT1 ... Schmitt inverter, Ic ... constant current source, MN13 ... discharging N-type MOS transistor, VD ... voltage detection circuit.

Claims (5)

A first conductivity type first MOS transistor having one end connected to the first power supply terminal, and a second conductivity type first MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to the second power supply terminal. A voltage divider circuit having 2MOS transistors;
A CMOS logic circuit that outputs a reset signal based on a voltage appearing at a connection point of the first and second MOS transistors;
A reset circuit comprising:   2. A third MOS transistor of a second conductivity type connected in parallel to the second MOS transistor, wherein a gate of the third MOS transistor is connected to an output terminal of the CMOS logic circuit. The reset circuit described. A first conductivity type first MOS transistor having one end connected to a first power supply terminal;
A capacitor having one end connected to the other end of the first MOS transistor and the other end connected to a second power supply terminal;
A CMOS logic circuit for outputting a reset signal based on a voltage appearing at a connection point between the first MOS transistor and the capacitor;
A second MOS transistor of a second conductivity type connected in parallel with the capacitor;
A voltage detection circuit for supplying a conduction signal to the gate of the second MOS transistor when the power supply voltage reaches a predetermined value;
A reset circuit comprising:   4. The reset circuit according to claim 3, further comprising a logical sum circuit that performs a logical sum operation between the output of the CMOS logic circuit and the output of the voltage detection circuit.   4. The reset circuit according to claim 1, wherein the CMOS logic circuit is a Schmitt circuit having a hysteresis characteristic.

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