JP4919704B2 - Power-on reset circuit - Google Patents

Description

  The present invention relates to a power-on reset circuit that is provided in a semiconductor integrated circuit and outputs a reset signal when power is turned on.

  An internal circuit such as a flip-flop constituting the semiconductor integrated circuit is not determined in its rising state, and therefore needs to be in an initialized state (hereinafter referred to as a reset state) before starting operation. Therefore, conventionally, a semiconductor integrated circuit is provided with a power-on reset circuit for resetting an internal circuit when power is turned on.

  An outline of the configuration of a conventional power-on reset circuit will be described with reference to FIG. This conventional power-on reset circuit 100 has a P-channel MOS transistor (hereinafter referred to as PMOS) 101 having a source connected to the power supply voltage VDD and a gate connected to the ground voltage VSS, a drain of the PMOS 101, and a ground voltage VSS (usually 0). And the first and second inverters 103 and 104 connected to a common connection point (node X) between the PMOS 101 and the capacitor 102. In order to increase the time constant, the PMOS 101 generally has a high resistance. The output terminal of the second inverter 104 is connected to the internal circuit 105, and a reset signal RES is output from the output terminal when the power is turned on.

  Next, the operation of the conventional power-on reset circuit 100 will be described with reference to the waveform diagram of FIG. In FIG. 4, the vertical axis represents voltage and the horizontal axis represents time.

  When the power is turned on, the power supply voltage VDD rises, the PMOS 101 is turned on, a current flows, and the capacitor 102 is charged. The voltage Vx at the node X rises with a delay by a predetermined time constant determined by the PMOS 101 and the capacitor 102.

  During a period when the voltage Vx of the connection node X is lower than the threshold value Vt of the first inverter 103, that is, for a certain period immediately after the power is turned on, a low level (L) reset signal RES is output from the second inverter 104. The reset signal RES is supplied to the internal circuit 105, and the internal circuit 105 is in a reset state.

  As time elapses, the charging voltage of the capacitor 102 increases, and when the voltage Vx of the connection node X becomes higher than the threshold value Vt, the second inverter 104 outputs a high level (H) signal (reset) instead of the reset signal RES. (Release signal) is output, and the reset state of the internal circuit 105 is released.

  In this way, the internal circuit 105 is automatically reset when the power is turned on, and can operate normally.

The above-described technique is described in, for example, the following patent documents.
JP 2002-335148 A

  However, in the case of the above-described conventional power-on reset circuit 100, when power supply is instantaneously interrupted due to a power failure or the like, and then recovered immediately (generally referred to as instantaneous interruption or instantaneous interruption). However, the reset signal RES is not properly output, and the internal circuit 105 is not reset.

  In other words, when the power supply is momentarily interrupted and the level of the power supply voltage VDD becomes equal to or lower than the threshold value of the PMOS 101, the PMOS 101 is turned off and the current path is closed. 0.5 volt) will remain. This residual charge is spontaneously discharged over time, but the residual charge does not escape to the outside when the power supply voltage VDD recovers immediately after the instant interruption. Then, since the voltage Vx of the node X does not drop below the threshold value of the first inverter 103 when the power is restored, the first and second inverters 103 and 104 are not inverted, and as a result, the reset signal RES is not output. Become. In this case, since the internal circuit 105 starts up in an unstable state that is not reset, the possibility of causing a malfunction becomes extremely high.

  Therefore, the present invention is a power-on reset that can reliably output a reset signal not only when the power is turned on, but also when the power supply voltage VDD drops instantaneously and then immediately recovers. An object is to provide a circuit.

The present invention has been made in view of the above problems, and its main features are as follows. That is, a power-on reset circuit according to the present invention is a power-on reset circuit that includes a latch circuit and outputs a reset signal to an internal circuit in accordance with a voltage at an output node of the latch circuit. A first capacitor connected between the first capacitor and a first inverting circuit for supplying an electric charge to the output node when the power supply voltage decreases and inverting an output of the latch circuit , wherein the first inverting circuit comprises: A rectifying element and a first MOS transistor connected between the power supply voltage and the output node of the latch circuit; and a connection node between the rectifying element and the first MOS transistor and a ground voltage. And a second capacitor, and a power supply voltage is applied to the gate of the first MOS transistor .

  In the power-on reset circuit of the present invention, the latch circuit includes a second inverter and a third inverter connected in a ring shape, a connection point between the second inverter and the third inverter, and a ground voltage. A third capacitor is connected between the two.

  The power-on reset circuit according to the present invention includes a first resistance element between the output of the second inverter and the input of the third inverter.

  The power-on reset circuit according to the present invention includes a second inversion circuit that is connected to an input node of the latch circuit and inverts the output of the power-on reset circuit in response to a reset release signal from the internal circuit. Features.

  In the power-on reset circuit according to the present invention, the second inversion circuit includes a second MOS transistor and a second resistance element connected in series between a power supply voltage and a ground voltage, and an input node of the latch circuit. And a third MOS transistor having a gate connected to a connection point between the second MOS transistor and the second resistance element.

  The power-on reset circuit according to the present invention includes an inversion circuit that inverts the output when the power supply voltage instantaneously drops due to a power failure or the like during a normal operation and falls below a predetermined voltage. Therefore, it is possible to reliably output a reset signal at such a momentary interruption (instantaneous power interruption), and the internal circuit can be brought into a reset state.

  Next, a power-on reset circuit according to the best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of this embodiment. Although the signal output from the output terminal Out of the power-on reset circuit may function as a reset signal at a high level (H), in this embodiment, the signal functions as a reset signal at a low level (L). explain.

  This power-on reset circuit mainly includes a first inverter 1 that outputs a reset signal RES, a latch circuit 2, capacitors 3 and 4, a first inversion circuit 5, and a second inversion circuit 6. ing. The output terminal (output terminal Out) of the first inverter 1 is connected to an internal circuit 7 such as a microcomputer.

  The latch circuit 2 is formed by connecting a second inverter 8, a resistor 9, and a third inverter 10 in a ring shape, and its output node A is connected to the input terminal of the first inverter 1. A capacitor 3 is connected between the power supply voltage VDD and a connection point between the output node A and the first inverter 1. A capacitor 4 is connected between a connection point (node B) between the second inverter 8 and the third inverter 10 and the ground voltage VSS. In this way, the latch circuit 2 supplies a high level (H) signal from the output node A to the input terminal of the first inverter 1 in the reset state, and low level (L) in the non-reset state (reset release state). Is supplied to the input terminal of the first inverter 1. That is, it can also be said that the power-on reset circuit of the present embodiment outputs a reset signal or a reset release signal according to the voltage of the output node A of the latch circuit 2.

  The first inversion circuit 5 is connected between the diode 11 and the PMOS 12 connected in series between the power supply voltage VDD and the output node A of the latch circuit 2, and between the connection point (node C) and the ground voltage VSS. The capacitor 13 is provided. The gate of the PMOS 12 is connected to the power supply voltage VDD. Furthermore, the substrate of the PMOS 12 is also connected to the node C.

  One of the features of this embodiment is that the first inversion circuit 5 is provided. The first inverting circuit 5 is charged in the capacitor 13 during normal operation. When the power supply is momentarily interrupted and falls below a predetermined voltage (the threshold value of the PMOS 12), the first inverting circuit 5 is stored in the capacitor 13 on the output node A side. Supply charge. Then, the latch circuit 2 is inverted, and the output of the power-on reset circuit, which has been a high level signal (reset release signal) until then, is inverted to a low level (reset state). As a result, the reset signal RES is reliably output. To do. Note that the first inverting circuit is provided as long as it has a function of inverting the output of the power-on reset circuit by supplying charges to the predetermined part (in this embodiment, the output node A) only when the power supply is momentarily interrupted. It is possible to change the configuration of 5 to a configuration other than the present embodiment.

  The second inversion circuit 6 includes a PMOS 14 and a resistor 15 connected in series between the power supply voltage VDD and the ground voltage VSS, and an NMOS 16 connected in series between the input node E of the latch circuit 2 and the ground voltage VSS. , The gate of the PMOS 14 and a fourth inverter 17 connected to the output terminal thereof. The gate of the NMOS 16 is connected to a connection point (node F) between the PMOS 14 and the resistor 15. The reset release signal CLR output from the internal circuit 7 such as a microcomputer to the reset release state for a predetermined period is supplied to the gate of the PMOS 14 via the fourth inverter 17. The second inversion circuit 6 inverts the output of the latch circuit 2 in response to the reset release signal CLR from the internal circuit 7 at a predetermined voltage or higher when the power is turned on and when the power is restored from an instantaneous interruption, and the power-on reset circuit The output is inverted from a low level (L) reset signal RES to a high level (H) signal. If the output of the power-on reset circuit is inverted according to the reset release signal CLR of the internal circuit 7 (or other external circuit) as described above, the configuration of the second inversion circuit 6 is implemented in this embodiment. It is possible to change to a configuration other than the form.

  Next, the operation of the power-on reset circuit of this embodiment will be described. First, the operation when the power is turned on will be described. When the power is turned on, the voltage at the output node A of the latch circuit 2 is pulled up to the power supply voltage VDD by the capacitor 3 and the node B is pulled to the ground voltage VSS by the capacitor 4. That is, a high level (H) is held at the output node A, and a low level (L) is held at the node B. Then, the input terminal of the first inverter 1 becomes high level (H), and when the voltage of the output node A becomes equal to or higher than a predetermined value (threshold value of the first inverter 1), the first inverter 1 (output terminal) A low level (L) reset signal RES is output from Out). Then, when the internal circuit 7 recognizes the reset signal RES, the reset state is established.

  After the internal circuit 7 recognizes the reset signal RES, an oscillation circuit (for example, the RC oscillation circuit 20) provided in the internal circuit 7 is activated and counts for a predetermined period. Further, in order to confirm that the oscillation circuit oscillates stably, the timer circuit 21 counts for a predetermined period, and then each program of the internal circuit 7 is started. That is, the period during which the oscillation circuit and the timer circuit are counting is a period during which the reset state is held (reset period). Further, the timer output is latched by the latch circuit 22, and when the reset period ends, the internal circuit 7 outputs a high level (H) reset release signal CLR.

  The reset release signal CLR is applied to the gate of the PMOS 14 via the fourth inverter 17, thereby turning on the PMOS 14. Subsequently, the voltage at the connection node F rises and the NMOS 16 is turned on, and the voltage at the output node A of the latch circuit 2 is pulled to the ground voltage VSS side and latched to the low level (L). Then, the output from the first inverter 1 (output terminal Out) is inverted from the reset signal RES (low level) to the reset release signal (high level), and the reset state is released. At this time, the second inverter 8 and the NMOS 16 pull the level of the node E, but due to the presence of the resistor 9, the level of the node E is easily lowered to the ground voltage VSS side due to IR drop. That is, the resistor 9 makes it easy to invert the output of the latch circuit 2 after the reset release signal CLR is output from the internal circuit 7.

  Even if the reset release signal CLR is output from the internal circuit 7 due to a malfunction before the reset signal RES is output in a low voltage state immediately after the power is turned on, the impedance of the PMOS 14 is much higher than the impedance of the resistor 15. Therefore, the voltage at the node F does not rise and the NMOS 16 is not turned on. Therefore, the latch circuit 2 is not inverted.

  Next, the operation during the normal operation of the power-on reset circuit of this embodiment will be described. Since the PMOS 12 is off during normal operation, the first inversion circuit 5 is also off. Further, since the reset release signal CLR is not output from the internal circuit 7, the second inverting circuit 6 is also turned off. The output node A of the latch circuit 2 is latched at the low level. For this reason, the power-on reset circuit of the present embodiment has no current path during normal operation and consumes no current.

  In the normal operation, the first inverting circuit 5 charges the capacitor 13 via the diode 11. Note that the voltage at the node C is lower than the power supply voltage VDD by the voltage drop of the diode 11.

  Next, the operation of the power-on reset circuit according to the present embodiment at the time of instantaneous power interruption will be described with reference to FIG. In FIG. 2, the vertical axis represents voltage and the horizontal axis represents time.

  When a power supply interruption (instantaneous power interruption) occurs, the power supply voltage VDD decreases as shown in FIG. 2, and the voltage Vout of the output terminal OUT and the voltage Vb of the node B both decrease. Here, even if the power supply voltage VDD continues to decrease and becomes lower than the voltage Vc at the node C, the decrease in the voltage Vc is suppressed by the rectifying action of the diode 11.

  Then, when the power supply voltage VDD further decreases and becomes equal to or lower than the threshold value of the PMOS 12 (about 0.5 volts in this simulation), the first inversion circuit 5 operates. That is, the PMOS 12 is turned on, and the charge charged in the capacitor 13 flows into the output node A side. Note that since the power supply voltage VDD is lowered, the driving capability of the second inverter 8 is lowered, and the current flowing from the PMOS 12 side to the node A side is dominant. As a result, the low level (L) voltage Va at the output node A rises and the latch circuit 2 is inverted. As a result, a high level (H) voltage is supplied to the input terminal of the first inverter 1, the first inverter 1 is inverted based on this, and Vout becomes the ground voltage VSS (0 volt).

  In this way, the power-on reset circuit outputs the low level (L) reset signal RES instead of the high level (H) reset release signal, and the internal circuit 7 enters the reset state. If the first inverting circuit 5 does not exist, the voltage Va at the output node A does not rise from the low level to the high level (H) as shown in FIG. 2, and the reset signal is not output.

  As time further elapses, the power supply voltage VDD once falls to zero volts, and then the power supply recovers, and then the power supply voltage VDD starts to rise. When the internal circuit 7 recognizes that the reset state is sufficient by the RC circuit 20 and the timer circuit 21 described above, a reset release signal CLR is output from the internal circuit 7, the PMOS 14 is subsequently turned on, and the voltage of the node F Vf rises. Then, the NMOS 16 is turned on, and the voltage Va of the output node A is inverted to a low level (L) correspondingly, and the first inverter 1 is also inverted to output a high level signal (reset release signal) from the output terminal Out. ) Is output. Subsequent circuit operations are the same as those in the normal operation described above.

  As described above, the power-on reset circuit according to the present embodiment includes an inverting circuit that inverts the output before the instantaneous power interruption when the voltage is lower than a predetermined voltage (the threshold value of the PMOS 12). Therefore, even when the power supply voltage drops due to an instantaneous interruption and then recovers, it is possible to reliably output the reset signal instead of the reset release signal. In addition, there is no problem of non-output of a reset signal due to residual charge that has occurred in a conventional power-on reset circuit. Accordingly, it is possible to output a reset signal both when the power is turned on and when the power is interrupted, thereby preventing malfunction of the internal circuit.

  Furthermore, as described above, the power-on reset circuit of the present embodiment realizes a low-power consumption power-on reset circuit because current consumption during normal operation is suppressed.

  Needless to say, the present invention is not limited to the above-described embodiment, and the design can be changed without departing from the gist thereof. Specifically, for example, by adjusting the transistor size of the PMOS 12, it is possible to adjust the start timing of the supply of charge from the first inversion circuit 5 to the node A.

It is a circuit diagram explaining the power-on reset circuit which concerns on embodiment of this invention. It is a wave form diagram explaining operation | movement of the power-on reset circuit which concerns on embodiment of this invention. It is a circuit diagram explaining the conventional power-on reset circuit. It is a wave form diagram explaining operation | movement of the conventional power-on reset circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st inverter 2 Latch circuit 3 Capacitor 4 Capacitor 5 1st inversion circuit 6 2nd inversion circuit 7 Internal circuit
8 Second inverter 9 Resistance 10 Third inverter
11 Diode 12 P-channel MOS transistor
13 Capacitor 14 P-channel MOS transistor 15 Resistor 16 N-channel MOS transistor 17 Fourth inverter 20 RC circuit 21 Timer circuit 22 Latch circuit 100 Power-on reset circuit 101 P-channel MOS transistor 102 Capacitor 103 First inverter 104 First Inverter 2 2 Internal circuit RES Reset signal CLR Reset release signal Out Output terminal VDD Power supply voltage VSS Ground voltage

Claims (6)

A power-on reset circuit comprising a latch circuit and outputting a reset signal to an internal circuit in accordance with a voltage at an output node of the latch circuit;
A first capacitor connected between a power supply voltage and the output node;
A first inversion circuit that supplies electric charge to the output node when the power supply voltage decreases and inverts the output of the latch circuit;
The first inversion circuit includes a rectifier element and a first MOS transistor connected between a power supply voltage and an output node of the latch circuit;
A second capacitor connected between a connection node between the rectifying element and the first MOS transistor and a ground voltage, and a power supply voltage is applied to the gate of the first MOS transistor A featured power-on reset circuit. Power-on reset circuit according to claim 1, characterized in that the output node and the input terminal of said latch circuit comprises a first inverter connected, a reset signal from said first inverter is outputted. In the latch circuit, a second inverter and a third inverter are connected in a ring shape, and a third capacitor is connected between a connection point between the second inverter and the third inverter and a ground voltage. The power-on reset circuit according to claim 1 or 2 . The power-on reset circuit according to claim 3 , further comprising a first resistance element between an output of the second inverter and an input of the third inverter. Is connected to an input node of said latch circuit, according to claim 1 to claim 4, characterized in that it comprises a second inverting circuit for inverting the output of the power-on reset circuit in response to the reset release signal from the internal circuit A power-on reset circuit according to any one of the above. The second inverting circuit includes a second MOS transistor and a second resistance element connected in series between a power supply voltage and a ground voltage;
A third MOS transistor connected between the input node of the latch circuit and the ground voltage and connected to the connection point between the second MOS transistor and the second resistance element and the gate thereof; The power-on reset circuit according to claim 5 .

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