JP2002100973A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power-on reset circuit, which can surely reset a logic circuit using a method, where a drop in a power-supply potential Vcc is detected and a power-on reset signal is raised again, after the power supply potential has been dropped. SOLUTION: The drop in the power-supply potential is detected by a potential-drop detection part, and an output at a level L is supplied to the gate of a P-channel transistor 7. The transistor 7 is turned on. The latch of a first inverter 2 and that of a second inverter 3 are inverted, and the power-on reset circuit is set to an initial state. Thereby, when the power-supply potential is dropped, the power-on reset signal POR is re-started, and a reset period is installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power-on reset circuit that outputs a reset signal when power is turned on.

[0002]

2. Description of the Related Art A logic circuit such as a flip-flop constituting an integrated circuit has to be reset before starting operation because the rising state of the logic circuit when power is turned on is not determined. For this reason, a power-on reset circuit that automatically generates a reset signal when power is turned on is provided inside the integrated circuit.

FIG. 4 is a circuit diagram showing a conventional power-on reset circuit, and FIG. 5 is a waveform diagram showing its operation. The power-on reset circuit includes a first capacitor 1,
It comprises a second capacitor 4, a first inverter 2, a second inverter 3, an N-channel transistor 5, and a potential detector 6.

A first capacitor 1 is connected between a power supply and a node A. The second capacitor 4 is connected between the ground point and the node B. The first inverter 2 has an input side connected to the node A and an output side connected to the node B. The second inverter 3 has the input side connected to the node B and the output side connected to the node A, contrary to the first inverter 2.

The N-channel transistor 5 is connected between the ground point and the node A, and has a gate connected to the potential detector 6. The driving capability of the N-channel transistor 5 is set to be larger than the driving capability of the transistor forming the inverter 3. The potential detector 6 is connected to the node A
The N-channel transistor 5 is turned on and off in accordance with the potential change of the N-channel transistor. The potential detection unit 6 includes, for example, a plurality of resistors 6a connected in series between the node A and a ground point,
And 6b, and by these resistors 6a and 6b,
The potential V _R obtained by dividing the potential difference between the potential V _{A of the} node A and the ground potential V _GND is applied to the gate of the N-channel transistor 5. The change in the potential V _B at the node B is outputted as the power-on reset signal POR.

The above operation of the power-on reset circuit is described as follows.
This will be described with reference to FIG. Here, it is assumed that the power supply potential Vcc changes from the ground potential V _{GND to} V _MAX at the time of rising. Normally, the ground potential V _GND is 0V. In an initial state before power-on, a power supply potential Vcc, the node potential V _A of A, node all potential V _B is the ground potential V _GND of B.

When the power is turned on at timing t0, the power supply potential Vcc starts to rise as shown in FIG. With the rise of the power supply potential Vcc, the potential VA of the node _A also starts rising as shown in FIG. At this time, the potential V _B at the node B, as shown in FIG. 5 (3), is maintained at the ground potential V _GND.

[0008] Potential V_AIs (R1 + R2) · Vtn / R2
(I.e., the divided potential V _RBut N channel
Reaches the threshold value Vtn of the type transistor 5), N channel
The transistor 5 starts to turn on. Where R1, R2
Is the resistance value of the resistors 6a and 6b. At this time, N Chan
The driving capability of the second inverter 3 is
Potential is set higher than_AIs shown in Fig. 5 (2)
Start to fall as shown in. Then, the potential V of the node A_A
Is reduced to the threshold value Vi1 of the first inverter 2.
At the timing t2, the first inverter 2 inverts the output.
And the potential V of the node B _BStart to launch. This node B
Potential V_BIs the power-on reset signal POR
Yes, ground potential V_GNDIs maintained during the period t0 to t2,
Period. That is, the timing from the rise of the power supply
The initial state is completed in a period until t2.

[0009] In the timing t3 when the potential V _B reaches the threshold Vi2 of the second inverter 3 in a Node B, a second inverter 3 inverts the output, stable first and second inverters 2 and 3 State. Power-on reset signal
The logic circuit receiving the POR is in a state where the reset has been released, and becomes operable.

[0010]

A logic circuit that repeats a predetermined operation may malfunction when the power supply potential Vcc decreases. In such a case, it is necessary to provide a reset period again to reset the logic circuit. However, a power-on reset circuit described above, when the power supply potential Vcc does not drop to near ground potential V _GND, the first and second inverters 2 and 3 does not reverse, it is impossible to provide a reset period. Therefore, the power supply potential Vc
When c drops halfway, there is a problem that the logic circuit malfunctions but the reset is not applied. Therefore, an object of the present invention is to provide a power-on reset circuit that can detect a decrease in the power supply potential Vcc and reliably reset a logic circuit.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a first capacitor having one terminal connected to a first potential, and an input terminal connected to the other of the capacitors. A first inverter connected to the terminals of
A second inverter connected in parallel and in the opposite direction to the first inverter; a second inverter having one terminal connected to the input side of the second inverter and the other terminal connected to the second potential; 2 capacitor, a one conductivity type transistor connected between the output side of the second inverter and a second potential, and the one conductivity type transistor turned on in response to the input side of the first inverter. A first detecting unit to be connected, a reverse conductivity type transistor connected between the input side of the first inverter and a first potential, and turning on the reverse conductivity type transistor in response to the first potential. And a second detection unit.

[0012]

FIG. 1 is a circuit diagram showing a power-on reset circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation thereof. In this figure, first and second capacitors 1 and 4, first and second inverters 2,
3, N-channel type transistor 5, and potential detector 6
Is the same as that of each unit shown in FIG. 4, and outputs the potential VB of the node _B as the power-on reset signal POR.

A feature of the present invention is that a P-channel transistor 11 and a potential drop detector 12 are provided so that the power-on reset signal POR falls even when the power supply potential Vcc drops halfway. It is in.

The P-channel transistor 11 is connected between the power supply and the node A, and has a gate to which the control potential V _D supplied from the potential drop detector 12 is applied. The driving capability of the P-channel transistor 11 is set to be larger than the driving capability of the transistor constituting the second inverter 3. Potential drop detection unit 12 detects a drop in the power supply potential Vcc, on the P-channel transistor 11, and outputs the control potential V _D to control the off.

The operation of the power-on reset circuit according to the present invention will be described with reference to FIG. Until the timing t0 to t3, the potential change of the power supply potential Vcc, the node potential V _A of A, Node B potential V _B (the power-on reset signal POR) is identical to that shown in FIG. The potential V _D output from the potential drop detection unit 12 at the timing t0 to t3, the power supply potential Vc
It rises slightly later than the rise of c, and finally rises to a potential V1 lower than the power supply potential Vcc. The control potential V _D, in a period during which the power supply potential Vcc is maintained at V _MAX, as shown in FIG. 2 (4), is maintained at a potential V1.

At timing t4, the power supply potential Vcc is low.
When the voltage drops, the potential drop detection unit 12 detects a drop in the power supply potential Vcc.
Is detected, and as shown in FIG._DGround
Potential V _GNDPull down close. That is, the potential drop detector
12 indicates that the power supply potential Vcc is equal to the ground potential V_GNDI have to go down
The control potential V_DTo the ground potential V_GNDPull down close
Things. At timing t5, the power supply potential Vcc
When it begins to rise, the control potential V_DAlso started to rise
Confuse. At this time, the control potential V_DIs shown in FIGS. 2 (1) and 2 (4)
As shown, the power supply potential
Stand up.

[0017] is the potential difference between the control potential V _D and the power supply potential Vcc,
When the P-channel transistor 11 is turned on at the timing t6 when the threshold voltage Vtp of the P-channel transistor 11 becomes larger than the threshold value Vtp, the P-channel transistor 1
1, the power supply potential Vcc is supplied to the node A. Here, than the driving capability of the transistors constituting the second inverter 3, due to the high driving capability of the P-channel transistor 11, the potential V _A of the node A, starts to increase as shown in FIG. 2 (2) . Then, at timing t7 when the potential _VA reaches the threshold value Vi1 of the first inverter 2, the first
Is inverted, the potential V _{B of the} node B is inverted.
(Power reset signal POR) starts to drop.

[0018] The timing t8 when the divided potential V _R of the potential detecting section 6 reaches the threshold Vtn5 the N-channel-type transistor 5
, The N-channel transistor 5 starts to turn on. Here, the N-channel type transistor 5 is set to have a higher driving capability than the transistor constituting the second inverter 2, and as shown in FIG.
The potential _VA is reduced to the ground potential _VGND . Then, at timing t9 when lowered to the threshold Vi1 of a transistor potential V _A constitutes a first inverter 2, the output of the first inverter 2 is inverted, the potential V _B starts to rise. Then, the potential V _B is, at the timing t10 to reach the threshold Vi2 of the second inverter 3, second inverter 3 inverts the output, the first and second inverters 2 and 3 and a stable state . Therefore, the power-on reset signal POR is maintained at the ground potential V _GND during the period t8 to t9.
After resetting again, after timing t10, the logic circuit receiving the power-on reset signal POR is brought into an operable state.

FIG. 3 is a circuit diagram showing an example of the configuration of the potential drop detector 12 of FIG. The potential drop detection unit 12
First to fifth transistors 21, 22, 23, 24, 2
6 and a capacitor 25.

The first transistor 21 is of an N-channel type, and has a source and a gate connected to a power supply, respectively. The second transistor 22 is a P-channel type,
And the gate is connected to the ground point. Capacitor 25 is connected between the ground point and node C. Third transistor 23
Is an N-channel type, and a source and a gate are respectively connected to a power supply. The fourth transistor 24 is of a P-channel type, is connected between the third transistor and the node D, and has a gate connected to a ground point. The fifth transistor 26 is of an N-channel type, is connected between the node D and a ground point, and has a gate connected to the node C. The driving ability of the fifth transistor 26 is set sufficiently smaller than the driving ability of the third and fourth transistors 23 and 24. Then, the potential V _D of the node D, a control potential is supplied to the gate of the P-channel-type transistor 11 shown in FIG.

Here, it is assumed that the power supply potential Vcc changes from the ground potential V _{GND to} V _MAX at the time of rising. Normally, the ground potential V _GND is 0 V, and the power supply potential Vcc, the potential V _{A of} the node _A , and the potential of the node B before the power is turned on.
V _B , the potential V _{C of} the node _C , and the potential V _{D of the} node D are equal to the ground potential V
_GND . The threshold value of the first transistor 21 is Vt1, the threshold value of the third transistor 23 is Vt3,
The threshold of the transistor 24 is Vt4, and the threshold of the fifth transistor 26 is Vt5.

When the power supply potential Vcc rises and the power supply potential Vcc exceeds the threshold value Vt1, the first transistor 21
Turns on and the capacitor 25 is charged, the node C
The potential V _C of becomes V _C ≒ Vcc-Vt1. Here, the threshold value Vt1 of the first transistor 21 and the fifth transistor 2
Since the threshold value Vt5 of 6 is set to satisfy Vt5 <Vcc-Vt1, the fifth transistor 26 is turned on after the capacitor 25 is charged. When the power supply potential Vcc exceeds the threshold value Vt3, both the third transistor 23 and the fourth transistor 24 are turned on. Driving ability of the fifth transistor 26 is a third transistor 23, as compared with the driving capability of the fourth transistor 24, because it is set sufficiently small, the potential V _D of the node D, V _D ≒ Vcc-
Vt3 (that is, the above-described potential V1 becomes V1ccVcc−Vt3). At this time, the potential V _D is the power supply potential Vcc than rises, starts to rise with a delay. Therefore, the power supply potential Vc
While c maintains the V _MAX, supplying a potential V _D as a control potential to the gate of the P-channel transistor 11 (FIG. 1). Here, the control voltage V _D is, because it is larger than Vcc-Vtp, and turns off the P-channel transistor 11.

In this state, when the power supply potential Vcc decreases and Vcc <Vt3 + Vt4, the third transistor 2
Third, one of the fourth transistors 24 is turned off. Thus, the current supply path from the power supply to the node D is shut off. On the other hand, since the potential of the node C is held by the capacitor 25, the fifth transistor 26 remains on. Accordingly, the node D via the fifth transistor 26 is grounded, the control voltage V _D is, the ground potential V
_Pulled down to _GND .

[0024] Once when reduced supply potential Vcc rises, but rises in response thereto the potential V _D of the node D,
Since the fifth transistor 26 is on, it rises more slowly than the power supply potential Vcc as shown in FIG.
At timing t6 shown in FIG. 2, the potential difference between the power supply potential Vcc and the control voltage V _D reaches the threshold Vtp of the P-channel-type transistor 11 shown in FIG. 1 (i.e., V _D ≒ Vcc-Vt
And the 3-Vtp), to turn on the P-channel transistor 11, and supplies the control potential V _D to the gate of the P-channel transistor 11. Such a potential V _{D of the} node _D
Due to the delay in the rise of
A reset period can be provided.

The control voltage V _D rises, the potential difference between the power supply potential Vcc and the control voltage V _D is, becomes smaller than the threshold Vtp of the P-channel transistor 11, P-channel transistor 11 is turned off. After this, the power supply potential Vcc
Rises to V _MAX , the first inverter 2 and the second inverter 3 shown in FIG. 1 enter a stable state. Therefore, the logic circuit receiving the power-on reset signal POR
The state becomes the same as the initial state, and the operation becomes possible.

[0026]

According to the power-on reset circuit of the present invention, the logic circuit receives the power supply potential Vcc is repeated a predetermined operation, after being reset, even when the power supply potential Vcc is not lowered to the ground potential V _GND, A drop in the power supply potential Vcc is detected, a reset period is provided again, and the logic circuit can be reset. Thus, the logic circuit can be reset in response to a decrease in the power supply potential Vcc, which is effective in preventing a malfunction of the logic circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power-on reset circuit of the present invention.

FIG. 2 is a waveform chart showing an operation of the power-on reset circuit of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a potential drop detection unit.

FIG. 4 is a circuit diagram showing a configuration of a conventional power-on reset circuit.

FIG. 5 is a waveform chart showing an operation of a conventional power-on reset circuit.

[Explanation of symbols]

1, 4, 25: Capacitor 2, 3: Inverter 5, 11, 21, 22, 23, 24, 26: Transistor 6: Potential detector 12: Potential drop detector

Claims (4)

[Claims] 1. A first capacitor having one terminal connected to a first potential, a first inverter having an input connected to the other terminal of the capacitor, and a first inverter connected in parallel to the first inverter. A second inverter connected in the reverse direction, a second capacitor having one terminal connected to the input side of the second inverter and the other terminal connected to a second potential, A transistor of one conductivity type connected between the output side of the inverter and the second potential;
A first detection unit that turns on the one-conductivity-type transistor in response to an input side of the inverter, and a reverse-conduction-type transistor connected between the input side of the first inverter and a first potential; A second detection unit for turning on the reverse conductivity type transistor in response to a first potential, wherein a reset signal is obtained from an output side of the first inverter. 2. The first detecting section includes a plurality of resistors connected in series between an input side of the first inverter and a second potential, and the voltage is divided by the plurality of resistors. 2. The power-on reset circuit according to claim 1, wherein a potential is applied to a gate of said one conductivity type transistor. 3. The second detection unit includes a first transistor of one conductivity type, a source and a gate each connected to a first potential, and a first transistor connected in series to the first transistor, and a gate connected to the first transistor. A second transistor connected to the second potential, a capacitor connected between the second transistor and the second potential, and a source and a gate each connected to the first potential.
A third transistor of one conductivity type connected to the potential of
A fourth transistor of the opposite conductivity type, connected in series to the third transistor and having a gate connected to a second potential, connected between the fourth transistor and a second potential, A fifth transistor of one conductivity type connected between the second transistor and the capacitor, wherein the potential between the fourth transistor and the fifth transistor is set to the opposite conductivity type. 2. A power-on reset circuit according to claim 1, wherein the power-on reset circuit is supplied to the gate of the power-on reset circuit. 4. The power-on reset circuit according to claim 3, wherein the driving capability of the fifth transistor is smaller than the driving capabilities of the third and fourth transistors.