JP2008092271A - Delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a delay circuit which can produce an output signal with a desired delay amount of time even if pulse width of the input signal is short. <P>SOLUTION: The delay circuit includes a first flip-flop to which an input signal is input from the set input, a first inverter which inverts an input signal, a second flip-flop to which an output signal from the first inverter is input from the set input, a first delay generating circuit which inputs an output signal from the first flip-flop to make the input signal delay and outputs the signal delayed to the reset input of the first flip-plop, a second delay generating circuit which inputs an output signal from the second flip-flop to make the input signal delay and outputs the signal delayed to the reset input of the second flip-plop, and a third flip-flop which inputs an output signal from the first delay generating circuit from the set input. Then, the first and second delay generating circuits perform a delaying operation in response to charging to a capacitor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a delay circuit used in a semiconductor integrated circuit that delays a signal in accordance with charge / discharge using a capacitor, and particularly to obtain an output signal with a desired delay even when the pulse width of the input signal is short. The present invention relates to a delay circuit that can be used.

  FIG. 16 is a circuit diagram showing a delay circuit generally used in a CMOS semiconductor integrated circuit or the like (see, for example, Patent Document 1). This delay circuit includes inverters 1 to 4 connected in series between an input and an output, and a capacitor 5 having one end connected to a connection point a between the inverter 2 and the inverter 3 and the other end grounded.

  FIG. 17 is a timing chart for explaining the operation of the delay circuit shown in FIG. The input signal that has reached the connection point a has a gradual potential transition due to the action of the capacitor 5 and takes a predetermined time to reach the threshold potential of the inverter 3 in the subsequent stage, which becomes a delay time.

JP-A-2005-198240

  However, when the pulse width of the input signal is shorter than the delay time in the delay circuit, the potential transition is canceled before the potential transitions to the threshold potential of the inverter 3 at the connection point a. As a result, there is a problem that the input signal disappears in the delay generation circuit section (FIG. 17).

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an output signal having a desired delay by preventing the disappearance of the signal even when the pulse width of the input signal is short. A delay circuit that can be obtained is obtained.

  The delay circuit according to the present invention includes a first flip-flop that inputs an input signal from a set input, a first inverter that inverts the input signal, and a second input that receives an output signal of the first inverter from the set input. A flip-flop, a first delay generation circuit unit that inputs an output signal of the first flip-flop, delays it and outputs it to the reset input of the first flip-flop, and an output signal of the second flip-flop A second delay generation circuit unit that outputs a delayed output to the reset input of the second flip-flop, and an output signal of the first delay generation circuit unit is input from the set input, and the output of the second delay generation circuit unit A third flip-flop that inputs a signal from a reset input, and the first and second delay generation circuit sections perform a delay in accordance with charging of the capacitor. Other features of the present invention will become apparent below.

  According to the present invention, an output signal with a desired delay can be obtained even when the pulse width of the input signal is short.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a delay circuit 100a according to the first embodiment of the present invention. The delay circuit 100a includes a first flip-flop 11, a first inverter 12, a second flip-flop 13, a first delay generation circuit unit 14a, a second delay generation circuit unit 15a, 3 flip-flops 16. Note that the first to third flip-flops are all RS flip-flops, and when the set input S and the reset input R are both “H”, the output Q is set priority to output “H”. .

  The first flip-flop 11 receives the input signal IN from the set input S1. Then, the first inverter 12 inverts the input signal IN. The second flip-flop 13 receives the output signal of the first inverter 12 that is a signal having a phase opposite to that of the input signal from the set input S2. Then, the first delay generation circuit unit 14a receives the output signal of the first flip-flop 11 as an input, delays this signal, and outputs it to the reset input R1 of the first flip-flop 11. The second delay generation circuit unit 15a receives the output signal of the second flip-flop 13 as an input, delays this signal, and outputs it to the reset input R2 of the second flip-flop 13. The third flip-flop 16 receives the output signal of the first delay generation circuit unit 14a from the set input S3, receives the output signal of the second delay generation circuit unit 15a from the reset input R3, and outputs the output Q3. Outputs an output signal OUT.

  The first delay generation circuit unit 14a is a capacitor in which one end is connected to a connection point a1 of the inverters 17 to 20 connected in series between the input and the output and the inverter 18 and the inverter 19, and the other end is grounded. 21. The second delay generation circuit unit 15a is a capacitor having one end connected to the inverters 22 to 25 connected in series between the input and the output, and a connection point a2 between the inverter 23 and the inverter 24 and the other end grounded. 26. The first and second delay generation circuit units 14a and 15 perform delays according to the charging of the capacitors 21 and 26, respectively. In FIG. 1, the inverters 18 and 23 are formed of CMOS, and the current drive capability on the PMOS side is suppressed from the NMOS side. By doing so, the charging time of the capacitor becomes longer than the discharging time, and the rising time of the signal delay time given by the first and second delay generation circuit units 14a and 15a becomes longer than the falling time. Is set to

  FIG. 2 is a timing chart for explaining the operation of the delay circuit 100a shown in FIG. First, when IN is “L” and R1 is “L”, Q1 is “L”, the connection point a1 is “L”, and S3 is “L”. On the other hand, Q2 is “H”, the connection point a2 is “H”, and R3 is “H”.

  Next, when IN changes from “L” to “H”, Q1 becomes “H”, and thus the capacitor 21 is charged. When the potential of the connection point a1 exceeds the threshold potential of the inverter 19, R1 and S3 become “H”. On the other hand, since Q2 becomes “L”, the capacitor 26 is quickly discharged. When the potential at the connection point a2 falls below the threshold potential of the inverter 24, R2 and R3 become “L”.

  To summarize the operation of the flip-flop 16, when IN is “L”, S3 is “L”, R3 is “H”, and Q3 is “L”. When IN changes from “L” to “H”, R3 quickly changes from “H” to “L”, so S3 changes to “L”, R3 also changes to “L”, and Q3 remains “L”. do not do. After that, when the capacitor 21 is charged and the potential at the connection point a1 exceeds the threshold potential of the inverter 19, S3 becomes “H”, R3 becomes “L”, and Q3 changes from “L” to “H”. That is, after IN changes from “L” to “H”, the capacitor 21 is delayed by the charging time, and Q3 changes from “L” to “H”.

  On the other hand, when IN changes from “H” to “L”, the path from IN to S3 and the path from IN to R3 are switched with respect to the above-described operation. That is, after IN changes from “H” to “L”, the capacitor 26 is delayed by the charging time, and Q3 changes from “H” to “L”.

  Thereby, even when the pulse width of the input signal is short, the output Q1 of the flip-flop 11 holds “H” until the capacitor 21 is charged and the potential at the connection point a1 exceeds the threshold potential of the inverter 19. Therefore, the potential transition is not canceled at the connection point a1, and a short pulse signal is input to S3. When S3 becomes “H”, Q3 becomes “H”. Thereafter, even if S3 immediately becomes “L”, Q3 remains “H” until R3 becomes “H”. Therefore, an output signal with a desired delay can be obtained even when the pulse width of the input signal is short.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a delay circuit 100b according to the second embodiment of the present invention. The first delay generation circuit unit 14 b includes a constant current circuit 27 and an NMOS transistor 28 that charge the capacitor 21 instead of the inverter 18 in the first embodiment. The second delay generation circuit unit 15b includes a constant current circuit 29 that charges the capacitor 26 and an NMOS transistor 30 instead of the inverter 23 in the first embodiment. Other basic configurations are the same as those in the first embodiment.

  Specifically, the constant current circuit 27 is connected between one end of the capacitor 21 and the power source. The NMOS transistor 28 has a gate connected to the output of the inverter 17, a source grounded, and a drain connected to one end of the capacitor 21. The constant current circuit 29 is connected between one end of the capacitor 26 and the power source. The NMOS transistor 30 has a gate connected to the output of the inverter 22, a source grounded, and a drain connected to one end of the capacitor 26.

  Furthermore, in this configuration, the power supply voltages used differ between the constant current circuits 27 and 29 and the NMOS transistors 28 and 30 as boundaries. That is, the first power supply voltage VDD1 is supplied to the flip-flops 11 and 13 and the inverters 12, 17, and 22, and the inverters 19, 20, 24, and 25 and the flip-flops 16 after the constant current circuits 27 and 29 are supplied. The second power supply voltage VDD2 is applied.

  According to the present embodiment, the same effects as those of the first embodiment can be obtained. In addition, the design of the delay time is improved and the delay time is provided. In this configuration, the flip-flops 11 and 13 and the inverters 12, 17 and 22 are provided. The power supply voltage and the circuit power supply after the constant current circuits 27 and 29 can be made different, and therefore level shift can be performed simultaneously.

Embodiment 3 FIG.
FIG. 4 is a circuit diagram showing a delay circuit 100c according to the third embodiment of the present invention. The first delay generation circuit unit 14 c includes a constant current circuit 31 and a PMOS transistor 32 that discharge the capacitor 21 instead of the inverter 18 in the first embodiment. The second delay generation circuit unit 15 c includes a constant current circuit 33 and a PMOS transistor 34 that discharge the capacitor 26 instead of the inverter 23 in the first embodiment. Further, in order to match the logic, unlike the first and second embodiments, the inverters 19 and 24 are arranged in the subsequent stages of the inverters 17 and 22, respectively, and their outputs are connected to the gates of the PMOS transistors 32 and 34. Other basic configurations are the same as those in the first embodiment.

  Specifically, the constant current circuit 31 is connected between one end of the capacitor 21 and the ground. The PMOS transistor 32 has a gate connected to the output of the inverter 17, a source connected to the power supply, and a drain connected to one end of the capacitor 21. The constant current circuit 33 is connected between one end of the capacitor 26 and the ground. The PMOS transistor 34 has a gate connected to the output of the inverter 22, a source connected to the power supply, and a drain connected to one end of the capacitor 26.

  Further, in this configuration, the reference potentials used at the boundaries between the PMOS transistors 32 and 34 and the constant current circuits 31 and 33 are different. That is, the first reference potential VSS1 is supplied to the flip-flops 11 and 13 and the inverters 12, 17, 19, 22, and 24, and the inverters 20 and 25 and the flip-flops 16 after the constant current circuits 31 and 33 are supplied. The second reference potential VSS2 is provided.

  According to the present embodiment, the same effects as those of the first embodiment can be obtained, and the delay time design can be improved and the delay time is provided. In this configuration, the flip-flops 11 and 13 and the inverters 12, 17 and 19 are provided. , 22 and 24 and the reference potentials in the circuits after the constant current circuits 31 and 33 can be made different, and therefore, the reverse level shift can be performed simultaneously.

Embodiment 4 FIG.
FIG. 5 is a circuit diagram showing a delay circuit 100d according to the fourth embodiment of the present invention. The first delay generation circuit unit 14d includes constant current circuits 35 and 36 for charging and discharging the capacitor 21, respectively, instead of the inverter 18 in the first embodiment. The second delay generation circuit unit 15d includes constant current circuits 37 and 38 for charging and discharging the capacitor 26, respectively, instead of the inverter 23 in the first embodiment. Other configurations are the same as those in the first embodiment.

  Specifically, the constant current circuit 35 is connected between one end of the capacitor 21 and the power supply, and the constant current circuit 36 is connected between one end of the capacitor 21 and the ground. In accordance with the output of the inverter 17, one of the constant current circuits 35 and 36 is activated. That is, when the output of the inverter 17 is “H”, a constant current is supplied from the constant current circuit 35 so as to charge the capacitor 21. On the contrary, when the output is “L”, the charge charged in the capacitor 21 is discharged. A constant current is drawn through the constant current circuit 36. The constant current circuit 37 is connected between one end of the capacitor 21 and the power source, and the constant current circuit 38 is connected between one end of the capacitor 21 and the ground. Then, one of the constant current circuits 37 and 38 is activated in accordance with the output of the inverter 22. When the output of the inverter 22 is “H”, the constant current circuit 37 charges the capacitor 26. On the other hand, when the constant current is supplied and is “L”, the constant current is drawn through the constant current circuit 38 so as to discharge the electric charge charged in the capacitor 26.

  According to the present embodiment, the same effects as in the first embodiment can be obtained, and the design and accuracy of the delay time can be improved. Further, as shown in Embodiment 2 or Embodiment 3, by using different power supply voltages or reference voltages in the circuit, level shift or reverse level shift can be performed simultaneously with the provision of the delay time.

Embodiment 5. FIG.
FIG. 6 is a circuit diagram showing a delay circuit 100e according to the fifth embodiment of the present invention. The first delay generation circuit unit 14 e has a resistor 39 between the drain terminal of the PMOS transistor 18 p constituting the inverter 18 in the first embodiment and the capacitor 21. Further, the second delay generation circuit unit 15 e has a resistor 40 between the drain terminal of the PMOS transistor 23 p constituting the inverter 23 in the first embodiment and the capacitor 26. Other configurations are the same as those in the first embodiment.

  According to the present embodiment, the same effect as in the first embodiment is obtained.

Embodiment 6 FIG.
FIG. 7 is a circuit diagram showing a delay circuit 100f according to the sixth embodiment of the present invention. The first delay generation circuit unit 14 f includes a comparator 41 provided at the subsequent stage of the capacitor 21 instead of the inverter 19 in the first embodiment. The second delay generation circuit unit 15 f includes a comparator 42 provided at the subsequent stage of the capacitor 26 instead of the inverter 24 in the first embodiment. Other configurations are the same as those in the first embodiment.

  Specifically, the inverting (−) input of the comparator 41 is connected to one end of the capacitor 21, the non-inverting (+) input is connected to the detection reference voltage Vref, and the output is connected to the input of the inverter 20. Further, the inverting (−) input of the comparator 42 is connected to one end of the capacitor 26, the non-inverting (+) input is connected to the detection reference voltage Vref, and the output is connected to the input of the inverter 25. For the detection reference voltage Vref, for example, a desired voltage value can be determined simply by resistance division of the power supply voltage, and the first delay generation circuit unit 14 and the second delay generation circuit unit 15 are shared. May be used for Further, it may be prepared by other circuits including the outside.

  According to the present embodiment, the same effects as those of the first embodiment can be obtained, and the delay time can be easily set. Further, by changing the detection reference voltage of the comparator from the outside, the delay time can be easily adjusted according to, for example, the application and purpose, and high versatility can be obtained. In addition, this Embodiment and Embodiment 2-5 can also be combined.

Embodiment 7 FIG.
FIG. 8 is a circuit diagram showing a delay circuit 101 according to the seventh embodiment of the present invention. The delay circuit 101 inputs an input signal and outputs it to the set input S1 of the first flip-flop 11 and inputs the output signal of the second inverter 43 and inverter 44 and the first inverter 12 to the second input. And inverters 45 and 46 for outputting to the set input S2 of the flip-flop 13. The threshold potential _{V th1} of the first inverter 12 and the threshold potential _{V th2} of the second inverter 43 is set to be different from each other. Other configurations are the same as those in the first embodiment.

FIG. 9 is a timing chart for explaining the operation of the delay circuit 101 shown in FIG. As shown in the figure, when the delay time of the delay circuit 101 elapses after the input signal rises and reaches the threshold potential _Vth1 , the output signal from Q3 rises. Further, when the delay time of the delay circuit 101 elapses after the potential of the input signal falls and reaches the threshold potential _Vth2 , the output signal falls. Therefore, only by setting the threshold potential V _th2 threshold potential V _th1 and the inverter 43 of the first inverter 12, a hysteresis voltage is the difference between them can be set to a desired value.

  According to this embodiment, in addition to the same effects as those of the first embodiment, a simple delay circuit having a hysteresis function can be obtained. That is, since there is no need to provide a conventional simulation circuit having a hysteresis function, there is no problem that a signal with a short pulse width disappears when the response speed of the simulation circuit is slow. In addition, the delay time and the hysteresis width can be easily set as compared with the case where a simut circuit is provided, and there is no problem that the accuracy deteriorates due to the influence of the temperature characteristics and design variations of the simut circuit. In addition, this Embodiment and Embodiment 2-6 can also be combined.

Embodiment 8 FIG.
FIG. 10 is a circuit diagram showing the delay circuit 102 according to the eighth embodiment of the present invention. This delay circuit 102 is provided with a delay circuit 52 in the subsequent stage of the twin filter 51.

  The twin filter 51 includes a first delay generation circuit unit 53, a first inverter 54, a second delay generation circuit unit 55, and a first flip-flop 56.

  Then, the first delay generation circuit unit 53 delays the input signal. The first inverter 54 inverts the input signal, and the second delay generation circuit unit 55 delays the output signal of the first inverter 54. The first flip-flop 56 receives the output signal of the first delay generation circuit unit 53 from the set input S1, and receives the output signal of the second delay generation circuit unit 55 from the reset input R1.

  The delay circuit 52 includes a second flip-flop 57, a third flip-flop 58, a third delay generation circuit unit 59, a fourth delay generation circuit unit 60, and a fourth flip-flop 61. Have

  Then, the second flip-flop 57 receives the output signal of the first flip-flop 56 from the set input S2. The third flip-flop 58 receives the inverted output signal of the first flip-flop 56 from the set input S3. The third delay generation circuit 59 receives the output signal of the second flip-flop 57, delays it, and outputs it to the reset input R2 of the second flip-flop 57. The fourth delay generation circuit unit 60 receives the output signal of the third flip-flop 58, delays it, and outputs it to the reset input R3 of the third flip-flop 58. The fourth flip-flop 61 receives the output signal of the third delay generation circuit unit 59 from the set input S4, receives the output signal of the fourth delay generation circuit unit 60 from the reset input R4, and outputs the output Q4. To output an output signal.

  The first delay generation circuit unit 53 includes capacitors 61 to 64 connected in series between an input and an output, a capacitor having one end connected to a connection point b1 between the inverter 62 and the inverter 63, and the other end grounded. 65. The second delay generation circuit unit 55 includes a capacitor having one end connected to a connection point b2 between the inverters 66 to 69 connected in series between the input and the output and the inverter 67 and the inverter 68 and the other end grounded. 70. The third delay generation circuit unit 59 includes an inverter 71 to 74 connected in series between an input and an output, and a capacitor 75 having one end connected to a connection point between the inverter 72 and the inverter 73 and the other end grounded. And have. The fourth delay generation circuit unit 60 includes inverters 76 to 79 connected in series between an input and an output, and a capacitor 80 having one end connected to a connection point between the inverter 77 and the inverter 78 and the other end grounded. And have. The first to fourth delay generation circuit units 53, 55, 59, and 60 perform delays in accordance with charging of the capacitors 65, 70, 75, and 80, respectively. In FIG. 10, the inverters 62 and 67 are composed of CMOS, and the current drive capability on the PMOS side is suppressed from the NMOS side. By doing so, the charging time of the capacitor becomes longer than the discharging time, and the rising time of the signal delay time given by the first and second delay circuit units 53 and 55 is longer than that of the falling time. Is set to

  FIG. 11 is a timing chart for explaining the operation of the twin filter 51. First, when IN is “L”, the set input S1 of the first flip-flop 56 is “L”, the reset input R1 is “H”, and the output Q1 is “L”.

  Next, when IN changes from “L” to “H”, R1 quickly changes to “L”, and b1 starts to change from “L” to “H”. In the beginning, since S1 is “L”, Q1 remains “L”. Thereafter, when the time when IN is “H” is sufficiently long and the potential b1 reaches the threshold potential of the inverter 63, S1 becomes “H” and the output Q1 becomes “H”. On the other hand, when IN is “H” for a short time and b1 does not reach the threshold potential of inverter 63, S1 does not become “H”, and output Q1 remains “L”.

  Next, when IN changes from “H” to “L”, S1 immediately changes to “L”, and b2 starts to change from “L” to “H”. In the beginning, since R1 is “L”, Q1 remains “H”. After that, when IN is sufficiently “L” and b2 reaches the threshold potential of the inverter 68, R1 becomes “H” and the output Q1 becomes “L”. On the other hand, when the time when IN is “L” is short and b2 does not reach the threshold potential of the inverter 68, R1 does not become “H” and the output Q1 remains “H”.

  Thus, the twin filter 51 has a filter function that works on both the on-pulse and off-pulse, and can filter a noise signal or the like mixed in the input signal. The output signal of the twin filter 51 is input to the delay circuit 52 and delayed in the same manner as in the first embodiment. Therefore, even when the pulse width of the input signal that has passed through the twin filter circuit is short, an output signal with a desired delay can be obtained. In addition, there is an advantage that the circuit configuration is simplified as compared with the case where a desired delay is obtained by using only a plurality of stages of twin filters.

  As the circuit configurations of the first to fourth delay generation circuit units 53, 55, 59, and 60, the circuit configurations of the delay circuits of the second to sixth embodiments can be applied. Furthermore, the hysteresis function can be provided by applying the seventh embodiment.

Embodiment 9 FIG.
FIG. 12 is a circuit diagram showing a delay circuit 103a according to the ninth embodiment of the present invention. The delay circuit 103 a includes an inverter 85, a first flip-flop 83, a first delay generation circuit unit 84, a second delay generation circuit unit 88, and a second flip-flop 89.

  The first flip-flop 83 receives an input signal from the set input S1. The first delay generation circuit unit 84 receives the output signal of the first flip-flop 83, delays it, and outputs it to the reset input R1 of the first flip-flop 83. The inverter 85 inverts the input signal, and the second delay generation circuit unit 88 delays the output signal of the inverter 85. The second flip-flop 89 receives the output signal of the first delay generation circuit unit 84 from the set input S2, and receives the output signal of the second delay generation circuit unit 88 from the reset input R2.

  The first delay generation circuit unit 84 includes inverters 91 to 94 connected in series between an input and an output, and a capacitor 95 having one end connected to a connection point between the inverter 92 and the inverter 93 and the other end grounded. And have. The second delay generation circuit unit 88 includes capacitors 100 to 99 connected in series between the input and output, and a capacitor 100 having one end connected to a connection point between the inverter 97 and the inverter 98 and the other end grounded. And have. Then, the first and second delay generation circuit units 84 and 88 perform delays according to charging of the capacitors 95 and 100, respectively.

  FIG. 13 is a timing chart for explaining the operation of the delay circuit 103a shown in FIG. As shown in the figure, the rising edge of the input is detected for the on-pulse of the input signal to give a predetermined delay, and the filter acts on the off-pulse of the input signal. For this reason, it is not affected by noise generated in the ON pulse of the input signal. Therefore, the same effect as in the eighth embodiment can be realized with a simpler circuit.

  As the circuit configurations of the first and second delay generation circuit units 84 and 88, the circuit configurations of the delay circuits of the second to sixth embodiments can be applied. Furthermore, the hysteresis function can be provided by applying the seventh embodiment.

Embodiment 10 FIG.
FIG. 14 is a circuit diagram showing a delay circuit 103b according to the tenth embodiment of the present invention. The delay circuit 103 b includes an inverter 85, a first flip-flop 83, a first delay generation circuit unit 84, a second delay generation circuit unit 88, and a second flip-flop 89.

  Then, the second delay generation circuit unit 84 delays the input signal. The inverter 85 inverts the input signal, and the first flip-flop 83 receives the output signal of the inverter 85 from the set input S1. The second delay generation circuit unit 88 receives the output signal of the first flip-flop 83, delays it, and outputs it to the reset input R1 of the first flip-flop 83. The second flip-flop 89 receives the output signal of the first delay generation circuit unit 84 from the set input S2, and receives the output signal of the second delay generation circuit unit 88 from the reset input R2. Further, the first and second delay generation circuit units 84 and 88 perform delays according to charging of the capacitors 95 and 100, respectively.

  FIG. 15 is a timing chart for explaining the operation of the delay circuit 103b shown in FIG. As shown in the figure, the falling edge of the input is detected for the off pulse of the input signal to give a predetermined delay, and the filter acts on the on pulse of the input signal. For this reason, it is not affected by noise generated in the off pulse of the input signal. Therefore, the same effect as in the eighth embodiment can be realized with a simpler circuit.

  As the circuit configurations of the first and second delay generation circuit units 84 and 88, the circuit configurations of the delay circuits of the second to sixth embodiments can be applied. Furthermore, the hysteresis function can be provided by applying the seventh embodiment.

1 is a circuit diagram illustrating a delay circuit according to a first embodiment of the present invention. 2 is a timing chart for explaining the operation of the delay circuit shown in FIG. 1. It is a circuit diagram which shows the delay circuit based on Embodiment 2 of this invention. It is a circuit diagram which shows the delay circuit based on Embodiment 3 of this invention. It is a circuit diagram which shows the delay circuit based on Embodiment 4 of this invention. It is a circuit diagram which shows the delay circuit based on Embodiment 5 of this invention. It is a circuit diagram which shows the delay circuit based on Embodiment 6 of this invention. It is a circuit diagram which shows the delay circuit based on Embodiment 7 of this invention. 9 is a timing chart for explaining the operation of the delay circuit shown in FIG. 8. It is a circuit diagram which shows the delay circuit based on Embodiment 8 of this invention. It is a timing chart for explaining operation of a twin filter. It is a circuit diagram which shows the delay circuit based on Embodiment 9 of this invention. 13 is a timing chart for explaining the operation of the delay circuit shown in FIG. 12. It is a circuit diagram which shows the delay circuit based on Embodiment 10 of this invention. 15 is a timing chart for explaining the operation of the delay circuit shown in FIG. It is a circuit diagram which shows the delay circuit generally used FIG. 17 is a timing chart for explaining the operation of the delay circuit shown in FIG. 16. FIG.

Explanation of symbols

11, 56, 83 First flip-flops 12, 54 First inverters 13, 57, 89 Second flip-flops 14, 53, 84 First delay generation circuit sections 15, 55, 88 Second delay generation circuits Part 16, 58 third flip-flop 21, 26, 65, 70, 75, 80, 95, 100 capacitor 27, 29, 31, 33, 35-38 constant current circuit 39, 40 resistor 41, 42 comparator 43 second Inverter 59 Third delay generation circuit section 60 Fourth delay generation circuit section 61 Fourth flip-flop 85 Inverter

Claims (15)

A first flip-flop for inputting an input signal from a set input;
A first inverter for inverting the input signal;
A second flip-flop for inputting an output signal of the first inverter from a set input;
A first delay generation circuit unit that inputs an output signal of the first flip-flop, delays it and outputs it to a reset input of the first flip-flop;
A second delay generation circuit unit that inputs an output signal of the second flip-flop, delays it and outputs it to a reset input of the second flip-flop;
A third flip-flop that inputs an output signal of the first delay generation circuit unit from a set input and inputs an output signal of the second delay generation circuit unit from a reset input;
The delay circuit according to claim 1, wherein the first and second delay generation circuit sections perform delay according to charging of the capacitor.   2. The delay circuit according to claim 1, wherein the first and second delay generation circuit units further include a constant current circuit for charging the capacitor.   The delay circuit according to claim 1, wherein the first and second delay generation circuit units further include a constant current circuit for discharging the capacitor.   The delay circuit according to claim 1, wherein the first and second delay generation circuit units further include a constant current circuit that charges and discharges the capacitor.   The delay circuit according to claim 1, wherein the first and second delay generation circuit units further include a resistor provided in front of the capacitor.   6. The delay circuit according to claim 1, wherein each of the first and second delay generation circuit units further includes a comparator provided at a subsequent stage of the capacitor. A first delay generation circuit for delaying an input signal;
A first inverter for inverting the input signal;
A second delay generation circuit for delaying the output signal of the first inverter;
A first flip-flop for inputting an output signal of the first delay generation circuit unit from a set input and an output signal of the second delay generation circuit unit from a reset input;
A second flip-flop for inputting an output signal of the first flip-flop from a set input;
A third flip-flop for inputting an inverted output signal of the first flip-flop from a set input;
A third delay generation circuit unit that inputs an output signal of the second flip-flop, delays it and outputs it to a reset input of the second flip-flop;
A fourth delay generation circuit unit that inputs an output signal of the third flip-flop, delays it and outputs it to a reset input of the third flip-flop;
A fourth flip-flop that inputs an output signal of the third delay generation circuit unit from a set input and inputs an output signal of the fourth delay generation circuit unit from a reset input;
The first to fourth delay generation circuit units perform a delay in accordance with charging of a capacitor.   The delay circuit according to claim 7, wherein the first to fourth delay generation circuit units further include a constant current circuit that charges the capacitor.   The delay circuit according to claim 7, wherein the first to fourth delay generation circuit units further include a constant current circuit for discharging the capacitor.   8. The delay circuit according to claim 7, wherein the first to fourth delay generation circuit units further include a constant current circuit for charging and discharging the capacitor.   The delay circuit according to claim 7, wherein the first to fourth delay generation circuit units further include a resistor provided in front of the capacitor.   12. The delay circuit according to claim 7, wherein each of the first to fourth delay generation circuit units further includes a comparator provided at a subsequent stage of the capacitor. A second inverter that inputs the input signal and outputs the input signal to a set input of the first flip-flop;
The delay circuit according to any one of claims 1 to 12, wherein a threshold potential of the first inverter and a threshold potential of the second inverter are different from each other. A first flip-flop for inputting an input signal from a set input;
A first delay generation circuit unit that inputs an output signal of the first flip-flop, delays it and outputs it to a reset input of the first flip-flop;
An inverter for inverting the input signal;
A second delay generation circuit for delaying the output signal of the inverter;
A second flip-flop that inputs an output signal of the first delay generation circuit unit from a set input and inputs an output signal of the second delay generation circuit unit from a reset input;
The delay circuit according to claim 1, wherein the first and second delay generation circuit sections perform delay according to charging of the capacitor. A first delay generation circuit for delaying an input signal;
An inverter for inverting the input signal;
A first flip-flop for inputting an output signal of the inverter from a set input;
A second delay generation circuit unit that inputs an output signal of the first flip-flop, delays it and outputs it to a reset input of the first flip-flop;
A second flip-flop that inputs an output signal of the first delay generation circuit unit from a set input and inputs an output signal of the second delay generation circuit unit from a reset input;
The delay circuit according to claim 1, wherein the first and second delay generation circuit sections perform delay according to charging of the capacitor.

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