JPH0870241A - Delay circuit - Google Patents

Abstract

PURPOSE: To provide the delay circuit corresponding to a high frequency pulse signal by reducing a standby time. CONSTITUTION: The circuit is provided with a 1st inverter circuit 2 providing an output of an inverted input signal from an input terminal Vin. an RC time constant circuit comprising a resistor R and a capacitor C used to decide a time constant of a delay time based on an output of the 1st inverter circuit 2, a charge/discharge circuit 4 promoting charging/discharging the capacitor C of the RC time constant circuit 3, a comparator 5 providing a low level Vss from an output terminal when a level of an input terminal and an output terminal of the charge discharge circuit 4 is lower than a level Vref and providing a high level Vcc from the output terminal when the level of the input terminal and the output terminal of the charge discharge circuit 4 is higher than the level Vref, and a 2nd inverter circuit 6 providing an inverted output signal from the comparator 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly, it relates to a delay circuit having a reduced waiting time.

[0002]

2. Description of the Related Art In recent years, with the rapid progress of semiconductor technology,
Many delay circuits are used in electronic circuits to adjust the timing of electrical signals. Since a delay circuit has a finite speed at which an electric signal propagates, in order to align the phases of a plurality of electric signals transmitted through different paths, the delaying circuit delays the preceding signal by a necessary time ( In principle, it is not possible to speed up delayed signals.) It is a circuit for correcting the time difference between signals, and, for example, when it is desired to cause a predetermined time difference between signals in an electronic circuit. When timing adjustment is required, it is used to obtain the required timing accurately and stably.

Conventionally, as such a delay circuit, there is, for example, a delay circuit 101 having an output stage having a hysteresis characteristic as shown in FIG. FIG. 8 is a circuit diagram showing the configuration of the conventional delay circuit 101. The delay circuit 101 shown in FIG. 8 includes an inverter circuit 102 and an RC which are input stages.
It is composed of a time constant circuit 103, a Schmitt trigger circuit 104 serving as an output stage, and an inverter circuit 105.

The inverter circuit 102 is a P channel MO.
This is a CMOS inverter composed of an S transistor P11 and an N-channel MOS transistor N11. The input end side is connected to the input terminal Vin and the output end side is connected to the RC time constant circuit 103 of the next stage.

The RC time constant circuit 103 is a time constant circuit composed of a resistor R1 and a capacitor C1. The input end side is connected to the output end side of the inverter circuit 102 and the output end side is the Schmitt of the next stage. It is connected to the trigger circuit 104. The delay time in the delay circuit 101 is determined based on the resistance value of the resistor R1 and the capacitance of the capacitance C1.

The Schmitt trigger circuit 104 has an input end side connected to the RC time constant circuit 103 and an output end side connected to the next-stage inverter circuit 104, and has two different threshold values (in this case, 3.0 V and By having 2.2V), the delay circuit 101 has a hysteresis characteristic, and thereby chattering due to a change in the input potential level is prevented.

The inverter circuit 105 is a P-channel MO.
It is a CMOS inverter composed of an S transistor P22 and an N-channel MOS transistor N22. The input end side is connected to the output end side of the Schmitt trigger circuit 105 and the output end side is connected to the output terminal Vout.

An operation example of the above configuration will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram showing the voltage level at each node of the delay circuit 101 shown in FIG.
FIG. 10 is a composite diagram of each voltage level in FIG.
In addition, (X), (Y), and (Z) in FIGS.
Nodes (X), (Y), and
The potential of (Z) is shown.

As shown in FIG. 9A, when "H" is input to the inverter circuit 102 as one pulse signal, first, the RC time constant circuit 103 gradually increases the potential of the node (Y). When the potential of the node (Y) becomes lower than 2.2 V (see the first half of FIG. 9B), the Schmitt trigger circuit 104 operates and the inverter circuit 105 outputs “H” (FIG. 9). (See the first half of (c)).

On the other hand, when "L" is input to the inverter circuit 102, the RC time constant circuit 103 gradually raises the potential of the node (Y) (see the latter half of FIG. 9B) and the node ( When the potential of Y) becomes larger than 3.0 V, the Schmitt trigger circuit 104 operates again and "L" is output from the inverter circuit 105 (see the latter half part of FIG. 9C). As a result, the pulse signal input from the input terminal Vin has a predetermined time (hereinafter, delay time td).
It is delayed and output from the output terminal Vout.

[0011]

However, in such a conventional delay circuit 101, the Schmitt trigger circuit 104 having a hysteresis characteristic is provided in the output stage in order to prevent chattering due to deviation of the input potential level. Therefore, there were problems as described below.

That is, after the output level of the inverter circuit 104, which is the final output stage, becomes "H", the potential of the node (Y) is further lowered by the RC time constant circuit 103, and the potential of the node (Y) is almost low. Potential power line Vss (=
Until the potential level of (GND) is reached (specifically, the potential level of the node (Y) becomes smaller than 0.2 V), a predetermined time (hereinafter referred to as a standby time tw) is applied to the input terminal Vin. Delay circuit 1 even if a pulse signal is input
01 does not work correctly in principle.

Therefore, in the conventional replacement circuit 101,
It was not possible to cope with pulse input at a time interval shorter than the delay time td + waiting time tw, and could not be used in a pulse signal with a short cycle, that is, in an electronic circuit handling a high frequency pulse signal. .

The present invention has been made under such circumstances, and an object thereof is to provide a delay circuit which shortens the waiting time and copes with a high frequency pulse signal.

[0015]

Means for Solving the Problems The first aspect of the present invention is shown in FIG.
As shown in FIG. 3, in the delay circuit 1 which outputs the pulse signal input from the input terminal Vin from the output terminal Vout after a lapse of a predetermined time, the input terminal is connected to the input terminal Vin and is connected to the input terminal side of the next-stage circuit. Connect the output end,
A first inverter circuit 2 that outputs an inverted signal of a signal input from the input end from the output end, an input end connected to the output end of the first inverter circuit 2, and an output end connected to the input end of the next stage circuit. And an RC time constant circuit 3 composed of a resistor R and a capacitor C for determining the time constant of the delay time, and R
An input / output terminal is connected to the output terminal of the C time constant circuit 3, and a charging / discharging circuit 4 for promoting charging / discharging of the capacitance C in the RC time constant circuit 3 and an input terminal for the input / output terminal of the charging / discharging circuit 4. In addition to the connection, the output terminal is connected to the input terminal side of the next stage circuit, and when the potential level of the input / output terminal of the charging / discharging circuit 4 is lower than the predetermined potential level Vref, the potential level V lower than the output terminal.
On the other hand, when the potential level of the input / output terminal of the charging / discharging circuit 4 is higher than a predetermined potential level Vref, the comparator 5 outputs ss and outputs a higher potential level Vcc from the output terminal.
A second inverter circuit 6 having an output terminal of the comparator 5 connected to an input terminal, an output terminal connected to the output terminal Vout, and an inverted signal of a signal input from the input terminal being output from the output terminal; It is characterized by including.

According to a second aspect of the present invention, as shown in FIG. 2, in a delay circuit 1'that outputs a pulse signal input from an input terminal Vin from an output terminal Vout after a lapse of a predetermined time, an input terminal to the input terminal Vin is provided. With connecting
An output terminal is connected to the input terminal side of the next stage circuit, and an inverter circuit 2'that outputs an inverted signal of the signal input from the input terminal from the output terminal and an input terminal is connected to the output terminal of the inverter circuit 2 '. At the same time, an output terminal is connected to the input terminal side of the next-stage circuit, and an RC time constant circuit 3 composed of a resistor R and a capacitor C that determines the time constant of the delay time, and an input / output at the output terminal of the RC time constant circuit 3. A charging / discharging circuit 4 for connecting the terminals to promote charging / discharging of the capacitance C in the RC time constant circuit 3, an input terminal is connected to the input / output terminal of the charging / discharging circuit 4, and the input terminal side of the next-stage circuit is connected. When the potential level of the input / output terminal of the charging / discharging circuit 4 is lower than the first potential level VL, a higher potential level Vcc is output from the output terminal and the input / output terminal of the charging / discharging circuit 4 is connected. If the potential level of is higher than the second potential level VH, A comparator circuit 7 with a hysteresis characteristic to output the low potential level Vss, characterized in that it comprises a.

According to a third aspect of the present invention, in the first or second aspect of the invention, the charge / discharge circuit includes a first P-channel MOS transistor P3 between a high potential power line and a low potential power line. Second P-channel MOS transistor P
4, the second N-channel MOS transistor N4 and the first N-channel MOS transistor N3 are serially connected in this order, and the connection point between the second P-channel MOS transistor P4 and the second N-channel MOS transistor N4 is an input / output terminal. And the first P-channel MOS transistor P
3 and the first N-channel MOS transistor N3 are commonly connected to the input terminal Vin, and the second P-channel MOS transistor P4 and the second N-channel MOS transistor N4 are commonly connected. And is connected to the output terminal Vout.

According to a fourth aspect of the present invention, in the second or third aspect of the invention, the comparator circuit 7 has one input terminal connected to the input / output terminal of the charge / discharge circuit 4 and the other input terminal. A first comparator 8 which applies a low potential reference voltage VL, and a second comparator 9 which applies a high potential reference voltage VH to one input terminal and connects the other input terminal to the input / output terminal of the charge / discharge circuit 4. And the output terminal of the first comparator 8 is connected to the set terminal S, and the second comparator 9
And an RS flip-flop 10 having an output terminal connected to the reset terminal R.

[0019]

According to the first aspect of the invention, since the charge / discharge circuit rapidly charges or discharges the capacitance in the RC time constant circuit, the rise and fall times of the pulse signal input to the comparator are significantly increased. It will be shortened and the waiting time will be greatly shortened. This makes it possible to cope with a high-frequency pulse signal having a short cycle.

According to the second aspect of the present invention, since the charge / discharge circuit rapidly charges or discharges the capacitance in the RC time constant circuit, the rise and rise of the pulse signal input to the comparator circuit having a hysteresis characteristic. The fall time is greatly shortened, and the waiting time is accordingly shortened. As a result, it is possible to cope with a high-frequency pulse signal having a short cycle while having an output stage having a hysteresis characteristic.

In this case, according to the invention of claim 3, since the charge / discharge circuit is composed of four MOS transistors, in addition to the invention of claim 1 or 2, The number of parts for forming the charge / discharge circuit can be reduced. In addition, the charge / discharge circuit in this case has a CMO
Since it can be manufactured by S technology, compared to conventional circuits,
It can be manufactured with almost no increase in circuit space and manufacturing cost.

Further, in this case, according to the invention of claim 4, the comparison result signal of the first comparator having the low potential reference voltage VL as a reference voltage is input to the set terminal of the RS flip-flop, and the high potential reference is applied. The comparison result signal of the second comparator using the voltage VH as the reference voltage is input to the reset terminal of the RS flip-flop, so that in addition to the invention described in claim 2 or 3, the combination of ordinary comparators is used. Thus, for example, a function equivalent to that of a Schmitt trigger circuit or a hysteresis comparator is realized.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to FIGS.
Will be described with reference to. First, the configuration of this embodiment will be described.

FIG. 1 is a circuit diagram showing the configuration of the delay circuit 1 of the first embodiment. In FIG. 1, the delay circuit 1 of this embodiment is roughly composed of a first inverter circuit 2, an RC time constant circuit 3, a charging / discharging circuit 4, a comparator 5, and a second inverter circuit 6.

The first inverter circuit 2 is a P-channel MOS transistor connected in series between a high potential power line and a low potential power line.
Transistor P1 and N-channel MOS transistor N1
And a gate connected to each other by commonly connecting the gates to each other as an input terminal to the input terminal Vin, and also in the P-channel MOS transistors P1 and N.
The connection point with the channel MOS transistor N1 is connected as an output end to the RC time constant circuit 3 of the next stage, and the inverted signal of the pulse signal input from the input terminal Vin is supplied to the R of the next stage.
It is output to the C time constant circuit 3.

The RC time constant circuit 3 is a time constant circuit composed of a resistor R and a capacitor C. One end of the resistor R is connected as an input end to the output end of the inverter circuit 2 and the other end of the resistor R is connected. Charge / discharge circuit 4 at the next stage with the end as the output end
Further, the output end is connected to the other end of the capacitor C whose one end is connected to the low potential power line. Thus, the delay time in the delay circuit 1 is determined based on the resistance value of the resistor R and the capacitance of the capacitance C.

The charge / discharge circuit 4 includes a first P-channel MOS transistor P3 and a second P-channel MOS transistor P, which are connected in series between a high potential power line and a low potential power line.
4, a second N-channel MOS transistor N4 and a first N-channel MOS transistor N3, and a second P-channel MOS transistor P4 and a second N-channel MOS transistor.
The connection point with the transistor N4 is connected as an input / output terminal to the output terminal of the RC time constant circuit 3 and the input terminal of the hysteresis comparator 7, and further the first P-channel MOS transistor P3 and the first N-channel MOS transistor N are connected.
The gates of the second P-channel MOS transistor P4 and the second N-channel MOS transistor N4 are commonly connected to the output terminal Vout and are connected to the input terminal Vin. In order to shorten the time, the capacity C of the RC time constant circuit 3 is rapidly charged and discharged.

The comparator 5 has an input end connected to the charge / discharge circuit 4
Is connected to the input / output terminal of the second inverter circuit 6 and the output terminal thereof is connected to the second inverter circuit 6 of the next stage, and a predetermined threshold voltage Vre
It has f (= Vcc / 2).

The second inverter circuit 6 is a P-channel MOS transistor connected in series between a high potential power line and a low potential power line.
Transistor P2 and N-channel MOS transistor N2
Is a CMOS inverter configured by commonly connecting the gates of both to the output end of the hysteresis comparator 7 as an input end,
Transistor P2 and N-channel MOS transistor N2
The connection point with and is connected to the output terminal Vout as an output end, and the inverted signal of the pulse signal output from the comparator 5 is output to the output terminal Vout.

In the above configuration, there is no problem when the signal waveform input to the comparator 5 does not include noise, but when the signal waveform fluctuates in the vicinity of the threshold voltage Vref of the comparator 5 due to the noise included in the signal waveform. Since noise may change the time or cause chattering, it is desirable to use a hysteresis comparator having a hysteresis characteristic as shown in FIG. 2 during actual use.

FIG. 2 is a circuit diagram showing the configuration of the delay circuit 1 of the second embodiment. The delay circuit 1 in FIG. 2 includes an inverter circuit 2 ′ having the same configuration as the first inverter circuit 2 and an R circuit.
C time constant circuit 3, charging / discharging circuit 4, and hysteresis comparator 7, and the above-mentioned comparator 5 and second inverter circuit 6 are replaced with a hysteresis comparator 7 which is a comparator circuit having hysteresis characteristics. Is.

The hysteresis comparator 7 has its input end connected to the input / output end of the charge / discharge circuit 4 and its output end connected to the output terminal Vout, and has two different thresholds (VL = Vcc / 2− in this case). Vα1 and VH = Vc
By having c / 2 + Vα2), the delay circuit 1 has a hysteresis characteristic for preventing chattering. Note that Vα1 and Vα2 are operating points of the hysteresis comparator 7, and the delay time difference between rising and falling can be finely adjusted by Vα1 and Vα2. In this case, if Vα1 = Vα2, the delay times of rising and falling are aligned, which is preferable.
The value of Vα1 + Vα2 is determined by the noise level of the signal.

FIG. 3 is a circuit diagram showing a configuration example of a comparator circuit 7'having a hysteresis characteristic, which is an alternative to the hysteresis comparator shown in FIG. As shown in FIG. 3, the comparator circuit 7 ′ in this example includes the first comparator 8
And a second comparator 9 and an RS flip-flop 10.

The first comparator 8 is a comparator in which one input end is connected to the input / output end of the charging / discharging circuit 4 and the low potential reference voltage VL is applied to the other input end. Is a comparator having a high potential reference voltage VH applied to one input terminal and the other input terminal connected to the input / output terminal of the charging / discharging circuit 4.

The RS flip-flop 10 connects the output terminal of the first comparator 8 to the set terminal S and the output terminal of the second comparator 9 to the reset terminal R, thereby providing a hysteresis of VH-VL. It has an output.

Hereinafter, an operation example of the delay circuit 1'of the second embodiment will be described with reference to FIGS. FIG. 4 is a diagram showing voltage levels at respective nodes of the delay circuit 1 ′ shown in FIG.
5 is a composite view of the voltage levels in FIG. 4, FIG. 6 is an enlarged view of the first half of FIG. 5, and FIG. 7 is an enlarged view of the second half of FIG. In addition, (A) in FIGS.
(B) and (C) indicate the potentials of the nodes (A), (B), and (C) in FIG. 2, respectively.

First, as an initial condition of the delay circuit 1'in this embodiment, the potential level applied to the input terminal Vin, that is, the potential level at the node (A) is Vs.
s (= "L"), potential level Eb at node (B)
And Eb = Vcc (= “H”).

When the potential level of the input terminal Vin rises from Vss to Vcc, the P-channel MOS transistor P1 is turned off and the N-channel MOS transistor N1 is turned on, and the discharge of the capacitor C is started. In this case, since the potential level of the node (A) is Vcc, the first P-channel MOS transistor P3 is off and the first N-channel MOS transistor is off.
The transistor N3 is turned on.

The potential level Eb of the node (B) is the falling threshold voltage VL (= 2.2) of the hysteresis comparator 7.
Until it reaches V), the potential level of the output terminal Vout,
That is, since the potential level at the node (C) is Vss, the second P-channel MOS transistor P4 is turned on,
The second N-channel MOS transistor N4 is turned off.
Therefore, the potential level Eb of the node (B) is [Equation 1]
Descend according to.

[0040]

[Equation 1] Then, the potential level Eb of the node (B) falls to the falling threshold voltage VL (=
2.2V), the potential level of the output terminal Vout is inverted, the potential level at the node (C) becomes Vcc, and the second P-channel MOS transistor P4 turns off.
The second N-channel MOS transistor N4 is turned on, and the capacitance C is discharged through the N-channel MOS transistor N1 and the second N-channel MOS transistor N4 and the first N-channel MOS transistor N3. . Therefore, the potential level Eb of the node (B) drops according to [Equation 2].

[0041]

(2) where (Ron2 + Ron3) becomes (Ron1
+ R), it becomes τ2τ
As shown in FIG. 6, the potential level Eb of the node (B) after the output of the hysteresis comparator 7 and the second inverter circuit 6 is inverted, the potential level Eb of the second N-channel MOS transistor N4 and the first N-channel MOS transistor N
Compared with the case where 3 is not present, it approaches Vss more quickly.

Next, the potential level applied to the input terminal Vin, that is, the potential level at the node (A) is V
Let cc (= “H”) and the potential level at the node (B) be Eb, and Eb = Vss (= “L”).

When the potential level of the input terminal Vin falls from Vcc to Vss, the P-channel MOS transistor P1 is turned on and the capacitor C is charged.
In this case, since the potential level of the node (A) is Vss, the first P-channel MOS transistor P3 is turned on and the first N-channel MOS transistor N3 is turned off.

The potential level Eb of the node (B) is the rising threshold voltage VH (= 3.0) of the hysteresis comparator 7.
Until it reaches V), the potential level of the output terminal Vout,
That is, since the potential level at the node (C) is Vcc, the second P-channel MOS transistor P4 is off,
The second N-channel MOS transistor N4 is turned on.
Therefore, the potential level Eb of the node (B) is [Equation 3]
Rise according to.

[0045]

[Equation 3] Then, the potential level Eb of the node (B) rises to the threshold voltage VH (=
3.0 V), the potential level of the output terminal Vout is inverted, the potential level at the node (C) becomes Vss, and the second P-channel MOS transistor P4 turns on.
The second N-channel MOS transistor N4 is turned off, and the capacitance C is added to the current supplied via the P-channel MOS transistor P1 as well as the first P-channel MOS transistor P3 and the second P-channel MOS transistor P.
It is charged by the current supplied via 4. Therefore, the potential level Eb of the node (B) rises according to [Equation 4].

[0046]

Where (Ron5 + Ron6) is replaced by (Ron4
+ R), it will be τ4τ
3, the potential level Eb of the node (B) after the output of the hysteresis comparator 7 and the second inverter circuit 6 is inverted, as shown in FIG. 7, the first P-channel MOS transistor P3 and the second P-channel MOS transistor P
Compared with the case without 4, the value approaches Vcc more quickly.

As described above, in this embodiment, the charging / discharging circuit 4 rapidly charges or discharges the capacitance C in the RC time constant circuit 3 so that the rise and fall times of the pulse signal input to the hysteresis comparator 7 are changed. It can be greatly shortened and the waiting time can be greatly shortened. Therefore, it is possible to provide the delay circuit 1 ′ which is provided with the output stage having the hysteresis characteristic and is also adapted to the high frequency pulse signal having the short period.

Further, in this case, since the charging / discharging circuit 4 is composed of only four MOS transistors P3, P4, N3, N4, the number of parts to be added to configure the charging / discharging circuit 4 can be small. Also, the circuit space and the manufacturing cost hardly increase.

Although the invention made by the present inventor has been specifically described based on the preferred embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the hysteresis comparator 7 or the comparator circuit 7'is used as the comparator circuit having the hysteresis characteristic. Instead of these, a Schmitt trigger circuit (inverted Schmitt trigger circuit) capable of inverting output is used. ) May be used.

Further, for example, in the above embodiment, it goes without saying that the resistance and capacitance in the RC time constant circuit 3 and the on-resistance of each MOS transistor in the charge / discharge circuit 4 can be set arbitrarily. In this case, one end of the capacitor in the RC time constant circuit 3 is connected to the power failure power line, but it may be connected to the high potential power line.

[0052]

According to the first aspect of the invention, by rapidly charging or discharging the capacitance in the RC time constant circuit by the charge / discharge circuit, the rise and fall times of the pulse signal input to the comparator are greatly shortened. Therefore, the waiting time can be greatly reduced. Therefore, it is possible to provide a delay circuit which can cope with a high frequency pulse signal having a short cycle.

According to the second aspect of the present invention, the charge / discharge circuit rapidly charges or discharges the capacitance in the RC time constant circuit, so that the rise and fall times of the pulse signal input to the comparator circuit having the hysteresis characteristic can be set. It can be greatly shortened, and the waiting time can be shortened accordingly. Therefore, it is possible to provide the delay circuit which is provided with the output stage having the hysteresis characteristic, and which can cope with the high frequency pulse signal having the short period.

Further, in this case, in the invention described in claim 3, since the charge / discharge circuit is composed of only four MOS transistors, in addition to the invention described in claim 1 or 2, The number of parts added to configure the discharge circuit is small, and in this case, the charge / discharge circuit is
Since it can be manufactured by the CMOS technology, it can be manufactured with almost no increase in circuit space and manufacturing cost as compared with the conventional circuit.

Further, in this case, according to the invention of claim 4, the comparison result signal of the first comparator having the low potential reference voltage VL as a reference voltage is inputted to the set terminal of the RS flip-flop, and the high potential reference voltage is applied. By inputting the comparison result signal of the second comparator having VH as the reference voltage to the reset terminal of the RS flip-flop, in addition to the invention described in claim 2 or 3, the normal comparator is combined. For example, it is possible to realize a comparator circuit having hysteresis equivalent to that of a Schmitt trigger circuit or a hysteresis comparator.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a delay circuit according to a first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a delay circuit according to a second embodiment.

FIG. 3 is a circuit diagram showing a configuration example of a comparator circuit having a hysteresis characteristic that replaces the hysteresis comparator in FIG.

FIG. 4 is a diagram showing voltage levels at respective nodes of the delay circuit shown in FIG.

5 is a composite diagram of each voltage level in FIG. 4. FIG.

FIG. 6 is an enlarged view of the first half portion of FIG.

FIG. 7 is an enlarged view of the latter half of FIG.

FIG. 8 is a circuit diagram showing a configuration of a conventional delay circuit.

9 is a diagram showing voltage levels at respective nodes of the delay circuit shown in FIG.

10 is a composite diagram of voltage levels in FIG. 9. FIG.

[Explanation of symbols]

1 Delay Circuit 2 First Inverter Circuit 2'Inverter Circuit 3 RC Time Constant Circuit 4 Charge / Discharge Circuit 5 Comparator 6 Second Inverter Circuit 7 Hysteresis Comparator (Comparator Circuit) 7'Comparator Circuit 8 First Comparator 9 Second Comparator 10 RS Flip Float The

[Formula 1]

[Formula 2]

[Formula 3]

[Formula 4]

Claims (4)

[Claims] 1. A delay circuit for outputting a pulse signal input from an input terminal from an output terminal after a lapse of a predetermined time, the input terminal being connected to the input terminal, and the output terminal being connected to the input terminal side of a next stage circuit. A first inverter circuit that outputs an inverted signal of the signal input from the input end from the output end, and an input end connected to the output end of the first inverter circuit, and an output end on the input end side of the next-stage circuit. And an RC time constant circuit composed of a resistor and a capacitor for determining the time constant of the delay time, and an input / output terminal connected to the output terminal of the RC time constant circuit.
A charging / discharging circuit for accelerating charging / discharging of the capacity in the C time constant circuit, and an input terminal connected to the input / output terminal of the charging / discharging circuit and an output terminal connected to the input terminal side of the next-stage circuit, When the potential level at the input / output terminal of the circuit is lower than the predetermined potential level, a low potential level is output from the output terminal, while the potential level at the input / output terminal of the charge / discharge circuit is higher than the predetermined potential level. A comparator that outputs a higher potential level than the output end, and an input end connected to the output end of the comparator, an output end connected to the output terminal, and an inverted signal of the signal input from the input end from the output end. A second inverter circuit for outputting, and a delay circuit comprising: 2. A delay circuit for outputting a pulse signal input from an input terminal from an output terminal after a lapse of a predetermined time, the input terminal being connected to the input terminal and the output terminal being connected to the input terminal side of a next stage circuit. Then, an inverter circuit that outputs an inverted signal of the signal input from the input end from the output end, while connecting the input end to the output end of the inverter circuit, and connecting the output end to the input end side of the next stage circuit, An RC time constant circuit composed of a resistor and a capacitance for determining the time constant of the delay time, and an input / output terminal connected to the output terminal of the RC time constant circuit,
A charging / discharging circuit for accelerating charging / discharging of the capacity in the C time constant circuit, and an input terminal connected to the input / output terminal of the charging / discharging circuit and an output terminal connected to the input terminal side of the next-stage circuit, When the potential level at the input / output end of the circuit is lower than the first potential level, a higher potential level is output than at the output end, and when the potential level at the input / output end of the charge / discharge circuit is higher than the second potential level, output A delay circuit comprising: a comparator circuit having a hysteresis characteristic that outputs a lower potential level from its end. 3. The charge / discharge circuit comprises a first P-channel MOS transistor between a high potential power line and a low potential power line,
Second P channel MOS transistor, second N channel M
The OS transistor and the first N-channel MOS transistor are connected in series in this order, and the second P-channel MO transistor is connected.
The connection point between the S transistor and the second N-channel MOS transistor is used as an input / output terminal, and the gates of the first P-channel MOS transistor and the first N-channel MOS transistor are commonly connected and connected to the input terminal. , The second P channel M
3. The delay circuit according to claim 1, wherein the gates of the OS transistor and the second N-channel MOS transistor are commonly connected to the output terminal. 4. The comparator circuit has a first comparator having one input terminal connected to an input / output terminal of the charging / discharging circuit and a low potential reference voltage applied to the other input terminal, and a high potential applied to one input terminal. While applying a reference voltage, the other input terminal is connected to the input / output terminal of the charging / discharging circuit, and the output terminal of the first comparator is connected to a set terminal, and the second comparator is connected. 4. The delay circuit according to claim 2, comprising an RS flip-flop having an output terminal connected to a reset terminal.