JP2003008423A - Bus interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus interface circuit that decreases waveform distortion of a signal transmitted through a bus signal line and increases the operating frequency of a system. SOLUTION: Each of the semiconductor devices 1a-1n coupled in common to a bus signal line 2 included in a common bus has the same bus interface circuit. The bus interface circuit includes a change detection circuit 4 that detects a change in a signal received via a signal terminal 3 coupled to the bus signal line 2 and a drive circuit 5 that drives the signal in the same direction as the change in the signal given to the signal terminal 3 according to the detection of the change in the signal by the change detection circuit 4. When the signal given to the bus interface circuit through the signal terminal 3 is changed, the change detection circuit 4 detects the change and the drive circuit 5 drives the signal through the signal terminal 3 according to the result of detection in the same direction as the signal change direction so as to reduce waveform distortion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit, and more particularly to a structure of a bus interface circuit coupled to a bus to which a plurality of semiconductor devices are commonly coupled. More specifically, the present invention relates to a configuration for reducing waveform distortion of signals transferred on a common bus.

[0002]

2. Description of the Related Art FIG. 14 is a diagram showing an example of the configuration of a conventional bus system. In the bus system shown in FIG. 14, the controller CTL and the modules M0 to Mn are coupled via a common bus CB. These modules M
0-Mn only needs to have a function of transmitting and receiving signals, and may be a single semiconductor device. Also, the controller CTL may have a function of transmitting and receiving signals,
It may be a processor.

A terminating resistor R is provided at both ends of the common bus CB.
T1 and RT2 are connected. These termination resistors RT
1 and RT2 terminate the common bus CB to the termination voltage VT. These terminating resistors RT1 and RT2 have the same impedance as the characteristic impedance of the common bus CB. The terminating resistor RT2 suppresses a reflected wave with respect to a signal transmitted from the controller CTL via the common bus CB, and the terminating resistor RT1 includes the modules M0 to Mn.
The reflected wave of the signal transferred from the controller to the controller CTL via the common bus CB is suppressed.

Termination resistors RT1 and RT2 having an impedance equal to the characteristic impedance of the common bus CB.
The common bus is terminated by using, to suppress the reflection of the transfer signal at the bus termination due to impedance mismatch, and the reflected wave of the transfer signal is superimposed on the transfer signal to cause distortion in the transfer signal waveform. To suppress the noise of the transfer signal.

By connecting a semiconductor device such as a module to the common bus CB using a stub (branch), the system configuration can be easily changed.

[0006]

FIG. 15 is a diagram schematically showing a resistance distribution in a conventional bus system. In FIG. 15, modules M0-Mn each have an input impedance and are coupled to the common bus CB via this input impedance (hereinafter referred to as stub resistance) RS0-RSn. Similarly, controller CTL
Is also coupled to common bus CB via stub resistor RST.

Therefore, for example, the controller CTL
When a signal is sent from the common bus CB to the common bus CB, the stub resistors RS0 to RSn of these modules M0 to Mn cause
The impedance of the bus fluctuates at the connection point between the common bus CB and the stub, and these stub resistances RS0-RSn
Causes a reflected wave. In the common bus CB, as shown in FIG. 16, the reflected wave is superimposed on the transfer signal at the connection point with each stub, and distortion such as ringing occurs in the transfer signal waveform. This ringing has a waveform that oscillates around the terminal voltage VT when the signal rises, and has a waveform that oscillates around the ground voltage GND when the signal falls.

Due to this ringing, when the transfer signal waveform changes beyond the input logic threshold value, it is impossible to accurately determine the logic of the signal. Therefore, it is necessary to take in a signal in each of the modules M0-Mn in a state where the ringing is suppressed and the voltage level of the transfer signal is stabilized to some extent. Therefore, during the period T in which ringing is occurring, the signal cannot be taken in, and the problem that the signal cannot be transferred at high speed occurs. In particular, when such transfer signal ringing occurs, the upper limit of the operating frequency of the entire system is determined by the ringing occurrence period T, which causes a problem that a system operating at high speed cannot be configured.

Therefore, an object of the present invention is to provide a bus interface circuit which can transfer signals at high speed without causing ringing.

Another object of the present invention is to provide a bus interface circuit which does not affect the impedance of the bus during signal transfer.

Still another object of the present invention is to provide a bus interface circuit capable of reducing distortion of transfer signal waveform.

[0012]

SUMMARY OF THE INVENTION A bus interface circuit according to the present invention has a change detecting means for detecting a change in a signal applied through a terminal, and the same terminal as the change according to the detection result of the change detecting means. A driving means for driving in the direction is provided.

Preferably, the change detecting means includes a circuit for generating a one-shot pulse signal in response to a signal change at this terminal.

Alternatively, preferably, the change detecting means is configured to compare the signal transmitted through the terminal with a reference voltage, and one-shot in response to the output signal of the comparing circuit. First to generate the pulse signal of
And a second pulse generation circuit. The drive means includes first and second drive transistors respectively arranged corresponding to the first and second pulse generation circuits and driving the terminals in response to the pulse signal from the corresponding pulse generation circuit. . These first and second drive transistors charge a terminal when one is conducting and the other is conducting when the other is conducting.
Discharge the terminals.

Alternatively, preferably, the change detecting means includes a first comparison circuit for comparing the signal applied through the terminal with the first reference voltage, and the signal applied through the terminal and the second comparison circuit. A second comparison circuit for comparing the reference voltage of
In response to the output signals of the first and second comparison circuits, the one having a pulse width from the change of the output signal of the first comparison circuit to the elapse of a predetermined time after the change of the output signal of the second comparison circuit. In response to the output signals of the first pulse generation circuit and the first and second comparison circuits that generate the shot pulse signal, the first change from the output signal of the second comparison circuit
A second pulse generating circuit for generating a one-shot pulse signal having a pulse width from the change of the output signal of the comparator circuit to the elapse of a predetermined time. The drive circuit includes a first drive transistor that charges the terminal in response to the pulse signal output to the first pulse generation circuit, and a first drive transistor that discharges the terminal in response to the pulse signal output to the second pulse generation circuit. Two
Drive transistor.

Preferably, the second reference voltage has a voltage level equal to or higher than the first reference voltage. Alternatively, preferably, the first pulse generation circuit includes a first inverter that receives the output signal of the first comparison circuit, and a first delay circuit that delays the output signal of the second comparison circuit. A second inverting delay circuit that inverts and delays the output signal of the second inverter, and a second inverting delay circuit when the output signal of the first inverter and the output signal of the second inverting delay circuit are both at the first logic level. A first gate circuit for generating a logic level signal. The second pulse generation circuit includes a second inverter that receives the output signal of the second comparison circuit, a second inverting delay circuit that delays and inverts the output signal of the first inverter, and a second inverter of the second inverter. A second gate circuit that outputs a signal of the first logic level when both the output signal and the output signal of the second inverting delay circuit are at the second logic level. The second inverter constitutes a part of the first delay circuit.

Preferably, the terminal is coupled to the signal bus having the characteristic impedance via the stub signal line, and the output impedance of the driving circuit is the impedance of the stub signal line and the internal wiring coupled to this terminal excluding the driving circuit. Is substantially equal to the sum.

Alternatively, preferably, the terminal is coupled to the signal line of the bus via the stub signal line, and the drive circuit includes a charge / discharge transistor for charging / discharging this terminal. The impedance of the charge / discharge transistor when it is conductive is equal to the sum of the impedances of the stub signal line and the internal wiring that are coupled to the terminals except the drive circuit.

By detecting a change in the signal applied through the terminal and driving the terminal in the same direction as this signal change, the stub signal line coupled to this terminal is moved in the same direction as the transferred signal. It can be charged and discharged, and the influence of the signal on the signal bus line on the signal can be suppressed. That is, by driving the stub signal line to the same voltage level as the voltage of the bus signal line, the stub signal line can be electrically separated from the bus signal line, which locally reduces the impedance of the bus signal line. It is possible to suppress the fluctuation from the characteristic impedance, prevent the reflected wave from being superimposed on the signal transmitted through the bus, and it is possible to transfer a signal having an accurate waveform at high speed.

[0020]

[First Embodiment] FIG. 1 is a diagram schematically showing a configuration of a bus system according to a first embodiment of the present invention. In FIG. 1, semiconductor devices 1a-1n are commonly coupled to a bus signal line 2 included in a common bus.
These semiconductor devices 1a-1n are shown in FIGS.
Controller CTL and module M0-Mn shown in
Corresponding to. Termination resistors RT1a and RT2a are arranged at both ends of the bus signal line 2. These terminating resistors RT1
a and RT2a have the same impedance as the characteristic impedance of the bus signal line 2, and terminate the bus signal line 2 at the termination voltage VT.

Each of semiconductor devices 1a-1n has the same bus interface circuit, and FIG. 1 representatively shows the configuration of the bus interface circuit of semiconductor device 1h.

The bus interface circuit applies a change detection circuit 4 for detecting a change in a signal applied through a terminal 3 coupled to the bus signal line 2 and a terminal 3 according to the change detection of the change detection circuit 4. It includes a drive circuit 5 that drives in the same direction as the generated signal change.

When change detection circuit 4 includes an input buffer, the output signal of the input buffer included in change detection circuit 4 is applied to internal circuit 6, and internal circuit 6 is provided with an input buffer. In this case, the signal at terminal 3 is applied to internal circuit 6 (these signal paths are indicated by broken lines).

In this bus interface circuit,
Always monitor the change of the signal given through terminal 3,
When a signal change occurs, the drive circuit 5 causes the terminal 3
Is driven in the same direction as the changing direction of the applied signal, the terminal 3 is driven at the same voltage level as the signal transmitted via the bus signal line 2 at high speed. Therefore, this terminal 3 is electrically separated from the bus signal line 2,
This terminal 3 has no effect on the signal transmitted via the bus signal line 2.

Therefore, the terminal 3 of the semiconductor device 1h
The impedance coupled to the other semiconductor device 1a
, And 1n are not affected. In each of the semiconductor devices 1a-1n, the bus interface circuit having the same configuration is arranged, and it is possible to suppress the variation of the characteristic impedance of the bus signal line 2 due to the stub connection, and it is possible to suppress the generation of the reflected wave. Accordingly, the ringing of the signal transferred via the bus signal line 2 can be suppressed and the signal can be transmitted at high speed.

That is, as shown in FIG. 2, when the signal transmitted via the bus signal line 2 is driven from the H level (termination voltage VT level) to the L level (ground voltage level), in the semiconductor device 1h. , The signal change at the terminal 3 is detected by the change detection circuit 4, and the drive circuit 5 drives the terminal 3 in the changing direction. Therefore, this bus signal line 2
The target reaching voltage level of the signal transmitted via the terminal 3 has already reached, and if the impedance mismatch occurs,
Even when a reflected wave exists, this reflected wave has already reached the target reaching voltage level, has the same voltage level as the signal transferred on the bus signal line 2, and is transmitted via the bus signal line 2. No ringing occurs on the signal.

Therefore, the signals transmitted to the input parts of the semiconductor devices 1a-1n are the same as those of the semiconductor devices 1a, 1h.
Transfer is performed according to the characteristic impedance of the bus signal line 2 without being affected by the stubs of. Semiconductor device 1n
The same bus interface circuit is provided for the input of, and the corresponding terminal is driven at high speed according to the signal transmitted through the bus signal line 2.
The target voltage level of this terminal 2 is reached. Bus signal line 2
Are terminated by terminating resistors RT1a and RT2a at both ends, and these terminating resistors RT1a and RT2 are terminated.
a has the same impedance as the characteristic impedance of the bus signal line 2. Therefore, even if a signal is transferred through the bus signal line 2, reflection does not occur at this terminal portion, and also in the semiconductor devices 1a-1n, the respective input portions or the corresponding stubs connect the bus signal line 2 to each other. It has already been driven to the target voltage level of the signal selected via. Equivalently and electrically, those semiconductor devices 1
Since a-1n is separated from the bus signal line 2, ringing does not occur in the signal transmitted via the bus signal line 2.
Therefore, the semiconductor devices 1a-1n can take in signals and perform internal processing without considering the ringing period T as shown in FIG. 16, and the cycle of transfer signals can be shortened. The operating frequency can be increased.

The signal in the transient state of the transfer signal is reflected by the impedance mismatch and is superimposed on the transfer signal to cause ringing. However, in this semiconductor device 1a-1n, by driving the terminal 3 to the target ultimate voltage level of the transfer signal, the signal change at the time of the transition is not reflected and the transfer signal is not affected. Therefore, from the viewpoint of the transfer signal, the semiconductor devices 1a-1n are equivalent to being electrically separated from the bus signal line 2, and the generation of reflected waves and ringing can be suppressed.

As described above, according to the first embodiment of the present invention, the change in the signal transferred from the bus signal line 2 to the stub signal line 2 is detected, and the corresponding terminal 3 is connected in the same direction in accordance with the change. The stub signal line is driven, and the stub signal line can be electrically separated from the bus signal line 2 equivalently, and the impedance accompanying the stub signal line affects the signal transferred on the bus signal line 2. There is no bus signal line 2
The signal can be transferred stably and at high speed according to the characteristic impedance of the bus signal line, and the operating frequency of the system can be increased.

[Second Embodiment] FIG. 3 shows a structure of a bus interface circuit according to a second embodiment of the present invention. The bus interface circuit includes a change detection circuit 4 and a drive circuit 5 as shown in FIG. The change detection circuit 4 receives the signal supplied through the terminal 3 and the reference voltage Vr.
ef, an inverter 11 that inverts the output signal of the comparison circuit 10, and an inverting delay circuit 12 that inverts the output signal of the inverter 11 and delays it for a predetermined time.
A 2-input NAND circuit 13 that receives the output signal of the inverter 11 and the output signal of the inverting delay circuit 12, and a 2-input NOR circuit 14 that receives the output signal of the inverter 11 and the output signal of the inverting delay circuit 12. The inverter 11 is
The output signal of the comparison circuit 10 is buffered and the internal circuit 6 is processed.
It has a function of a buffer circuit for transmitting to.

The drive circuit 5 conducts when the output signal of the NAND circuit 13 is at the L level, and supplies a charge P-channel MOS transistor 5a for supplying electric charge to the terminal 3 when conducting, and NO.
Discharge N-channel MOS that conducts when the output signal of the R circuit 14 is at H level and discharges electric charge from the terminal 3 when conducting.
The transistor 5b is included.

A voltage of the same voltage level as termination voltage VT applied to termination resistors RT1a and RT2a is applied to drive circuit 5 as a power supply voltage. However, drive circuit 5 may be supplied with a power supply voltage having a voltage level different from termination voltage VT. When the signal at terminal 3 changes, the voltage level may be determined according to the activation period by drive circuit 5 and its charge driving capability time.

Comparison circuit 10 is connected between a power supply node receiving power supply voltage VCC and node 10f, and a P channel MOS transistor 10a having its gate connected to node 10g, and a power supply node and node 10g. And between P-channel MOS transistor 10b having its gate connected to node 10g, N-channel MOS transistor 10c connected between node 10c and node 10h and having its gate coupled to terminal 3 and nodes 10g and 10h. Includes an N channel MOS transistor 10d connected to V.sub.2 and receiving the reference voltage Vref at its gate, and an N channel MOS transistor 10e connected between node 10h and the ground node and receiving bias voltage Vbi at its gate.

In this comparison circuit 10, MOS transistors 10a and 10b form a current mirror circuit, and the mirror current of the current flowing through MOS transistor 10b flows through MOS transistor 10a. Therefore, MOS transistors 10a and 10
When the sizes of b (the ratio of the channel width to the channel length) are equal, these MOS transistors 10a and 10
The same current flows through b.

MOS transistors 10c and 10d form a differential stage, and the voltage level of signal terminal 3 and reference voltage V
Compare with ref. The MOS transistor 10e functions as a constant current source transistor. Reference voltage Vref
Is the H level / L of the signal transferred through the bus signal line.
It is a voltage level that serves as a level determination standard, and is set to, for example, a voltage level that is 1/2 times the termination voltage VT.

The comparison circuit 10 is always operated regardless of the selected / non-selected state of the corresponding semiconductor device, and the terminal 3
Monitor for changes in the signal applied to. The operation of the bus interface circuit shown in FIG. 3 will now be described with reference to the signal waveform diagram shown in FIG.

When the signal applied to terminal 3 is at H level (termination voltage VT level), this termination voltage VT is higher than reference voltage Vref, the output signal of comparison circuit 10 is at low level, and the output of inverter 11 is output. The signal is at H level (internal power supply voltage VCC level). Therefore,
In this state, the output signal of the inverting delay circuit 12 is L
The output signal of the NAND circuit 13 is at the L level and the output signal of the NOR circuit 14 is at the L level. Therefore, the drive circuit 5 is in the output high impedance state.

When the signal applied to the terminal 3 falls from the H level and becomes lower than the reference voltage Vref, the comparison circuit 1
The voltage level of the output signal of 0 rises, and accordingly the output signal of the inverter 11 falls from the H level to the L level. When the output signal of the inverter 11 falls to L level,
Since the output signal of the inverting delay circuit 12 is still at L level, the output signal of the NOR circuit 14 becomes H level, and MO
S-transistor 5b is rendered conductive to discharge the charge on terminal 3 and the corresponding stub signal line, and the signal applied to terminal 3 is driven to the ground voltage level.

When the corresponding stub signal line reaches the signal voltage level transferred via the bus signal line (not shown) by charging / discharging terminal 3, the stub signal line substantially coupled to this terminal 3 is reached. However, the stub signal line coupled to this terminal 3 has no effect on the signal transferred via the bus signal line because it is electrically separated from the bus signal line.

When the output signal of inverting delay circuit 12 rises to the H level, the output signal of NOR circuit 14 attains the L level, and MOS transistor 5b is rendered non-conductive. During this period, the MOS transistor 5a maintains the non-conducting state.

Therefore, during the delay time of inverting delay circuit 12, MOS transistor 5b is rendered conductive, and the corresponding stub signal line is driven to the ground voltage level via terminal 3.

On the other hand, when the signal applied to the terminal 3 rises from the L level and becomes higher than the reference voltage Vref, MO
The conductance of the S transistor 10c becomes larger than the conductance of the MOS transistor 10e, and the current supplied via the MOS transistor 10a becomes
The node 1 is discharged through the MOS transistor 10c.
The voltage level of 0f lowers, and accordingly, the output signal of inverter 11 rises to the H level.

When the output signal of the inverter 11 becomes H level, the output signal of the inverting delay circuit 12 is still at H level, so that the output signal of the NAND circuit 13 becomes L level, the MOS transistor 5a becomes conductive, and the terminal is turned on. 3 is supplied with electric charge. At that time, the NOR circuit 14 outputs an L level signal when the output signal of the inverter 11 is at H level, and the MOS transistor 5b maintains the non-conduction state.

When the delay time of the inverting delay circuit 12 elapses, the output signal of the inverting delay circuit 12 becomes L level, the output signal of the NAND circuit 13 accordingly becomes H level, and the MOS transistor 5a becomes non-conductive. . Even if the output signal of the inverting delay circuit 12 becomes H level, the output signal of the inverter 11 is already at H level, the output signal of the NOR circuit 14 is at L level, and the MOS transistor 5b maintains the non-conductive state.

Therefore, when the signal at the terminal 3 rises, charges are supplied to the terminal 3 by the MOS transistor 5a during the delay time of the inverting delay circuit 12. Therefore, when the signal on the stub signal line coupled to this terminal 3 becomes H level at high speed and reaches the same voltage level as the signal to be transferred, the stub signal line coupled to this terminal 3 is electrically connected to the bus signal line. It is equivalent to the state of being physically separated.

When the terminal 3 is driven, the stub signal line coupled to the terminal 3 and the internal wiring (signal line) connected to the terminal 3 are also driven at the same time by supplying / releasing charges from the driving circuit 5. To be done. Also in the following description, when the terminal 3 is driven, the terminal 3 is driven unless otherwise specified.
The input capacitance by the stub signal line and internal wiring connected to is also charged and discharged at the same time.

Therefore, when the signal applied to the terminal 3 changes, the terminal 3 is driven in the same direction as the changing direction of the signal only for a predetermined time, the signal change is accelerated, and the signal is joined to the terminal 3. By charging and discharging the stub signal line and the input capacitance of the terminal 3 itself, it is possible to suppress the influence on the input waveform of the semiconductor device connected to another bus signal line.

The rate of change of the voltage at the terminal 3 may be approximately the same as the rate of change of the signal transferred through the bus signal line 2.

FIG. 5 is a diagram for explaining the drive charge amount of the drive circuit 5. In FIG. 5, terminal 3 is coupled to bus signal line 2 via stub signal line 20. The stub signal line 20 has a parasitic capacitance Cs. On the other hand, the terminal 3 has an input capacitance Ci due to its own internal wiring of the semiconductor device. This input capacitance Ci is the input capacitance of the comparison circuit 10 shown in FIG.
Corresponds to the signal line capacitance between the two. When the semiconductor device has a module configuration, the comparison circuit 10 is arranged commonly to the internal chips. If the terminal 3 is directly coupled to the module internal wiring, this input capacitance corresponds to the capacitance of the module internal wiring.

The drive circuit 5 charges and discharges the capacitors Cs and Ci associated with the terminal 3 with the charge / discharge current I thereof. Therefore, the drive charge amount required for the drive circuit 5 can be determined by the capacitance value of the capacitors Cs and Ci associated with the terminal 3 and the drive current I of the drive circuit 5. Therefore, the drive charge amount is the activation time of the drive circuit 5, that is, the delay time T of the inverting delay circuit 12.
According to D and the drive current I, it can be obtained by the following equation.

I · TD = VT · (Cs + Ci) The delay time TD of the inverting delay circuit 12 can be determined from the above relational expression. Even if the stub signal line and the internal wiring are excessively driven, the excessive charge flows to the bus signal line 2 and only assists the bus driving of the semiconductor device that transfers the signal, and no particular problem occurs. In particular, if the change time of the transfer signal of the bus signal line and the change time of the stub signal line are set to be approximately the same, overdrive of the bus signal line can be reliably prevented, and the occurrence of ringing can be suppressed. In addition, even if the driving speed of the stub signal line is higher than the changing speed of the bus signal line, the driving force of the driving circuit in the interface circuit is smaller than that of the driving circuit that drives the bus signal line, which is excessive. Overdrive of the transfer signal due to electric charges is suppressed, and even if such excess charge driving occurs, ringing does not occur in the transfer signal.

The delay time of the inverting delay circuit is determined by the drive current I of the drive circuit 5 at the final test of the manufacturing process.
May be adjusted by laser trimming (eg, fuse programming) or the like. In addition, FIG.
When the semiconductor device 1 is a semiconductor memory device, as shown in FIG.
5 are provided. Therefore, the delay time setting data is stored in the mode register 25, and the inverting delay circuit 12 is stored in accordance with the data stored in the mode register 25.
The delay time may be set. As a method of adjusting the delay time of the inverting delay circuit 12, a method such as changing the number of delay stages of the inverting delay circuit 12 and adjusting an operating current can be used.

When using this mode register 25,
Data can be externally stored in the mode register even after package mounting, and the amount of drive charge of each semiconductor device can be adjusted according to the actual system configuration during system mounting.

FIG. 7 is a diagram schematically showing an example of the configuration of the semiconductor device 1. In FIG. 7, the semiconductor device 1 is
It is a module and includes a plurality of chips CH0-CHm. These chips CH0-CHm are commonly coupled to bus interface circuit 30 via internal wiring 32. The bus interface circuit 30 includes a common bus C
Bound to B. Therefore, in the bus interface circuit 30, each bus signal line (2) of the common bus CB is
, A set of the terminal 3, the change detection circuit 4, and the drive circuit 5 is provided for each.

Therefore, even in such a module configuration, by providing the input buffer (comparator circuit) 10 shown in FIG. 3 in common to the chips CH0 to CHm, the chips CH0 to CHm directly connect to the internal wiring (signal line). The gate capacitance of this terminal 3 can be reduced as compared with the case of being coupled to an external terminal via 32. The output signal of inverter 11 shown in FIG. 3 is transmitted to internal wiring 32.

The output signals from the chips CH0-CHm are
It is also transmitted to the terminal 3. Internal bus wiring 32
In the case of a bidirectional bus, simply the bus interface circuit 3
0 transfers the internal signal from 0, and chips CH0-CHm
Transfer the output signal from. Simply, the signal transfer path is
The only difference is the terminal bus interface circuit 30. In this case, the terminal 3 and the internal wiring 32 may be separated when the semiconductor device 1 is in the non-selected state or in the signal input mode. It is possible to prevent the output signal of the inverter 11 from being transferred to the terminal 3 via the internal wiring 32. In this case, the output signal of the inverter 11 is transmitted to the internal chips CH0-CHm via the internal wiring.

FIG. 8 is a diagram showing an example of the configuration of the internal circuit of the semiconductor device. In FIG. 8, terminal 3 is coupled to interface circuit 40. This interface circuit 40 is provided corresponding to one signal terminal 3, and includes a change detection circuit 4 and a drive circuit 5. The internal signal line 41 is coupled to the terminal 3. The output signal of the interface circuit 40 is not transmitted to the internal signal line 41. An internal input circuit 42 and an output circuit 44 are commonly coupled to the internal signal line 41. When this semiconductor device is a module, the input buffer and the output buffer of each chip are commonly connected.

The internal signal line 41 is connected to the internal input circuit 4
2 and the output circuit 44 are commonly connected to the terminal 3.
The output signal of the interface circuit 40 is not given to the input circuit 42. The interface circuit 40 simply
A signal change at the terminal 3 is detected, and charging / discharging of the terminal 3 is performed according to this signal change. Therefore, the internal signal line 4
Even when 1 is commonly coupled to the input circuit 42 and the output circuit 44, the output signal of the inverter 11 of the interface circuit 40 is transmitted to the terminal 3, the terminal 3 is driven by the inverter 11, and the next data change. Until,
This terminal 3 is prevented from being driven by the inverter and holding its voltage level. Thus, in the semiconductor devices 1a-1h, it is possible to prevent a signal / data collision between a semiconductor device that inputs a signal and a semiconductor device that outputs a signal.

That is, in the semiconductor device for inputting data / signal, in order to prevent the collision of the terminal 3 in the driving direction, as shown in FIG. 3, the NAND circuit 13 and the NOR circuit 14 and the inverting delay circuit 12 are provided. And constitute a one-shot pulse generation circuit, and in the input side semiconductor device, the terminal 3 is driven by one shot. In the output side semiconductor device, when the driving circuit 5 of itself is driving the terminal 3, collision of the driving direction of the terminal 3 occurs when the output signal / data changes, and the signal / output can be transferred at high speed. Can not.

When the output side semiconductor device and the input side semiconductor device are different from each other, if the input side semiconductor device drives the corresponding stub signal line in accordance with the previous signal / data, the output of the output side semiconductor device is next. When the logic level of the signal / data is changed, the charge driving directions of the input side semiconductor device and the output side semiconductor device are different, and the signal transferred via the bus signal line 2 is output at high speed at the output side semiconductor device output signal / data. Can not be changed according to. In order to prevent such a collision, the drive circuit is driven for one shot, and when the signal transferred on the bus signal line 2 changes next, the drive circuit 5 is set to the output high impedance state and according to the output signal of the output side semiconductor device. , The signal transferred through the bus signal line 2 is changed at high speed.

Further, in the semiconductor device 1, the comparison circuit 1
When the output signal of the internal output circuit is transmitted to the node of the inverter 11 which receives the output signal of 0, the drive circuit 5 drives the signal terminal 3, but in that case, the inverting delay circuit 12 determines the drive period. Therefore, there is a possibility that the bus signal line 2 cannot be sufficiently driven via the stub signal line 20 according to the output data / signal.
As shown in FIG. 8, by coupling the internal signal line 41 to the terminal 3, the bus signal line 2 is accurately transmitted through the terminal 3 and the stub signal line in accordance with the output signal of the output circuit 44.
Can be driven.

FIG. 9 shows another structure of the internal circuit. In FIG. 9, terminals 3a and 3b are a signal / data input terminal and a signal / data output terminal, respectively. Interface circuits 40a and 40b are provided for these terminals 3a and 3b, respectively.
Each of these interface circuits 40a and 40b includes change detection circuit 4 and drive circuit 5 shown in FIG. The output signal of the interface circuit 40a is given to the input circuit 42. On the other hand, the terminal 3b is coupled to the output circuit 44. Interface circuits 40a and 40b are provided corresponding to the input circuit 42 and the output circuit 44, respectively. As a result, in one semiconductor device, signals /
At the time of outputting data, when the signal potential of the bus signal line 2 changes according to the drive of the output side semiconductor device, it is prevented that the impedance of the output circuit and the stub signal line of the other non-selected semiconductor device is adversely affected. be able to.

Here, the bus signal line coupled to the terminal 3b is driven by the output drive circuit of the output side semiconductor device, and the output circuit 44 of the other non-selected semiconductor device is in the high impedance state. The interface circuit 40b can surely suppress the generation of a reflected wave on the stub signal line connected to the terminal 3b.

As described above, according to the second embodiment of the present invention, the change in the signal at the terminal is detected, and the corresponding terminal is driven by one shot according to the detection result.
The terminal 3 can be charged and discharged according to the transfer signal, and the stub signal line can be electrically disconnected from the bus signal line.

When this terminal is maintained in the state according to the transfer signal until the next change of the signal / data,
When the next transfer signal changes, the driving direction of the semiconductor device on the signal / data output side may collide with the driving direction of the semiconductor device on the signal / data input side, so that the signal / data transfer can be performed. It may run out. Even when the driving force of the driving circuit in the interface circuit is smaller than the driving force of the output driver that drives the bus signal line, the number of input side semiconductor devices is larger than the number of output side semiconductor devices, and the bus signal line 2 is Driven in the opposite direction. By performing such one-shot driving, the stub signal line is electrically separated from the corresponding bus signal line only during the period when the ringing or the reflected wave may occur, thereby suppressing the ringing and reducing the waveform distortion. Signals can be transferred.

[Third Embodiment] FIG. 10 shows a structure of a bus interface circuit according to a third embodiment of the invention. In the structure of the bus interface circuit shown in FIG. 10, comparison circuit 10 and inverter 11 shown in FIG. 3 are not provided. The inverting delay circuit 12 is coupled to the terminal 3, and the first inputs of the NAND circuit 13 and the NOR circuit 14 are coupled to the terminal 3. Therefore, NAND circuit 13 and inverting delay circuit 12 generate a one-shot pulse signal in response to the rising of the signal / data at terminal 3, while inverting delay circuit 12 and NOR circuit 14 cause terminal 3 to generate a pulse signal.
A one-shot pulse signal is generated in response to the trailing edge of the signal / data. The pulse signal output from the NAND circuit 13 is at L level when generated, while the one-shot pulse generated by the NOR circuit 14 is at H level when generated.

This NAND circuit 13 and NOR circuit 1
The output signal of No. 4 is given to the input / output circuit 50. The input / output circuit 50 is composed of a circuit for inputting / outputting complementary signals.
Therefore, in the input / output circuit 50, this NAND
When one of the circuit 13 and the NOR circuit 14 is generating a one-shot pulse signal, the logic level of the output signal is the same, so the input circuit of the input / output circuit 50 determines the input signal during that time. Instead, the differential input is judged after the one-shot pulse generation is completed. On the other hand, the output circuit of the input / output circuit 50 drives the signal terminal 3 via the drive circuit 5. Therefore, the drive circuit 5 is also used as a driver when outputting a signal.

In the case of the configuration shown in FIG. 10, the comparison circuit 1
0 and the inverter 11 are not provided, and the output signals of the NAND circuit 13 and the NOR circuit 14 change in response to the signal change of the terminal 3, so that they are affected by the gate delay of the comparison circuit 10 and the inverter 11. Without
In response to the signal change of the terminal 3, the terminal 3 can be driven in the signal change direction at high speed. Therefore, when the input capacitance of the terminal 3 is relatively large, the terminal 3 can be driven at an early timing, and the stub signal line coupled to the terminal 3 can be reliably separated from the corresponding bus signal line. it can.

In the structure shown in FIG. 10, input / output circuit 50 may be directly coupled to terminal 3 (see FIG. 8). That is, the signal from terminal 3 is applied to input / output circuit 50, and the signal from input / output circuit 50 is transmitted to the corresponding bus signal line via terminal 3. The drive circuit 5 is optimized only for charging / discharging the terminals when the signal changes, and signal / data output is performed by the output drive circuit of the input / output circuit 50. As a result, a signal can be transferred at high speed through the bus signal line, and the driving force of the driving circuit 5 can be optimized so as to charge and discharge the parasitic capacitance connected to the terminal 3 within a required time. You can

As described above, according to the third embodiment of the present invention, this terminal is driven in the same direction as the signal change in one shot in response to the signal change at the terminal, and the signal terminal is driven at an early timing. This terminal can be driven, and even if the input capacitance of this terminal is large, this terminal can be charged and discharged at an early timing, a gentle signal change can be prevented, and the terminal 3 is transferred at an early timing. Can be charged and discharged to the same voltage level as the signal, and when the signal changes,
The terminal 3 and the stub signal line can be reliably separated from the bus signal line.

[Fourth Embodiment] FIG. 11 shows a structure of a bus interface circuit according to a fourth embodiment of the present invention. 11, the bus interface circuit includes a comparison circuit 60 that compares the signal on the terminal 3 with the reference voltage Vrefh, an inverter 61 that inverts the output signal of the comparison circuit 60, and an inversion and delay of the output signal of the inverter 61. Inversion delay circuit 62, comparison circuit 63 that compares the output signal of signal terminal 3 and reference voltage Vrefl, inverter 64 that inverts the output signal of comparison circuit 63, and the inversion of the output signal of inverter 64 and delay by a predetermined time. Inverting delay circuit 65, a NAND circuit 66 that generates a one-shot pulse signal according to the output signal of the inverter 61 and the output signal of the inverting delay circuit 65, and the inverting delay circuit 6
It includes a NOR circuit 67 that generates a one-shot pulse according to the output signal of 2 and the output signal of inverter 64.

The reference voltage Vrefh is the reference voltage Vref.
The voltage level is lower than 1. The comparator circuit 60 outputs a low level signal when the signal at the terminal 3 is higher than the reference voltage Vrefh, and outputs a high level signal when the signal at the signal terminal 3 is lower than the reference voltage Vrefh. Output a signal.

Similarly, the comparison circuit 63 outputs a low-level signal when the signal at the signal terminal 3 is higher than the reference voltage Vrefl, while the signal at the terminal 3 is at the reference voltage Vrefl.
If it is lower than that, a high level signal is output.

These comparison circuits 60 and 63 have the same structure as that of the comparison circuit 10 shown in FIG. 3 and have the structure of a current mirror type differential amplifier circuit, and the bias voltage Vb.
The drive current is determined by i.

These comparator circuits 60 and 63 may operate in an analog manner to output a signal corresponding to the voltage difference between the input signal pair, or may operate in a digital manner to output a binary signal. Is also good.

The bus interface circuit further includes N
It includes drive circuit 5 which drives signal terminal 3 in accordance with the output signals of AND circuit 66 and NOR circuit 67. This drive circuit 5 is similar to the previous second and third embodiments in that when the output signal of NAND circuit 66 is at L level, charging MOS transistor 5a for supplying electric charge to signal terminal 3 and NOR circuit.
It includes a discharging MOS transistor 5b which conducts when the output signal of circuit 67 is at the L level and discharges charges from signal terminal 3. Next, the operation of the bus interface circuit shown in FIG. 11 will be described with reference to the signal waveform diagram shown in FIG.

The signal at the terminal 3 falls from the H level,
When it becomes lower than the reference voltage Vrefl, the output signal of the comparison circuit 63 becomes high level, and accordingly the output signal of the inverter 64 falls from H level to L level. When the output signal of the inverter 64 falls to the L level, the output signal of the inverting delay circuit 62 is still at the L level, so N
The output signal of OR circuit 67 rises to H level, discharge MOS transistor 5b becomes conductive, and terminal 3 is discharged.

Next, the signal at the terminal 3 changes to the reference voltage Vre.
When it becomes lower than fh, the output signal of the comparison circuit 60 becomes high level and the output signal of the inverter 61 falls to H level. Even if the output signal of inverter 61 falls to the L level, the output signal of NAND circuit 66 maintains the H level and MOS transistor 5a maintains the non-conductive state. When inverting delay circuit 62 raises its output signal to the H level in accordance with the output signal of inverter 61, N
The output signal of the OR circuit 67 becomes L level, and the discharge MO
The S transistor 5b is turned off, and the discharging operation of the terminal 3 is completed. Further, before the output signal of the inverting delay circuit 62 rises to the H level, the inverter 64
In response to the fall of the output signal of, the output signal of inverting delay circuit 65 rises to the H level. However, the output signal of the inverter 61 is already at the L level, and even if the output signal of the inverting delay circuit 65 rises to the H level, the NA
The output signal of the ND circuit 66 is at the H level, and the charging M
The OS transistor 5a maintains the non-conduction state.

Therefore, when the signal at the terminal 3 is a signal driven from the H level to the L level, the reference voltage Vr
When the voltage level of the signal at the terminal 3 becomes lower than that of efl,
Since the discharge operation is immediately started, the discharge operation period can be lengthened as compared with the case where the reference voltage Vref is at the intermediate voltage level (the delay time of the inversion delay circuits 62 and 65 is shown in FIG. 3). (When the delay time is the same as that of the inverting delay circuit 12).

On the other hand, when the signal at the terminal 3 rises from the L level to the H level, the signal at the terminal 3 changes to the reference voltage Vre.
When it becomes higher than fh, the output signal of the comparison circuit 60 becomes low level, and accordingly the output signal of the inverter 61 rises to H level. When the output signal of the inverter 61 rises to the H level, the output signal of the inverting delay circuit 65 is still at the H level, so that the output signal of the NAND circuit 66 is at the L level.
Then, the charging MOS transistor 5a becomes conductive, and the terminal 3 is charged.

Then, the signal at the terminal 3 changes to the reference voltage Vre.
When it becomes higher than fl, the output signal of the comparison circuit 63 becomes low level, and accordingly the output signal of the inverter 64 rises to H level. Even if the output signal of inverter 64 rises to the H level, the output signal of NOR circuit 67 maintains the L level, and discharge MOS transistor 5b maintains the non-conductive state.

The output signal of inverting delay circuit 62 changes from H level to L level in response to the rise of the output signal of inverter 64.
When it falls to the level, the output signal of the NAND circuit 66 becomes H level.
Then, the charging MOS transistor 5a becomes non-conductive.

The output signal of inverting delay circuit 62 falls to L level in response to the falling of the output signal of inverter 61 at a timing earlier than the falling of the output signal of inverting delay circuit 65. The output signal of the inverting delay circuit 62 is L
Even if it falls to the level, the output signal of inverter 64 is already at the H level, and the output signal of NOR circuit 67 maintains the L level.

Therefore, even during this charging operation,
When the signal at the terminal 3 becomes higher than the reference voltage Vrefh, the charging operation is started immediately, and the completion of the charging operation is continued until the signal at the signal terminal 3 exceeds the reference voltage Vrefl and a further predetermined time elapses. To be done. Therefore, this charging period can be lengthened.

That is, in the semiconductor device on the signal input side, by increasing the charging / discharging time, the stub signal line and the input capacitance can be charged / discharged at high speed, and the driver (output side) for driving this bus signal line Drive load of the semiconductor device) (including the case where the output side and the input side semiconductor devices are the same). Thereby, the waveform distortion of the transfer signal can be reduced and the signal can be transferred at high speed. Further, when the charging / discharging time is lengthened, excess drive charge due to charging / discharging of the stub signal line and the input capacitance is used for driving the bus signal line. As a result, the load on the bus signal line driver of the output side semiconductor device is reduced, and signals can be transferred at high speed. Even in this case, the semiconductor device connected to the bus signal line is
The charge / discharge operation completes the charge / discharge of this stub signal line and input capacitance, and it is electrically disconnected from the bus signal line.The load capacitance of the bus signal line is small, and ringing due to overdrive occurs. Is unlikely. That is, the drive circuit 5 is only required to drive the stub signal line and the input capacitance, and is not required to drive the entire bus signal line, and its drive capability is relatively small, and overdrive does not occur. It does not occur and the possibility of ringing is small.

Therefore, by lengthening the charging / discharging operation time of the semiconductor device on the input side as much as possible, the load on the driver of the semiconductor device on the output side can be reduced, and the load on the drive bus signal line can be reduced. A signal without signal distortion can be transferred at high speed.

As described above, the fourth embodiment of the present invention
According to the above, the charging / discharging time of the input side semiconductor device is configured to be as long as possible, the load of the driver of the output side semiconductor device is reduced, and a signal with less signal waveform distortion can be transferred at high speed.

In the structure of the bus interface circuit shown in FIG. 11, the internal input / output circuit is coupled to signal terminal 3. Further, as in the first embodiment, the internal input circuit and the output circuit are provided separately, and when they are coupled to different terminals, the bus interface circuit shown in FIG. 11 has an input terminal and an output terminal. Combined with each. When the input terminal and the output terminal are separately provided, for example, in the memory controller, a write data bus for transferring write data and a read data bus for transferring read data are separately provided, and the write of the memory controller is performed. The load during data transfer is reduced,
Further, the load on the output driver of each memory when the read data is transferred from the memory to the memory controller is reduced.

[Fifth Embodiment] FIG. 13 schematically shows a structure of a main portion of a bus interface circuit according to a fifth embodiment of the present invention. In FIG. 13, the terminal 3 is coupled to the bus signal line 2 via the stub signal line 70.
The stub signal line 70 has a parasitic impedance Z1 and the signal terminal 3 has a parasitic impedance Z2 due to the gate capacitance of the internal wiring and the internal circuit. Therefore, the parasitic impedance (Z
1 + Z2) exists, and this parasitic impedance (Z1 +
Z2) is the amount of increase in impedance that occurs in the bus signal line 2 because the stub signal line 70 is coupled to the bus signal line 2.

Charging MOS transistor 5 of drive circuit 5
a and the discharging MOS transistor 5b are respectively
When conducting, it has channel resistances RP and RN. The charging / discharging operation is performed through these channel resistors RP and RN. Therefore, when the parasitic impedance (Z1 + Z2) and the channel resistances RP and RN associated with the terminal 3 are in an impedance mismatched state, ringing may occur at the terminal 3 due to this charging / discharging operation. Therefore, these MOS transistors 5
The impedances (channel resistances) RP and RN of a and 5b are made equal to the parasitic impedance (Z1 + Z2) of the signal terminal 3, respectively.

Parasitic impedance of terminal 3 (Z1 + Z
In a state where the impedances of 2) and the channel resistances RP and RN are matched, the terminal 3 is charged and discharged to suppress the occurrence of ringing. That is, the channel resistances RP and RN are used as terminating resistors of the stub signal line to prevent generation of reflected waves of the signal transferred from the bus signal line 2 at the terminal 3.

The MOS transistor 5a for charging / discharging
The drain junction capacitances of 5 and 5b are included in the parasitic impedance Z2 of the terminal 3.

As described above, according to the fifth embodiment of the present invention, the impedance increase amount due to the addition of the stub is made equal to the impedance of the corresponding charge / discharge transistor for driving the terminal, and the signal of the bus signal line is When the stub signal line is charged / discharged in accordance with the change of, the ringing due to the reflected wave on the stub signal line can be suppressed by this charging / discharging operation, and the bus signal line can be accurately and quickly operated. Without adversely affecting the transmitted signal,
The stub signal line and the parasitic capacitance of the terminal can be charged and discharged.

Further, by utilizing the channel resistance of the charge / discharge transistor as the terminal resistance of the stub signal line, it is possible to prevent a reflected wave from being generated by the transfer signal at the terminal, and transfer the bus signal line at the time of charge / discharge. It is possible to prevent the generated signal waveform from being distorted.

[Other Embodiments] The semiconductor device including the bus interface circuit may be any semiconductor device coupled via a common bus.
It may be either a logic circuit or a processing circuit.

[0096]

As described above, according to the present invention, the change in the signal applied through the terminal is detected, and the terminal is driven in the same direction as this signal change according to the change detection result. Therefore, even when a plurality of semiconductor devices are coupled to the bus signal line, the characteristic impedance change of the bus signal line can be suppressed, and accordingly, the generation of the waveform distortion in the stub portion can be suppressed. It is possible to transfer a signal with a small amount of noise and to construct a system with a high operating frequency.

Further, by generating a one-shot pulse signal in response to a signal change, and driving this signal terminal by a one-shot pulse, when a plurality of semiconductor devices are coupled to the bus signal line, It is possible to prevent the change of signals on the line from colliding, and it is possible to transfer a required signal at high speed through the bus signal line.

Further, by comparing the reference voltage and the signal of the signal terminal, generating a one-shot pulse signal according to the comparison result, and charging and discharging the signal terminal via the drive transistor, the signal change is accurately detected. Then, the terminal can be driven to perform charging / discharging.

Further, by providing the first and second pulse generating circuits as the detecting means and comprising the drive transistors for charging and discharging the signal terminals in response to the output signals of these pulse generating circuits, respectively. With a simple circuit configuration, the signal terminal can be driven by one shot according to a signal change for charging / discharging, and the required charge can be driven, and the signal terminal and the stub can be reliably driven. Can be electrically separated from the corresponding bus signal line.

Further, the detecting means is composed of the comparing circuits for comparing with the first and second reference voltages and the circuits for respectively generating the one-shot pulse signals according to the output signals of these comparing circuits. When the signal changes, you can start charging / discharging the bus at an early timing, extend the charging / discharging time of the input side semiconductor device, reduce the load on the output side semiconductor device, and transfer signals with less waveform distortion at high speed. can do.

By changing the voltage level of the reference voltage, the bus can be charged and discharged at an early timing when the signal rises and falls, and the bus signal of the semiconductor device on the input side can be reliably carried out. The driving of the stub signal line coupled to the line and the input capacitance can be lengthened, and the load on the bus signal line driver on the signal output side can be reduced.

The first and second pulse generation circuits are driven according to an inverter that inverts the output signal of the comparison circuit, a delay signal of the output signal of another comparison circuit, and the output signal of the first inverter. By configuring the gate circuit that drives the transistor and the gate circuit that receives the inverter output signal that inverts the output signal of the different delay circuit and the output signal of the different comparison circuit to drive the different drive transistor with certainty, The charging / discharging time of the signal terminal can be lengthened.

When this terminal is coupled to the bus signal line via the stub signal line, the output impedance of the drive circuit is the total impedance of the input capacitances of the stub signal line and internal wiring coupled to this terminal. When the drive circuit drives the terminal, ringing at the terminal can be suppressed, and the stub signal line and the input capacitance can be charged and discharged accurately and reliably.

Further, by making the impedance of the charge / discharge transistor of the drive circuit in the conductive state equal to the impedance of the stub signal line, the impedance matching of the stub signal line and its associated input capacitance can be easily achieved. . Accordingly, the stub signal line can be accurately terminated, and the signal transferred through the bus signal line can be prevented from being reflected at the terminal and generating a reflected wave.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing transfer signal waveforms of the semiconductor device shown in FIG.

FIG. 3 is a diagram showing a structure of a bus interface circuit according to a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram showing an operation of the bus interface circuit shown in FIG.

5 is a diagram for explaining a charge / discharge operation of the drive circuit shown in FIG.

FIG. 6 is a diagram schematically showing a configuration for setting a bus drive time.

FIG. 7 is a diagram schematically showing an internal configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a diagram schematically showing connections between internal circuits and signal terminals of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a diagram schematically showing another example of the connection between the signal terminal and the internal circuit of the semiconductor device in the second embodiment of the present invention.

FIG. 10 shows a structure of a bus interface circuit according to a third embodiment of the invention.

FIG. 11 shows a structure of a bus interface circuit according to a fourth embodiment of the invention.

12 is a signal waveform diagram representing an operation of the bus interface circuit shown in FIG.

FIG. 13 is a diagram schematically showing a configuration of a bus interface circuit according to a fifth embodiment of the present invention.

FIG. 14 is a diagram schematically showing an example of the configuration of a conventional bus system.

15 is a diagram schematically showing an impedance distribution of the bus system shown in FIG.

16 is a diagram schematically showing transfer signal waveforms of the bus system shown in FIG.

[Explanation of symbols]

1a-1n, 1 semiconductor device, 2 bus signal lines, 3 terminals, 4 change detection circuit, 5 drive circuit, 6 internal circuit,
RT1a, RT2a terminal resistance, 10 comparison circuit, 11
Inverter, 12 inversion delay circuit, 13 NAND circuit, 14 NOR circuit, 5a charging MOS transistor, 5b discharging MOS transistor, 25 mode register, CH0-CH4 chip, 30 bus interface circuit, 32 internal bus wiring, 40, 40a, Four
0b interface circuit, 42 input circuit, 44
Output circuit, 3a input terminal, 3b output terminal, 50 input / output circuit, 60,63 comparison circuit, 61,64 inverter, 62,65 inversion delay circuit, 66 NAND circuit, 67 NOR circuit, RT, RN channel resistance, 7
0 Stub signal line.

Claims (9)

[Claims] 1. A bus interface circuit comprising: change detecting means for detecting a change in a signal given through a terminal; and drive means for driving the terminal in the same direction as the change in accordance with a detection result of the change detecting means. . 2. The bus interface circuit according to claim 1, wherein the detection means includes a circuit that generates a one-shot pulse signal in response to a signal change at the terminal. 3. The detection means includes a comparison circuit for comparing a signal transmitted through the terminal with a reference voltage, and a one-shot pulse signal generated in response to an output signal of the comparison circuit. A first pulse generating circuit and a second pulse generating circuit, wherein the driving means are arranged corresponding to the first pulse generating circuit and the second pulse generating circuit, respectively, and the terminal is responsive to a pulse signal from the corresponding pulse generating circuit. 2. A first and a second drive transistor for driving, wherein the first and the second drive transistor charge the terminal when one is conductive and discharge the terminal when the other is conductive. Bus interface circuit. 4. The first detecting means includes a first pulse generating circuit for generating a one-shot pulse signal in response to a change of the signal at the terminal to a first logic level; A second pulse generating circuit that generates a one-shot pulse signal in response to a change to a logic level of 2; and the driving unit outputs the one-shot pulse signal output from the first pulse generating circuit. A first drive transistor that responds to charge the terminal, and a second drive transistor that discharges the terminal in response to a one-shot pulse signal output from the second pulse generation circuit. 1. The bus interface circuit according to 1. 5. The first detection circuit, wherein the detection means compares a signal supplied via the terminal with a first reference voltage, and a signal supplied via the terminal with a second reference voltage. A second comparison circuit for performing the following, and, in response to the output signals of the first and second comparison circuits,
A first shot pulse signal having a pulse width from the change of the output signal of the first comparison circuit to the elapse of a predetermined time after the change of the output signal of the second comparison circuit is generated.
In response to the output signals of the pulse generator circuit and the first and second comparator circuits,
A second one for generating a one-shot pulse signal having a pulse width from the change of the output signal of the second comparison circuit to the elapse of a predetermined time from the change of the output signal of the first comparison circuit;
A pulse generating circuit of the first pulse generating circuit, the drive circuit is configured to charge the terminal in response to a pulse signal output from the first pulse generating circuit, and an output of the second pulse generating circuit. 2. The bus interface circuit according to claim 1, further comprising a second drive transistor that discharges the terminal in response to the pulse signal. 6. The bus interface circuit according to claim 5, wherein the second reference voltage has a voltage level higher than or equal to the first reference voltage. 7. The first pulse generating circuit includes a first inverter that receives the output signal of the first comparison circuit, a first delay circuit that delays the output signal of the second comparison circuit, and A first gate circuit that generates a signal of a second logic level when both the output signal of the first inverter and the output signal of the first delay circuit are at the first logic level; The pulse generation circuit includes a second inverter that receives the output signal of the second comparison circuit, a second inverting delay circuit that delays and inverts the output signal of the first inverter, and a second inverter of the second inverter. A second gate circuit which outputs a signal of the first logic level when both the output signal and the output signal of the second inverting delay circuit are at the second logic level; and the second inverter, Part of the delay circuit To formed, the bus interface circuit according to claim 5, wherein. 8. The terminal is coupled to a signal line of a bus via a stub signal line, and the output impedance of the driving circuit is an impedance of a stub signal line and an internal signal line coupled to the terminal excluding the driving circuit. 2. The bus interface circuit of claim 1, which is equal to the sum of 9. The terminal is coupled to a signal line of a bus via a stub signal line, the drive circuit includes a charge / discharge transistor for charging / discharging the terminal, and The bus interface circuit according to claim 1, wherein the impedance is equal to a sum of impedances of the stub signal line and the internal wiring excluding the drive circuit.