JP2008187475A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit for preventing malfunction due to a noise applied to a power supply line. <P>SOLUTION: This power-on reset circuit 1 is provided with a set signal generation part 11 for generating a set signal S by detecting a time from the rising of a positive voltage power source VDD for logic to be cast for the first till the rising of a positive voltage power source VGG for an LCD panel to be cast for the third; a flip flop circuit 12 for outputting a reset signal for an internal circuit when it is set by the set signal S; and a reset signal generation part 13 for delaying a signal generated by detecting the falling of a negative voltage power source VEE for the LCD panel to be cast for the second till the completion of the casing of the positive voltage power source VGG for the LCD panel, and for outputting it as a reset signal R for the flip flop to hold the flip flop circuit 12 after the completion of the casing of the positive voltage power source VGG for the LCD panel in a reset state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power-on reset circuit.

  A semiconductor integrated circuit in which scanning line driving circuits of an LCD (liquid crystal display) panel are integrated generates a plurality of driving signals for driving a plurality of scanning lines inside the LCD panel based on vertical shift data and a vertical shift clock. . For this reason, the scanning line driving circuit is provided with a shift register for transferring vertical shift data in synchronization with the vertical shift clock.

  This shift register operates with a low voltage positive voltage power supply VDD and a ground potential (reference potential) power supply GND, but the LCD panel is driven with a high voltage positive voltage power supply VGG and a negative voltage power supply VEE. A semiconductor integrated circuit in which a drive circuit is integrated is also provided with a level conversion circuit.

  That is, a positive voltage power supply VDD and a reference potential power supply GND as logic circuit power supplies, and a positive voltage power supply VGG and a negative voltage power supply VEE as LCD panel power supplies are input to a semiconductor integrated circuit in which a scanning line driving circuit is integrated. The

  When power is supplied to the semiconductor integrated circuit, first, the logic positive voltage power supply VDD is turned on, and then the LCD panel positive voltage power supply VGG and the negative voltage power supply VEE are turned on.

  A semiconductor integrated circuit in which the scanning line driving circuit is integrated is provided with a power-on reset circuit that generates a reset signal for fixing the initial value of the shift register when the power is turned on.

  Conventionally, as this power-on reset circuit, a circuit using the above-described power-on sequence to the semiconductor integrated circuit has been proposed (see, for example, Patent Document 1). This conventional power-on reset circuit has an inverter composed of a P-channel MOS transistor and an N-channel MOS transistor connected between a logic positive voltage power supply VDD and a reference potential power supply GND. By inputting the voltage power supply VGG, a reset signal is output from the rise of the logic positive voltage power supply VDD to the rise of the LCD panel positive voltage power supply VGG.

  By providing such a power-on reset circuit, the shift register of the scanning line driving circuit is reset when the power is turned on, and the output level in the initial state is fixed.

  However, noise in the power supply line of the semiconductor integrated circuit increases due to an increase in the load on the scanning line driving circuit due to the recent increase in the screen of the LCD panel and an increase in the resistance of the power supply line due to the progress of miniaturization of the semiconductor integrated circuit. However, due to the influence, a malfunction is likely to occur in the conventional power-on reset circuit.

This malfunction occurs when noise is applied to the LCD panel positive voltage power supply VGG, which is the input to the inverter of the power-on reset circuit, and when the potential drops below the inverter threshold, the output of the inverter is inverted and the reset signal is Generated by output.
JP 2006-24122 A (Page 4, FIG. 1)

  Therefore, an object of the present invention is to provide a power-on reset circuit that can prevent malfunction due to noise applied to a power supply line.

  According to one aspect of the present invention, there is provided a power-on reset circuit mounted on a semiconductor integrated circuit having a power-on sequence in which a first power source, a second power source, and a third power source are sequentially turned on. A set signal generation means for generating a set signal by detecting a time from turning on the first power supply to turning on the third power supply; and a flip-flop circuit that is set by the set signal and outputs a reset signal for an internal circuit; , Generating a signal obtained by delaying the signal generated by detecting the second power-on until after the third power-on is completed, and resetting the flip-flop after the third power-on is completed There is provided a power-on reset circuit comprising a reset signal generating means for outputting a reset signal for a flip-flop that is kept in a state.

  According to the present invention, it is possible to prevent malfunction of the semiconductor integrated circuit when noise is applied to the power supply line.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a power-on reset circuit according to an embodiment of the present invention.

  The power-on reset circuit 1 of this embodiment is provided in a semiconductor integrated circuit in which a scanning line driving circuit of an LCD panel is integrated. A semiconductor integrated circuit in which the scanning line driving circuit is integrated receives a positive voltage power supply VDD and a ground potential power supply GND as logic circuit power supplies, and a positive voltage power supply VGG and a negative voltage power supply VEE as LCD panel power supplies. Shall. When power is supplied to the semiconductor integrated circuit, the logic positive voltage power supply VDD is first input, the LCD panel negative voltage power supply VEE is input second, and the LCD panel is third. Assume that the positive voltage power supply VGG is turned on.

  The power-on reset circuit 1 of the present embodiment detects the time from the rise of the first positive voltage power supply VDD for logic to the rise of the third positive voltage power supply VGG for the LCD panel. A set signal generation unit 11 for generating S, a flip-flop circuit 12 that is set by the set signal S and outputs an internal circuit reset signal, and a negative voltage power supply VEE for the LCD panel that is input secondly. A flip-flop that delays the signal generated by the detection until the completion of the application of the positive voltage power supply VGG for the LCD panel and leaves the flip-flop circuit 12 after the completion of the application of the positive voltage power supply VGG for the LCD panel And a reset signal generation unit 13 that outputs the reset signal R for use.

  The set signal generation unit 11 includes a PMOS transistor P1 and an NMOS transistor N1 that are connected in series between the logic positive voltage power supply VDD and the ground potential power supply GND to form an inverter IV1. The LCD panel positive voltage power supply VGG is connected to the input of the inverter IV1, that is, to the respective gate electrodes of the PMOS transistor P1 and the NMOS transistor N1.

  Therefore, the set signal S output from the set signal generator 11 is “1” from the rise of the logic positive voltage power supply VDD until the potential of the LCD panel positive voltage power supply VGG exceeds the threshold value of the inverter IV1. After the potential of the LCD panel positive voltage power supply VGG exceeds the threshold value of the inverter IV1, it becomes “0”.

  The flip-flop circuit 12 is a set-reset type flip-flop in which two-input NOR gates NR1 and NR2 are connected to each other, and outputs an internal circuit reset signal from the output of the NOR gate NR2.

  This flip-flop outputs “1” as the internal circuit reset signal when “1” is input to the set signal S when the reset signal R is “0”, and the reset signal R is “1”. Is input as a reset signal for the internal circuit regardless of the value of the set signal S. That is, the flip-flop circuit 12 is a reset priority flip-flop. When both the set signal S and the reset signal R are “0”, the previous state is held.

  The reset signal generation unit 13 includes a resistor R1 and a capacitor C1 connected in series between the logic positive voltage power supply VDD and the LCD panel negative voltage power supply VEE. In this example, a reset signal R for the flip-flop circuit 12 is output from a connection point between the resistor R1 and the capacitor C1.

  The reset signal R rises as the potential rises when the logic positive voltage power supply VDD is turned on, but when the LCD panel negative voltage power supply VEE is turned on, the potential becomes VDD- | VEE |. Suddenly decreases. Thereafter, the potential rises to the logic positive voltage power supply VDD according to the time constant formed by the resistor R1 and the capacitor C1.

  Accordingly, the reset signal R is “0” during a period in which the potential is equal to or lower than the threshold value of the NOR gate NR2, and becomes “1” when the potential exceeds the threshold value of the NOR gate NR2. The period during which the reset signal R is “0” can be arbitrarily set by adjusting the time constant formed by the resistor R1 and the capacitor C1.

  Note that the circuit configuration of the reset signal generation unit 13 is not limited to the circuit illustrated in FIG. 1, and may be other configurations.

  FIG. 2 shows an example of a circuit having another configuration of the reset signal generation unit 13.

  FIG. 2A shows a circuit in which a resistor is a PMOS transistor P2. By connecting the gate of the PMOS transistor P2 to the LCD panel negative voltage power supply VEE, the PMOS transistor P2 operates with a constant on-resistance.

  In FIG. 2B, a Schmitt trigger circuit ST1 is connected to a connection point between the resistor R1 and the capacitor C1, and the output of the Schmitt trigger circuit ST1 is used as a reset signal R.

  When the time constant formed by the resistor R1 and the capacitor C1 is set large, the slope of the potential change at the connection point becomes gradual and is easily affected by external noise. Therefore, a Schmitt trigger circuit ST1 is inserted to eliminate noise.

  FIG. 2C shows the connection of the resistor R1 and the capacitor C1 reversed from that in FIG. In this case, the inverter IV2 is connected to the connection point between the resistor R1 and the capacitor C1, the level is inverted, and the reset signal R is output.

  Next, the operation of the power-on reset circuit 1 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 3 is a waveform diagram showing the operation of the power-on reset circuit 1 immediately after the power is turned on.

  First, when the logic positive voltage power supply VDD is first turned on and its potential rises, both the set signal S output from the set signal generator 11 and the reset signal R output from the reset signal generator 13 are both The flip-flop circuit 12 is reset to “1”, and the internal circuit reset signal of the output is set to “0”.

  Second, when the LCD panel negative voltage power supply VEE is turned on, the reset signal R becomes '0'. That is, since the set signal S input to the flip-flop circuit 12 is “1” and the reset signal R is “0”, the flip-flop circuit 12 is set, and the output reset signal for the internal circuit is “1”. It becomes.

  Third, when the LCD panel positive voltage power supply VGG is turned on, the set signal S changes to '0'. At this time, the time constants of the resistor R1 and the capacitor C1 of the reset signal generation unit 13 are adjusted so that the end of the rising edge of the reset signal R is after completion of the application of the positive voltage power supply VGG for the LCD panel. Set the delay time. Thereby, even after the set signal S changes to '0', the reset signal R can be kept at '0' for a certain time.

  During this time, both the set signal S and the reset signal R input to the flip-flop circuit 12 are “0”, so that the flip-flop circuit 12 maintains the set state, and the output internal circuit reset signal is “1”. 'Continue. As a result, an internal circuit reset signal having a time width sufficient to reset the internal circuit can be obtained.

  Thereafter, when the reset signal R changes to ‘1’, the flip-flop circuit 12 enters a reset state, and the internal circuit reset signal changes to ‘0’. Since the reset signal R subsequently holds “1”, the reset priority flip-flop circuit 12 holds the reset state regardless of the value of the set signal S, and the internal circuit reset signal is “0”. Remains.

  FIG. 4 is a waveform diagram showing how the power-on reset circuit 1 operates when power supply noise is applied to the LCD panel positive voltage power supply VGG after the power is turned on.

  When a large noise is applied to the LCD panel positive voltage power supply VGG so that the inverter IV1 of the set signal generation unit 11 is inverted, the set signal S output from the set signal generation unit 11 has a pulsed '1'. Appears.

  However, at this time, the reset priority flip-flop circuit 12 is in a reset state because “1” is input to the reset signal R, and even if “1” is input to the set signal S, it is not affected. The internal circuit reset signal, which is the output of the flip-flop circuit 12, remains “0”.

  That is, even when a large power supply noise is applied to the positive voltage power supply VGG for the LCD panel, the influence does not appear in the reset signal for the internal circuit, and the semiconductor integrated circuit in which the scanning line driving circuit of the LCD panel is integrated does not cause a malfunction. Absent.

  According to this embodiment, the internal circuit reset signal is not erroneously generated even when noise is applied to the power supply line, so that the semiconductor integrated circuit can be prevented from malfunctioning.

The block diagram which shows the example of a structure of the power-on reset circuit which concerns on the Example of this invention. The circuit diagram which shows another example of a structure of the reset signal generation part of the power-on reset circuit which concerns on the Example of this invention. The wave form diagram which shows the example of the operation timing of the power-on reset circuit which concerns on the Example of this invention. The wave form diagram which shows the example of operation | movement at the time of the power supply noise application of the power on reset circuit which concerns on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power-on reset circuit 11 Set signal generation part 12 Flip-flop circuit 13 Reset signal generation part P1, P2 PMOS transistor N1 NMOS transistor IV1, IV2 Inverter NR1, NR2 NOR gate R1 Resistor C1 Capacitor ST1 Schmitt trigger circuit VDD Positive voltage power supply for logic GND Ground potential VGG Positive voltage power supply for LCD panel VEE Negative voltage power supply for LCD panel

Claims (5)

A power-on reset circuit mounted on a semiconductor integrated circuit having a power-on sequence in which a first power source, a second power source, and a third power source are sequentially turned on,
A set signal generating means for detecting a time from turning on the first power to turning on the third power and generating a set signal;
A flip-flop circuit that is set by the set signal and outputs an internal circuit reset signal;
A signal generated by detecting that the second power is turned on is delayed until after the third power is turned on, and the flip-flop after the third power is turned on is reset. A power-on reset circuit comprising: a reset signal generating unit that outputs the reset signal as a flip-flop reset signal. The set signal generation means includes
2. The power-on reset circuit according to claim 1, further comprising an inverter driven by the first power supply and a ground potential power supply, wherein the third power supply is connected to an input of the inverter. The reset signal generating means includes
The power-on reset circuit according to claim 1, further comprising a resistor and a capacitor connected in series between the first power source and the second power source. The time constant formed by the resistor and the capacitor is
4. The power-on reset circuit according to claim 3, wherein the power-on reset circuit is determined in accordance with a time from when the second power is turned on to when the third power is turned on. The flip-flop circuit is
5. The power-on reset circuit according to claim 1, wherein the power-on reset circuit is a reset-priority set-reset type.

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