JP3474148B2 - Power-on reset circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit which is provided in a semiconductor integrated circuit, detects a power-on and supplies a reset pulse to each part of the semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional power-on reset circuit. This power-on reset circuit has a resistor 1 connected to one end of a power supply line, a capacitor 2 connected between the other end of the resistor 1 and the ground, and a connection node N1 of the resistor 1 and the capacitor 2. It is composed of the input terminal and the connected inverter 3. Figure 3
FIG. 3 is a diagram showing operation waveforms in FIG. 2. In the power-on reset circuit of FIG. 2, when the power is turned on and the power supply voltage Vdd is applied, the resistor 1 causes a current to flow to charge the capacitor 2. As a result of this charging, the voltage of the node N1 rises with a delay from the rise of the voltage Vdd by the time constant determined by the resistor 1 and the capacitor 2. In addition, the inverter 3
Also operates by being driven by the power supply voltage Vdd, so that the threshold value Vti of the inverter 3 also increases in proportion to the voltage Vdd. Immediately after the power is turned on, the inverter 3 outputs the "H" level signal proportional to the voltage Vdd because the voltage of the node N1 is lower than the threshold Vti (see the lower graph in FIG. 3). When the voltage Vdd rises with the passage of time, the voltage of the node N1 rises. Node N at time T1
When the voltage of 1 exceeds the threshold value Vti of the inverter 3, the inverter 3 is inverted and outputs the "L" level signal. By the above operation, the reset pulse signal P is output as the output signal of the inverter 3, and the reset pulse signal P is given to each part of the semiconductor integrated circuit.

FIG. 4 is a circuit diagram of another conventional power-on reset circuit. This power-on reset circuit has a resistor 4 having one end connected to the power supply line, a gate connected to the power supply line, and a drain connected to the resistance 4
Of the N-channel type M0S transistor (hereinafter referred to as NM0S) 5 which is connected to the other end of the N-channel type and the source or the ground, and the input terminal is connected to the node N2 which is a connection point of the drain of the NM0S5 and the resistor 4. The inverter 6 and the inverter 7 having an input terminal connected to the output terminal of the inverter 6 are arranged. FIG. 5 is a diagram showing operation waveforms in FIG. In the power-on reset circuit of FIG. 4, NM0S5 is in the off state before the power is turned on. When the power is turned on and the power supply voltage Vdd is applied, the node N2 becomes the power supply voltage Vdd level. Immediately after the power is turned on, the power supply voltage Vdd level of the node N2 changes to the inverter 6
, The inverter 6 outputs an "L" level signal (see the graph in the middle of FIG. 5), and the inverter 7 connected to it outputs the power supply voltage Vd.
The "H" level signal proportional to the rise of d is output (Fig. 5).
See chart below). Power supply voltage Vdd at time T2
Exceeds the threshold Vtn of NM0S5, this NM0S5
Turns on to connect the node N2 to the ground. Therefore, the voltage of the node N2 drops. At time T1, when the voltage of the node N2 drops below the threshold value Vti of the inverter 6, this inverter 6 outputs an "H" level signal which is an inverted signal. The inverter 7 receives the "H" level signal from the inverter 6, inverts this signal and outputs the "L" level signal. The "L" level signal output from the inverter 7 becomes the reset pulse P, which is supplied to each part of the semiconductor integrated circuit.

[0004]

However, the power-on reset circuit shown in FIGS. 2 and 4 has the following problems. In the power-on reset circuit of FIG. 2, the voltage V
If the rise of dd is gentle or fluctuates, the voltage of the node N1 also fluctuates. If such a voltage variation of the node N1 occurs near the threshold value Vti of the inverter 3, the inverting operation of the inverter 3 is repeated, and a plurality of reset pulses P are output. Moreover, in the power-on reset circuit of FIG. 3, when the voltage Vdd rises sharply, the gate voltage of NM0S5 also rises sharply and turns on. Therefore, the inverter 6 connected to the node N2 outputs the "H" level signal from the beginning, and the inverter 7 continues to output the "L" level signal. Therefore, there is a problem that the reset pulse P is not formed.

[0005]

In a power-on reset circuit according to the present invention, a power supply line to which a first power supply potential is applied, a first node, and a line between the first node and the power supply line. Connected to the resistor element, a second node, a reference node to which a second power supply potential is applied, a gate connected to the power supply line, a drain connected to the second node, and a source connected to the reference node. A first transistor connected to the power supply line, a drain connected to the first node, and a source connected to the second node; A capacitor connected to the node and a first inverter having an input connected to the first node were provided. By adopting such a configuration, even when the change in the power supply voltage is steep, the capacitor delays the flow of current to, for example, the first transistor and the resistor in the ON state. Therefore, it is delayed with respect to the change in the output voltage of the resistor or the change in the power supply voltage. The output voltage of this resistor is given to the inverter and is output as a reset pulse signal or an inverter.

[0006]

1 is a circuit diagram of a power-on reset circuit showing a first embodiment of the present invention. This power-on reset circuit 100 is provided with a power line 1 to a power line 1.
The power supply voltage Vdd is applied via 0, and the first transistor NM0S11, the second transistor NM0S12, and these NMOS1 are provided.
1 and 12 and a resistor 13 connected in series. NM0
The gate of S11 and NM0S12 is common to the power supply line 1
The back gates which are connected to 0 and are the substrate potentials of these NM0S11 and 12 are commonly connected to the ground.
The source of NM0S11 is connected to the ground, and the drain thereof is connected to the source of NM0S12. NM0
The drain of S12 is connected to one end of the resistor 13, and the other end of the resistor 13 is connected to the power supply line 10. NM
The input terminal of the first inverter 14 is connected to the connection node N3 to which the drain of 0S12 and one end of the resistor 13 are connected. The input terminal of the second inverter 15 is connected to the output terminal of the inverter 14. NM0S
One electrode of a capacitor 16 of, for example, about 2 to 3 pF is connected to a connection node N4 between the drain of 11 and the source of NM0S12. The other electrode of the capacitor 16 is connected to the power supply line 10.

FIG. 6A is a diagram showing operation waveforms of the power-on reset circuit 100 shown in FIG. 1 when the power supply potential Vdd rises sharply. The power-on reset circuit 10 shown in FIG. 1 will be described below with reference to FIG. 6A.
An operation when the power supply potential Vdd of 0 rises sharply will be described. In the state before the power source voltage Vdd is applied from the power source (the state of the origin in the graph), 2
The two NM0S11 and 12 are in the off state. As shown in the upper graph of FIG. 6A, when the power is turned on, the power line 10
When the power supply voltage Vdd is applied via the, the voltage applied to the gates of the NM0Ss 11 and 12 rises as the power supply voltage Vdd rises, and the threshold Vti of the inverters 14 and 15 increases.
Also rises in proportion. The voltage of the node N3 is also the power supply voltage V
It rises with the rise of dd. The voltage of the node N4 also rises by the capacitor 16 as the power supply voltage Vdd rises. As shown in the middle graph of FIG. 6A, immediately after the power is turned on, the inverter 14 outputs the “L” level signal, and the inverter 15 rises with the voltage Vdd as shown in the lower graph of FIG. 6A. "Output level signal.

When the voltage Vdd applied to the gates of NM0S11, 12 exceeds the threshold value Vtn of NM0S11, 12 at time T4, these NM0S11, 12 are turned on. When these NM0S11, 12 are turned on, NM0S11 first causes a charging current to flow from the capacitor 16 and drops the voltage of the node N4. Then, NM0S
A current flows through 12 or the resistor 13 and the node N3. That is, the capacitor 16 delays the flow of current through the resistor 13. The resistor 13 in which the current has started to flow gives the dropped voltage to the node N3. Therefore, the voltage of the node N3 drops a little after the power supply voltage Vdd exceeds the threshold value Vtn. At time T5, node N3
When the voltage of V reaches the threshold value Vti of the inverter 14, the inverter 14 outputs an inverted "H" level signal.
Therefore, the inverter 15 outputs an "L" level signal. In this way, the inverter 15 outputs the "L" level signal, whereby the output signal of the inverter 15 forms the reset pulse P of several ns. The signal having the reset pulse P is given to each part of the semiconductor integrated circuit.

FIG. 6B is a diagram showing operation waveforms of the power-on reset circuit 100 shown in FIG. 1 when the power supply potential Vdd rises gently. Below this FIG. 6B
Referring to FIG. 1, the power-on reset circuit 1 shown in FIG.
The operation when the power supply potential Vdd of 00 rises gently will be described. After the power supply potential Vdd is turned on, the potentials of the node N3 and the node N4 gradually rise as shown in the upper graph of FIG. 6B. Time T6
The power supply voltage Vdd is the threshold value V of NM0S11, 12
When tn is reached, the NMOSs 11 and 12 are turned on, and the charging current starts to flow from the capacitor 16 through NM0S11. As a result, the potential of the node N4 begins to drop, but the potential of the node N3 remains unchanged as the power supply potential Vd.
It keeps rising with d. When the charging current from the capacitor decreases, the current of the transistor 12 starts to flow, and the voltage of the node N3 also starts to drop. As shown in the upper graph of FIG. 6B, when the voltage of the node N3 reaches the threshold value Vti of the inverter 14 at time T7, the inverter 14 inverts the signal that has been output so far, and the power supply voltage Vdd level becomes “H”. Output level signal (Fig. 6B)
See the graph in the middle). Therefore, as shown in the lower graph of FIG. 6B, the implanter 15 outputs the “L” level signal. Since the inverter 15 outputs the “L” level signal, the output signal of the inverter 15 is
A reset pulse P is formed. This reset pulse P
A reset signal having is given to each part of the semiconductor integrated circuit.

As described above, in the first embodiment,
NM0S11 and NM0S11 and 12 are connected in series between the resistor 13 and the ground, and the capacitor 16 is connected to the connection point of NM0S11 and NM0S12. Therefore, the power supply voltage V
It is possible to delay the change in the voltage of the node N3 after dd reaches the threshold value Vtn of NM0S11 and 12, and the reset pulse P can be reliably formed even when the power supply voltage Vdd rises or is abrupt. Further, even if the power supply voltage Vdd rises gently, if the NM0S 11 and 12 are turned on, the voltage of the node N3 drops sufficiently, so that there is no problem that the inverters 14 and 15 repeat inversion. Further, since NM0S12 and the power supply line 10 are connected by the resistor 13, the voltage setting of the node N3 is NM0.
It is sufficient to manage only the threshold value Vtn of S11 and S12. Therefore, for example, as compared with the case where the P-channel type M0S (hereinafter referred to as PM0S) is used instead of the resistor 13,
Design becomes easier and manufacturing control becomes easier. Moreover, since the capacitor 16 is the only element that delays the inversion operation in the inverter 14 and the inverter 15, a delay circuit used for this purpose is provided before the first gates of NM0S11, 12 to delay the power supply voltage Vdd. However, design and manufacturing control are much easier.

FIG. 7 is a circuit diagram of a power-on reset circuit showing a second embodiment of the present invention. This power-on reset circuit 200 is the same as the delay circuit 20 of the first embodiment.
Is provided. Therefore, except for the delay circuit 20, the power-on reset circuit 200 is an NMO that is the same component as that shown in the first embodiment with the same reference numerals.
It is composed of S31, 32, a resistor 33, inverters 34, 35 and a capacitor 36. The delay circuit 20 is
A resistor 21 having a resistance value of 1 KΩ and a capacitor 22, for example, are connected in series between the power supply line 10 and the ground. The gate of NM0S31 is connected to the power supply line 10, and the gate of NM0S32 is connected to the connection node N5 of the resistor 21 and the capacitor 22. The back gates of NM0S31 and 32 are commonly connected to the ground. The source of NM0S31 is connected to the ground, and the drain thereof is connected to the source of NM0S32. The drain of NM0S32 has a resistance of 3
3 is connected to one end of the resistor 33, and the other end of the resistor 33 is connected to the power supply line 10. The resistance value of the resistor 33 is, for example, 4 MΩ. The input terminal of the inverter 34 is connected to the connection node N6 of the drain of the NM0S32 and the resistor 33. The input terminal of the inverter 35 is connected to the output terminal of the inverter 34. One electrode of the capacitor 36 is connected to a connection node N7 between the drain of NM0S31 and the source of NM0S32. The other electrode of the capacitor 36 is connected to the power supply line 10.

FIG. 8A is a diagram showing operation waveforms of the power-on reset circuit 200 shown in FIG. 7 when the power supply potential Vdd rises sharply. The power-on reset circuit 20 shown in FIG. 7 will be described below with reference to FIG. 8A.
An operation when the power supply potential Vdd of 0 rises sharply will be described. When the power supply voltage Vdd is not applied from the power supply (the origin of the graph), two NM
0S31 and 32 are in the off state. When the power supply voltage Vdd is applied through the power supply line 10 when the power is turned on,
As the power supply voltage Vdd rises, the voltage applied to the gate of NM0S31 rises. The delay circuit 20 has a power supply voltage V
Since dd is delayed and given to the gate of NM0S32, the voltage applied to the gate of NM0S32 is NM0S31.
Rise late. On the other hand, as shown in the upper graph of FIG. 8A, the threshold Vti of the inverters 14 and 15 also increases in proportion to the rising gate of the power supply voltage Vdd. Further, as shown in the upper graph of FIG. 8A, the voltage of the node N6 also rises as the power supply voltage Vdd rises, and the voltage of the node N7 also rises as the power supply voltage Vdd rises due to the capacitor 36. . Immediately after the power is turned on, the inverter 34
Outputs an "L" level signal, the inverter 35 outputs an "H" level signal that rises with the voltage Vdd.

At time T8, when the voltage Vdd applied to the gate of NM0S31 exceeds the threshold value Vtn of NM0S31, NM0S31 is turned on. Then, after the delay time determined by the delay circuit 20, the NMOS 32
Turns on. As shown in FIG. 8A, when the rise of the power supply voltage Vdd is steep, when NM0S31 is turned on at time T8, NM0S31 first starts flowing the charging current of the capacitor 36, and drops the voltage of the node N7. After the delay time determined by the delay circuit 20 from the power-on, NM
The OS 32 turns on, and the NM0S 32 causes a current to flow through the resistor 33. Even if NM0S32 is turned on, the capacitor 36 still functions, so that the current flowing through NM0S32 starts to flow with a delay. A voltage drop starts at the node N6 due to the resistor 13 in which the current starts flowing. Therefore, node N
Similar to the first embodiment, the voltage of 6 drops with time after the voltage of the power supply Vdd exceeds the threshold value Vtn. At time T9, when the voltage of the node N6 becomes equal to or lower than the threshold value Vti of the inverter 34, the inverter 34 outputs an "H" level signal which is an inverted signal. Inverter 3
Reference numeral 5 further inverts this output signal and outputs an "L" level signal. When the inverter 35 outputs the "L" level signal, a reset pulse P of several ns is formed in the output signal of the inverter 35. A signal having this reset pulse P is given to each part of the semiconductor integrated circuit.

FIG. 8B is a diagram showing operation waveforms of the power-on reset circuit 200 shown in FIG. 7 when the power supply potential Vdd rises gently. Below this FIG. 8B
Referring to FIG. 7, the power-on reset circuit 2 shown in FIG.
The operation when the power supply potential Vdd of 00 rises gently will be described. After the power supply potential Vdd is turned on, the potentials of the nodes N6 and N7 gradually rise as shown in the upper graph of FIG. 8B. Time T8
At the power supply potential Vdd of the NMOS transistor NM0
When the threshold value Vtn of S31 is exceeded, the NMOS 31 is turned on. As a result, the NM0S31 starts to flow the charging current of the capacitor 36 and drops the voltage of the node N7. After the delay time determined by the time constant determined by the resistor 21 and the capacitor 22 of the delay circuit 20 after the power is turned on, the NMOS
32 is turned on, and NM0S32 causes a current to flow through the resistor 33. By the discharge current from the capacitor 36,
NM0S32 starts to flow current after a short delay after turning on, and the voltage drop of the node N6 starts. That is, the node N6
The voltage of 1 drops after a lapse of time after the voltage of the power supply Vdd exceeds the threshold value Vtn. At time T9, when the voltage of the node N6 becomes equal to or lower than the threshold value Vti of the inverter 34, the inverter 34 outputs an "H" level signal which is an inverted signal. The inverter 35 further inverts this output signal and outputs an "L" level signal. Inverter 35
By outputting a "L" level signal, a reset pulse P of several ns is formed in the output signal of the inverter 35. A signal having this reset pulse P is given to each part of the semiconductor integrated circuit. Here, since the resistance value of the resistor 33 is larger than that of the resistor 21, the drain current of the NM0S32 is limited, and the delay circuit 20 delays the change of the power supply voltage Vdd and applies it to the gate of the NM0S32.
The reaction of NM0S32 becomes slow. Therefore, the voltage of the node N6, which is the input voltage of the inverter 34, is unlikely to become the "H" level once it becomes the "L" level. Therefore, the voltage of the node N6 makes a clean transition from the “L” level to the “H” level without causing rebound.

As described above, in the second embodiment,
Since the delay circuit 20 is provided and the changing power supply voltage Vdd is delayed and given to the gate of the NM0S32 to make the reaction of the NM0S32 gradual, the power supply voltage Vdd is less likely to change than in the first embodiment. It is possible to realize a power-on reset circuit having resistance to it.

FIG. 9 is a circuit diagram of a power-on reset circuit showing a third embodiment of the present invention. In this power-on reset circuit 300, the gate of the transistor 31 in the second embodiment is connected to the output of the delay circuit 20. Therefore, the power-on reset circuit 300
Are almost the same as those shown in the second embodiment, the reference numerals of the respective constituent elements are the same as those in the second embodiment. The specific circuit configuration is the same as that of the second embodiment, and therefore its explanation is omitted. Also, the third
Regarding the operation of the power-on reset circuit 300 according to the second embodiment, except that the NMOS 31 and the NMOS 32 are simultaneously turned on, the power-on reset circuit 2 according to the second embodiment is operated.
Since the operation is the same as that of No. 00, the description thereof will be omitted.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, there are the following modifications. (1) In the first and second embodiments, the cavitator 16,
Whether one electrode of 36 is connected to the power supply line 10,
May be connected to ground. By doing this, NM0
As the current flowing through S11 and S31 is delayed, the first
In addition, the same effect as the second embodiment is obtained. (2) The power supply voltage Vdd delayed by the delay circuit 20 as in the second embodiment is not the gate of the NM0S32 but the
It may be applied to the gate of NM0S31. (3) In the first and second embodiments, it is assumed that the power supply voltage Vdd is higher than the ground, NM0S11, 12,
Although 31 and 32 are used, if the power supply voltage Vdd is lower than the ground, these NM0S11, 12, 3
The P-channel M0S transistors may be substituted for 1 and 32.

[0018]

As described above in detail, according to the present invention, the first and second transistors, the resistor and the capacitive element are provided in the power-on reset circuit, and the current flowing through the resistor is formed by the capacitive element. Since the delay is applied, the output voltage of the resistor corresponding to the change in the power supply voltage is also delayed, and the reset pulse can be reliably formed even when the change in the power supply voltage is steep. Further, a delay circuit for delaying the power supply voltage is provided, and the delayed power supply voltage output from the delay circuit is also applied to the gate of the first transistor or the gate of the second transistor. The reaction of the second transistor becomes slow, the output voltage of the resistor does not fluctuate, and even if the change in the power supply voltage is slow, the reset pulse can be stably formed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a power-on reset circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional power-on reset circuit.

FIG. 3 is a diagram showing operation waveforms in FIG.

FIG. 4 is a circuit diagram showing another conventional power-on reset circuit.

5 is a diagram showing operation waveforms in FIG. 4;

6 is a diagram showing operation waveforms in FIG. 1 when the power supply potential Vdd rises sharply (A) and when it rises gently (B).

FIG. 7 is a circuit diagram of a power-on reset circuit showing a second embodiment of the present invention.

8 is a diagram showing operation waveforms in FIG. 7 when the power supply potential Vdd rises sharply (A) and when it rises gently (B).

FIG. 9 is a circuit diagram of a power-on reset circuit showing a third embodiment of the present invention.

[Explanation of symbols]

10 power lines 11, 12, 31, 32 NM0S 13,33 resistance 14, 15, 34, 35 inverters 16,36 Kyapashita 20 delay circuit N3-N7 connection nodes Vdd power supply voltage

Continuation of front page (56) Reference JP 58-80928 (JP, A) JP 9-270686 (JP, A) JP 10-65505 (JP, A) JP 10-145209 (JP , A) JP-A-11-68539 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 17/22

Claims (21)

(57) [Claims] 1. A power supply line to which a first power supply potential is applied, a first node, a resistance element connected between the first node and the power supply line, and a second node, A reference node to which a second power supply potential is applied; a gate connected to the power supply line; a drain connected to the second node; a source connected to the reference node; A second transistor connected to a power supply line, a drain connected to the first node, a source connected to the second node, and a capacitor having one terminal connected to the second node , A first inverter having an input connected to the first node. 2. The power-on reset circuit according to claim 1, wherein back gates of the first and second transistors are connected to the reference node. 3. A second inverter having an input connected to the output of the first inverter, the first and second inverters
The power-on reset circuit according to claim 1, wherein the inverter is driven by the first power supply potential. 4. The power-on reset circuit according to claim 1, wherein the other terminal of the capacitor is connected to the power supply line. 5. The power-on reset circuit according to claim 1, wherein the other terminal of the capacitor is connected to the reference node. 6. The first power supply potential has a higher potential than the second power supply potential, and the first and second transistors are NM.
The power-on reset circuit according to claim 1, which is an OS transistor. 7. The second power supply potential has a higher potential than the first power supply potential, and the first and second transistors are PM.
The power-on reset circuit according to claim 1, which is an OS transistor. 8. A power supply line to which a first power supply potential is applied, a first node, a resistance element connected between the first node and the power supply line, and a second node, A reference node to which a second power supply potential is applied; a gate connected to the power supply line; a drain connected to the second node; a source connected to the reference node; A delay circuit connected to the power supply line; a second transistor having a gate connected to the output of the delay circuit, a drain connected to the first node, and a source connected to the second node; A power-on reset circuit having a first inverter whose input is connected to the first node. 9. The power-on reset circuit according to claim 8, wherein back gates of the first and second transistors are connected to the reference node. 10. The power of claim 8, further comprising a second inverter having an input connected to the output of the first inverter, the first and second inverters being driven by the first power supply potential. On-reset circuit. 11. The power-on reset circuit according to claim 8, further comprising a capacitor connected between the power supply line and the second node. 12. The power-on reset circuit according to claim 8, further comprising a capacitor connected between the reference node and the second node. 13. The first power supply potential has a higher potential than the second power supply potential, and the first and second transistors are
The power-on reset circuit according to claim 8, which is an NMOS transistor. 14. The delay circuit is connected between a second resistance element connected between the power supply line and the gate of the second transistor, and between the reference node and the gate of the second transistor. 9. The power-on reset circuit according to claim 8, further comprising a capacitor. 15. A power supply line to which a first power supply potential is applied, a first node, a resistance element connected between the first node and the power supply line, and a second node, A reference node to which a second power supply potential is applied; a delay circuit having an input connected to the power supply line; a gate connected to the output of the delay circuit; a drain connected to the second node; A first transistor connected to a reference node, a second transistor having a gate connected to the output of the delay circuit, a drain connected to the first node, and a source connected to the second node , A first inverter having an input connected to the first node. 16. The power-on reset circuit according to claim 15, wherein back gates of the first and second transistors are connected to the reference node. 17. The power-on reset circuit according to claim 15, further comprising a capacitor connected between the power supply line and the second node. 18. The power-on reset circuit according to claim 15, further comprising a capacitor connected between the reference node and the second node. 19. The power of claim 15, further comprising a second inverter having an input connected to the output of the first inverter, the first and second inverters being driven by the first power supply potential. On-reset circuit. 20. The first power supply potential has a higher potential than the second power supply potential, and the first and second transistors are
The power-on reset circuit according to claim 15, which is an NMOS transistor. 21. The delay circuit is connected between a second resistance element connected between the power supply line and the gate of the second transistor, and between the reference node and the gate of the second transistor. The power-on reset circuit according to claim 15, further comprising a capacitor.