JPS61222318A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To generate a reset signal even when the leading of a power supply is slow by connecting an element which is turned on and then causes a prescribed voltage drop with a power supply rising to a voltage and a capacitor generating a reset signal in series between power supplies. CONSTITUTION:A MOS transistor (TR) Q5 turned on when the power supply rises to a voltage and causing a prescribed voltage drop further, a resistor R and a capacitor C are connected in series between power supplies. When a power supply voltage Vcc reaches the threshold value Vth of the TR Q5 at application of power, the TR Q5 is turned on and the capacitor C is charged through the resistor R. When a voltage VA exceeds the threshold voltage of an inverter I1, a TR Q1 is turned off, a TR Q2 is turned on and a voltage VB goes to an L level, then a TR Q3 is turned on, a TR Q4 is turned off and a voltage Vc at an output terminal C goes to an H level in an inverter I2, but the voltage Vc is at L level until that time and the voltage Vc being at an L level becomes a reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit that generates a reset signal for setting an internal logic circuit to an initial state when power is turned on in an integrated circuit without a reset terminal.

[Conventional technology]

Generally, flip-flops and the like included in a logic circuit are reset before the power is turned on and the logic circuit starts operating, and the operation is started from the reset state. If the logic circuit is configured as an integrated circuit (IC), applying the reset signal externally would increase the number of terminal pins by one, which is not a good idea. This is the power-on reset circuit.

There are several types of reset circuits of this kind, and FIG. 4 shows one example. This is made up of a series connection circuit of a resistor R and a capacitor C connected to the power supply Vcc, and the series connection point A
output a reset signal.

That is, when the IC power is turned on, Vcc generally rises rapidly from Ov to, for example, 5V, but the A point voltage, that is, the capacitor voltage vA, gradually rises with the RC time constant and lags behind Vcc. To explain with Figure 5, the power supply Vcc rises rapidly as shown in (a), whereas the capacitor voltage vA rises rapidly.)
As shown in FIG.
(high) level (circuit is operational) and low (low)
level, and flip-flops etc. are reset by this L level voltage vA (L level reset type)
. The voltage vA eventually rises to Vcc (5V) and no longer has a reset function, so after vA reaches the H level, the logic circuit can operate from the state in which the flip-flops and the like have been reset.

[Problem that the invention seeks to solve]

However, the conventional circuit shown in FIG. 4 has the following drawbacks. ! II. If the power supply circuit has a large time constant and rises slowly as shown in Figure 5 (C), the rise of the capacitor voltage vA will be similar to Vcc, and Vcc will become H level (the logic circuit will not operate). When this becomes possible, the VA:bH level (level without a reset function) is reached, and no reset signal is generated.

Also, as shown in Figure 6, some IC power supplies start out at a low voltage, say 2V, and then change to a high voltage, say 6V.
In such a device, the circuit of FIG. 4 generates a reset signal every time the power supply voltage increases. However, the reset is performed only when the power is turned on t1, that is, when the operation starts, and the reset is not normally performed even if the power supply voltage changes during operation (it does not return to the initial state), so the later reset (during the period t2) is inconvenient. It is. In other words, in the circuit shown in Figure 4, the usable range of power supply voltage is narrow.Since telephone ICs derive their power from the telephone line, there can be large voltage fluctuations, but it is necessary to avoid resets due to these voltage fluctuations. .

Recess 7) that occurs when the power supply voltage increases can be avoided by using an inverter as shown in FIG.

In this figure, Ql and Q2 are transistors that constitute a CMOS inverter. If the threshold value of this inverter is selected as 1■, it will be determined as L until the output voltage vA of the RC circuit reaches 1V, and the inverter output voltage Va will be H (= V cc
), IV or more, it is determined to be H and Va becomes L (-' ground level).

When the power supply Vcc changes from 2v to 6v, VA is still determined to be H, and VB-L remains unchanged.

That is, no reset signal is generated during period t2.

A third drawback of the circuit of FIG. 4 is that it does not generate a reset signal when the power supply is momentarily cut off. This is because the charge in the capacitor C is not suddenly discharged. Even if the power is momentarily interrupted, that is, the power is turned off temporarily and then turned on again, the output state of flip-flops in logic circuits may have partially changed, so it is necessary to reset them to their initial state and operate from there. It is preferable to resume operation, and it is a problem that a reset signal is not generated at the moment of power interruption. The circuit shown in FIG. 7 also does not output a reset signal when the power supply is momentarily cut off.

The present invention aims to improve these points and provide a power-on reset circuit that generates a reset signal even if the power supply rises slowly. In addition, the present invention also provides:
The present invention aims to provide a power-on reset circuit that does not generate a reset signal when the power supply voltage fluctuates, but generates a reset signal when there is a momentary power interruption.

[Means for solving problems]

The present invention relates to a power-on reset circuit that is mounted in an integrated circuit chip and generates a reset signal when the power of the integrated circuit is turned on. an element that causes a drop;
The device is characterized in that a resistor and a capacitor are connected in series between a power supply, and a reset signal is generated by the voltage of the capacitor.

[Operation and Examples] FIG. 1 shows an example of the present invention. In this figure, R and C are the aforementioned resistors and capacitors, which are connected to the power supply Vcc and output a voltage V^. Ql and Q2, Q3 and Q4 are CMOS
These inverters I1. I2 is connected in two stages in cascade. Qs, Qs is p
In the channel MO3) transistor, C5 works as an element whose drain and gate are short-circuited as shown in the figure to cause a voltage drop of the threshold value vth, and the transistor Q6 is connected to the power supply V.
cc and output terminal A, and its gate is connected to output terminal B of inverter I+. Also, D is a diode,
It is connected between the power supply Vcc and the output terminal A with the illustrated polarity.

In this circuit, when the power is turned on and the Vcc voltage rises, the
When cc exceeds vth of transistor QII, transistor Q5 is turned on and capacitor C is charged through resistor R. Therefore, the voltage vA rises, and when it exceeds the threshold of the inverter 11, Q+ is turned off, Q2 is turned on, and the voltage Va becomes L. Therefore, in inverter ■2, Q3 is turned on, Q4 is turned off, and the voltage Vc at the output terminal C becomes H. This low level Vc becomes the reset signal.

This circuit generates a reset signal even if the power supply Vcc rises slowly. To explain this with reference to FIG.
When turned on, it becomes the above-mentioned vth, and thereafter increases in the same way as Vcc. Capacitor C starts charging after transistor Q5 turns on, and voltage vA gradually rises. While this vA is determined to be L by inverter 1+, the power supply V
Although cc has risen considerably, Vc is at L level,
Vc during this period ta becomes a reset signal.

In addition, the circuit in Figure 1 does not generate a reset signal when the power supply voltage fluctuates. To explain this with Figure 2 (b), when the power supply Vcc changes from Ov to 2V (when the power is turned on), the above-mentioned During the operation, a reset signal is generated during the period taO, but at the end of the period taO, vA is determined to be H by 11 and Q
+off, 02on, and when VB-L, the p-channel transistor Q6 is turned on, and the output terminal A is directly connected to the power supply Vcc.

Therefore, from now on V A = V CC5V B #01Vc
#Vcc, the output states of inverters II and I2 do not change, and no reset signal is generated.

Further, the circuit shown in FIG. 1 generates a reset signal when the power supply is momentarily cut off. To explain this with reference to FIG. 2(C), the power supply Vcc
When the voltage changes from 6V to Ov, the capacitor C charged to 6V discharges to the power supply Vcc via the diode D, which is in the forward direction as seen from the capacitor, and the voltage vA quickly becomes Ov. In this example, the short-time return power supply Vcc has a voltage of 2
When the voltage returns to v, a reset signal is generated in the same manner as described above. Note that the resistor R is not necessarily necessary in the circuit shown in FIG.

Another embodiment of the present invention is shown in FIGS.
(in the figure) is a circuit system in which the resistor R in FIG. 1 is removed.

In other words, the resistor R in Figure 1 is formed by the transistor Q5, and by reducing the β of the transistor Q5, the ON resistance becomes thicker (thus, the ON resistance of the transistor Q5 becomes ON equivalent to the resistor R in Figure 1). If you design a resistor, it will become a power-on reset circuit equivalent to Figure 1.If the power supply voltage range used is not 2v to 6v and the lower limit is a little higher, the power supply voltage should be turned on until the power supply Vcc rises further than above. A reset signal may be generated, and in this case, it is preferable to connect a plurality of transistors Q5 in series.

FIG. 3(a) shows an example circuit in this case, in which two transistors Q5, C7 and Qs, are connected in series. Although the diode D is omitted in this circuit, the diode D
This function is performed by transistor Q6.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a power-on reset circuit having favorable characteristics such as being able to generate a reset signal even if the power supply voltage rises slowly.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a graph for explaining operation, Fig. 3 is a circuit diagram showing another embodiment of the invention, and Fig. 4 is a circuit diagram showing a conventional example. , FIG. 5 and FIG. 6 are explanatory diagrams of its operation, and FIG. 7 is a circuit diagram showing another conventional example. In the drawing, Vcc is a power supply, Qll is a p-channel MO3) transistor with gate and drain shorted, R is a resistor, and C is a capacitor. vcc Vcc Detailed explanation circuit of the present invention Fig. 1-e+ 1-e-'J ty
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Claims (3)

[Claims] (1) Connect an element in series between the power supply and a capacitor that turns on when the power supply rises to a certain voltage value and thereafter causes a constant voltage drop, and use the voltage of the capacitor to generate a reset signal. , a power-on reset circuit characterized in that it generates a reset signal within an integrated circuit chip when the integrated circuit is powered on. (2) A resistor is connected in series between the element that causes the voltage drop and the capacitor, and the reset signal is generated by the voltage of the capacitor. Power-on reset circuit. (3) The power-on reset circuit according to claim 1, wherein the element that causes the voltage drop is a p-channel MOS transistor whose gate and drain are short-circuited.