JP2645117B2 - Reset circuit for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention generates a reset signal for resetting (initializing) an internal circuit of a semiconductor integrated circuit (IC) when power is applied to the IC. Reset circuit.

(Related Art) When a reset circuit is formed inside a CMOS (complementary insulated gate) IC, for example, as shown in FIG. 4, a resistor is provided between a power supply voltage node and a ground potential node inside the IC. R and a capacitor C are connected in series, and a connection point of the resistor R and the capacitor C is connected to one input of a two-input NAND circuit NG,
It can be considered that the other input of the NAND circuit NG is connected to the power supply voltage node. Now, as shown in FIG. 5, when the power supply voltage is applied to the IC at time t1, the output Vb of the NAND circuit NG immediately rises to the power supply voltage level, and the terminal voltage of the capacitor C is equal to the voltage of the resistor R and the capacitor C. It rises slowly according to a constant. When the terminal voltage Va of the capacitor C reaches the "1" level of the NAND circuit input, the output Vb of the NAND circuit NG falls to the ground potential level. Therefore, a reset signal is generated from the NAND circuit NG when power is applied to the IC.

However, the reset circuit in FIG. 4 sets the time width of the reset signal to a certain value or more when the reset signal level is set to a certain value or more in order to surely reset the internal circuit (counter or the like) of the IC. Therefore, the value of the capacitance C must be set to a certain value or more, which is difficult in manufacturing an IC. Also, the threshold voltage of the MOS transistor used in the internal circuit (counter, etc.) of the IC varies depending on the process. However, since this variation is not the same as the above-mentioned variation of the time constant, the reset signal level required for resetting the internal circuit of the IC is different. May not be obtained, and it may not be possible to reliably reset the internal circuit of the IC.

(Problems to be Solved by the Invention) According to the present invention, as described above, the reset circuit using the time constant of the resistance and the capacitance may not be able to reliably reset the internal circuit of the IC when power is applied to the IC. To provide a reset circuit for a semiconductor integrated circuit that can reliably generate the required reset signal when the power is applied to the IC and reliably reset the internal circuit of the IC. The purpose is to do.

[Configuration of the Invention] (Means for Solving the Problems) A reset circuit of a semiconductor integrated circuit according to the present invention comprises a gate-drain interconnect between a high-potential power supply node and a low-potential power supply node inside an IC. Are connected in series and a first resistor is connected in series, and N is connected to a series connection point of the P-channel transistor and the first resistor.
A gate of the channel transistor is connected, a source of the N-channel transistor is connected to the power supply node on the low potential side, and a reset signal output circuit for receiving a drain output of the N-channel transistor and outputting a reset signal is formed. The reset signal output circuit includes a second resistor having one end connected to the drain of the N-channel transistor, a third resistor having one end connected to the power supply node on the low potential side, and a second resistor. Means for flowing a current having a value proportional to the current flowing through the third resistor,
The input terminal includes a CMOS inverter connected to the other end of the third resistor.

(Operation) In the process of raising the power supply voltage when applying power to the IC, the power supply voltage is the sum of the threshold voltage VTHP of the P-channel transistor and the threshold voltage VTHN of the N-channel transistor (VTHP).
Until (+ VTHN), the P-channel transistor and the N-channel transistor are off, and the output of the reset signal output circuit rises as the power supply voltage rises. The power supply voltage further rises and the voltage (VTHP + VTH
When N) is reached, the P-channel transistor and the N-channel transistor are turned on in this order, and the output of the reset signal output circuit is inverted to the ground potential. In this case, even if the threshold voltage of the MOS transistor fluctuates due to process variation and the threshold voltage of the internal circuit of the IC fluctuates, similarly, the MO for detecting the power supply level inside the reset circuit also remains.
Since the threshold voltage of the S transistor also varies, a required reset signal is reliably generated when power is applied to the IC, and the reset signal can reliably reset the internal circuit of the IC.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a reset circuit formed inside a CMOS type IC. This reset circuit is provided between a high potential side power supply node and a low potential side power supply node, in this example, a Vcc power supply voltage node. -Channel transistor P1 having a gate and a drain connected between the gate and a ground potential (GND) node
And the resistor R1 are connected in series, the gate of the N-channel transistor N1 is connected to the connection point of the P-channel transistor P1 and the resistor R1, and the N-channel transistor
The source of N1 is connected to the ground node. A P-channel transistor P2 and a resistor R2 whose gate and drain are connected to each other are connected in series between the Vcc node and the drain of the N-channel transistor N1.
A P-channel transistor P3 is current-mirror-connected to the channel transistor P2 to form a current mirror circuit CM. A resistor R3 is connected between the drain of the P-channel transistor P3 and the ground node, and a connection point between the drain of the P-channel transistor P3 and the resistor R3 is connected to a CMOS inverter IV.

The CMOS inverter IV operates with the Vcc power supply voltage, and the output of the CMOS inverter IV is supplied as a reset signal to an internal circuit (counter or the like) of the IC.
Resistor R2 and current mirror circuit CM and resistor R3 and
The CMOS inverter IV forms the reset signal output circuit 10.

Next, FIG. 2 (a) shows the operation of the reset circuit.
This will be described with reference to FIG. In the process where the Vcc power supply voltage rises from the ground potential to, for example, 5 V when the power supply of the IC is applied, the Vcc power supply voltage becomes the sum of the threshold voltage VTHP of the P-channel transistor P1 and the threshold voltage VTHN of the N-channel transistor N1 (VTHP + VTHN). Until it reaches, the P-channel transistor P1 and the N-channel transistor N1 are each off, and the current mirror circuit CM is also off.
Therefore, the input of the CMOS inverter IV is at the ground potential by the resistor R3, and the output of the CMOS inverter IV rises with the rise of the Vcc power supply voltage. When the Vcc power supply voltage further increases and reaches a voltage (VTHP + VTHN), for example, 2.5 V, the P-channel transistor P1, the N-channel transistor N1, and the current mirror circuit CM are turned on in this order. Here, FIG. 2 (b) shows the relationship between the source-gate voltage VSG and the drain current Id of the MOS transistor whose gate and drain are connected to each other. When the current Id is small, the voltage VGS can be regarded as almost the threshold voltage VTH. Therefore, the current I (N1) of the N-channel transistor N1 is given by I (N1) = (Vcc-VTH) / (R2 + RonN1) where the on-resistance of the transistor is represented by Ron (N1). Assuming a ratio of 1: 1, the input voltage Vin of the CMOS inverter is Vin = R3 × I (N1) = R3 × (Vcc−VTH) / (R2 + Ron (N1)). If R2 >> Ron (N1), then Vin ≒ R3 × (Vcc−VTH) / R2. Therefore, if the value of Vin is set to be substantially equal to the threshold voltage of the CMOS inverter IV, the operation of the CMOS inverter IV is inverted when the current mirror circuit CM is turned on, and the output is set to the ground potential. descend.

In the above operation, even if the threshold voltage of the MOS transistor fluctuates due to process variations and the threshold voltage of the internal circuit of the IC fluctuates, the threshold voltage of the MOS transistor for detecting the power supply level inside the reset circuit also fluctuates. When a power supply is applied, a required reset signal is reliably generated, and the reset signal can reliably reset the internal circuit of the IC.

In the reset circuit of the above embodiment, the reset signal output circuit 10 that receives the drain output of the N-channel transistor N1 and outputs a reset signal can be variously modified. As shown, a resistor R4 and a P-channel transistor P4
May be connected.

[Effects of the Invention] As described above, according to the present invention, the power supply level is detected by the P-channel transistor and the N-channel transistor. The reset can be surely performed, and a reset circuit of a semiconductor integrated circuit requiring a small number of elements can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a reset circuit of a semiconductor integrated circuit according to the present invention, FIG. 2 (a) is a voltage waveform diagram showing the operation of the reset circuit of FIG. 1, and FIG. 2 (b) is In FIG.
FIG. 3 is a diagram showing characteristics of a MOS transistor, FIG. 3 is a circuit diagram showing another embodiment of the reset circuit of the semiconductor integrated circuit of the present invention, FIG. 4 is a circuit diagram showing a conventional reset circuit, and FIG. FIG. 4 is a voltage waveform diagram showing an operation of the reset circuit shown in FIG. P1 to P4: P-channel transistor, N1: N-channel transistor, R1 to R4: resistor, CM: current mirror circuit, IV: CMOS inverter, 10: reset signal output circuit.

Claims (1)

(57) [Claims] A P-channel transistor having a gate and a drain connected to each other and a first resistor connected in series between a power supply node on a high potential side and a power supply node on a low potential side inside the semiconductor integrated circuit; The gate of the N-channel transistor is connected to the series connection point of the P-channel transistor and the first resistor, the source of the N-channel transistor is connected to the low potential side power supply node, and the drain output of the N-channel transistor is connected to the low potential side power supply node. And a reset signal output circuit for receiving the reset signal, the reset signal output circuit comprising: a second resistor having one end connected to a drain of the N-channel transistor; A third resistor connected to the node and a current having a value proportional to the current flowing through the second resistor are connected to the third resistor. Means for flowing and the input terminal
A reset circuit for a semiconductor integrated circuit, comprising: a CMOS inverter connected to the other end of the resistor.