JP2926921B2 - Power-on reset circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit that prevents a digital circuit from malfunctioning immediately after power-on until the power supply voltage is stabilized.

B. Conventional technology The output of a power-on reset circuit is connected to, for example, a reset terminal of a microcomputer, and immediately after power-on, the reset terminal is set to a high level to reset the microcomputer, and after a predetermined time, the output is again set to a low level. To reset the microcomputer. As described above, the power-on reset circuit prevents a microcomputer or the like from malfunctioning due to an unstable power supply voltage immediately after power-on.

As this power-on reset circuit, a CR detection type shown in FIG. 6 is known (see Japanese Patent Application Laid-Open No. 60-19317), and its outline will be described below.

There are two input circuits to a gate circuit 106 which is an inverter, one of which is connected to a power supply Vcc via a resistor 103,
The other is connected to a power supply Vee via a parallel circuit of a capacitor 104 and a resistor 105. Here, the power supply voltage Vee is a voltage lower than a threshold voltage of the gate circuit 106 (hereinafter, referred to as Vth). When the power supplies Vcc and Vee are turned on, the capacitor 104 is charged by the power supply Vcc, and its terminal voltage V104 gradually increases. When V104 <Vth, the output terminal 107 of the gate circuit 106 is at a high level, and when V104 ≧ Vth, the output terminal 107 is at a low level.

In this CR detection type power-on reset circuit, the time from when the power is turned on to when the output terminal 107 becomes low level (hereinafter, referred to as a reset time) is determined by the CR time constant of the capacitor and the resistor. When the speed rises quickly, the reset time also becomes short. Therefore, the microcomputer may not be able to detect the reset signal. To solve this problem, it is conceivable to increase the CR time constant. However, the chip area of the capacitor and the resistor on the substrate increases, and integration becomes difficult.

In order to solve such a problem of the CR detection type power-on reset circuit, a voltage detection type power-on reset circuit shown in FIG. 7 has been conventionally used.

The outline of the voltage detection type power-on reset circuit will be described with reference to FIG.

1b is a voltage comparison circuit, which includes a current source 1, a differential amplifier 3b,
An output buffer 4 is provided. The MOS field effect transistor (hereinafter, simply referred to as a MOSFET or simply a transistor) 32 of the differential amplifier 3b is a depletion type, and the others are enhancement type MOSFETs. The power supply voltage Vdd is connected to the input terminal 14 of the voltage comparison circuit 1b by the resistor 11 and the resistor 1.
2 and the divided voltage Vdd 'is applied, and the input terminal 15
Is applied with a voltage from the power supply Vdd via the gate protection resistor 13. The voltage applied to the input terminal 15 determines the reference voltage Vref of the voltage comparison circuit 1b.

Here, the drain current Id3 of the transistor 31 when the power is on is the drain current Id3 of the transistor 32.
The sum of 2 and the drain current Id33 of the transistor 33 is expressed as Id31 = Id32 + Id33. As described above, the transistor 32 is a depletion type, and the transistor 33 is an enhancement type. When the power is turned on, the MOS resistance of the transistor 32 is smaller than the MOS resistance of the transistor 33.
When the power is turned on, the drain current Id32 of the transistor 32 becomes larger than the drain current Id33 of the transistor 33, and the gate potentials of the transistors 34 and 35 become higher than their Vth, so that the transistors 34 and 35 are driven on.

If Id32> Id33 and the transistor 35 is on, the gate voltage of the transistor 42 connected to the drain of the transistor 35 does not increase to Vth, and the transistor 42 is driven off. As a result, the drain voltage of the transistor 42 rises and exceeds the Vth of the NOT gate 43, so that the output buffer 4 outputs a high-level signal to the output terminal 5.

As described above, since the transistor 42 is turned off while Id32> Id33, the output terminal 5 is at a high level.

Here, the gate of the transistor 32 is connected to Vd through the resistor 13.
d, the rate of rise of the gate voltage Vref depends on the rate of rise of Vdd. On the other hand, the gate voltage of the transistor 33 is Vdd 'divided by the resistors 11 and 12, and its rising speed is slower than Vref. Therefore, when the drain-source voltage of the transistor 32 is Vref 'and the drain-source voltage of the transistor 33 is Vdd ", Vdd, Vdd', Vdd", Vref '
The changes over time as FIG. 8, Vref at time t ₁ '>
Vdd ".

At time t1, the drain-source voltage Vdd ″ of the transistor 33
Becomes lower than the drain-source voltage Vref ′ of the transistor 32, that is, when the MOS resistance of the transistor 33 becomes smaller than that of the transistor 32, the drain current Id of the transistor 33 becomes larger than the drain current Id32 of the transistor 32. As a result, the drain potential of the transistor 32 decreases, and the transistors 34 and 35 are driven to the off side.
The transistor 35 cannot fully flow d33, and the drain potential of the transistor 35, that is, the gate potential of the transistor 42 rises, and the transistor 42 shifts to the ON side. Further, as a result, the drain potential of the transistor 42 decreases and NO
Vth of the T gate 43 or lower, that is, the output buffer 4
Outputs a low level signal to the output terminal 5. That is, t
= T1, the output of this power-on reset circuit is inverted to a low level.

C. Problems to be Solved by the Invention However, in such a conventional power-on reset circuit, the threshold voltage Vth
Since the reference voltage is generated using a depletion-type MOSFET that has a lot of manufacturing variations, the power-on reset circuit is reset by fluctuations in the power supply voltage during operation and fluctuations in the rise time of the power supply voltage when the power is turned on. In addition to the problem that the time greatly changes, the depletion-type MOSFET also requires a large number of manufacturing steps.

A technical object of the present invention is to reduce the influence of variations in threshold voltages of MOSFETs, to make the reset time of the power-on reset circuit constant, and to reduce the number of manufacturing steps of the power-on reset circuit.

D. Means and Solution for Solving the Problems The present invention will be described with reference to FIG. 1 showing an embodiment. The present invention relates to a method of generating a drain current according to a gate voltage applied to a gate in accordance with a power supply voltage. A first MOSFET 33 to obtain;
The first MOSFET 33 and the source are connected in parallel, a second MOSFET 32 that obtains a drain current according to a gate voltage applied to the gate in accordance with a reference voltage, and a gate voltage of the first MOSFET when power is turned on. Of the first and second
The present invention is applied to a power-on reset circuit using a MOSFET having output means 4 and 51 for outputting a reset signal until the magnitude of the drain current of the MOSFET is inverted.
MOSFETs 33 and 32 are formed in an enhancement type, and the first MOS
The above technical problem is achieved by applying a bias voltage to the substrate of the FET 33 or the second MOSFET 32.

In the above section D describing the configuration of the present invention, although the drawings of the embodiments are used for easy understanding of the present invention, the present invention is not limited to the embodiments.

E. Embodiment -First Embodiment- FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Reference numeral 1 denotes a voltage comparison circuit, which includes a current source 2 and a differential amplifier 3
And an output buffer 4. The current source 2 includes transistors 21 and 22, and supplies a constant voltage to the transistor 31 of the differential amplifier 3 and the gate of the transistor 41 of the output buffer 4.

The differential amplifier 3 includes enhancement-type MOSFET transistors 31 to 35. The substrate potential of the transistor 32 is connected to the power supply Vdd, and the substrate potential of the transistor 33 is connected to the source potential of the transistor. That is, the transistor
32 substrates are reverse biased. The reason why the bias is applied only to the substrate of the transistor 32 is as follows.

FIG. 2 shows the relationship between the substrate bias voltage Vbs and the threshold voltage Vth. As shown in the figure, as the absolute value of the substrate bias voltage Vbs increases, the threshold voltage Vth also increases. However, the rate of increase of Vth decreases as the absolute value of Vbs increases. That is, ΔVth1> ΔVth2
Becomes Therefore, the bias voltage Vb
By multiplying by s, even if the effective bias value fluctuates due to some influence during the operation of the circuit, Vth does not largely fluctuate. That is, the substrate voltage Vre of the voltage comparison circuit 1
Vth of the transistor 32 that determines f 'can be stabilized.

Further, a voltage Vd obtained by dividing the power supply voltage Vdd by the resistors 11 and 12 is connected to the gate of the transistor 33 of the differential amplifier 3.
d 'is applied via input terminal 14. The gate of the transistor 32 of the differential amplifier 3 is connected to the resistor 13 and the input terminal 15.
To the ground potential Vss, and the reference potential Vref is applied.

Transistor 31 is composed of transistors 32 and 33
Is controlled so that the sum of the drain currents of the transistors 32 and 33 is always constant.

Output buffer 4 is composed of transistors 41 and 42 and NOT gate 43.4
4, the output from the differential amplifier 3 is amplified and output to the inverter 51, and the power-on reset signal is output to the output terminal 5.

Next, FIG. 3 shows a voltage change of each part of the circuit shown in FIG.
The operation of the first embodiment will be described with reference to the drawings.

As in the description of FIG. 8, the power supply voltage is Vdd, and the transistor 3
3, the gate voltage is Vdd ′, the drain-source voltage is Vdd ″,
When the drain-source voltage of the transistor 32 is Vref ', these changes with time can be shown as in FIG.

3, the drain-source voltage Vref 'of the transistor 32 takes a constant value, and the drain-source voltage Vdd "of the transistor 33 depends on its gate voltage Vdd'. When the power supply Vdd is turned on at time t = 0, The voltage Vdd 'at the input terminal 14 of the voltage comparison circuit 1 rises as shown in FIG.
Until time t = t2, the drain-source voltage of the transistor 33
Vdd ″ is lower than the drain-source voltage Vref ′ of the transistor 32, that is, since the MOS resistance of the transistor 33 is smaller than the MOS resistance of the transistor 32, the drain current Id of the transistor 33 is larger than the drain current Id of the transistor 32. , The drain current Id of the transistor 35
Cannot flow the drain current Id of the transistor 33, the drain potential of the transistor 33 increases,
And the transistor 42 shifts to the ON side. As a result, the drain potential of the transistor 42 decreases and becomes equal to or lower than Vth of the NOT gate 43. That is, the output buffer 4 outputs a low level signal to the inverter 51.
Inverter 51 inverts this input signal from low level to high level and outputs it to output terminal 5. That is, time t =
Until t2, the output of the power-on reset circuit becomes high level.

Next, when t = t2, the drain-source voltage Vdd ″ of the transistor 33 becomes the drain-source voltage Vre of the transistor 32.
Since it exceeds f ', the MOS resistance of the transistor 32 becomes smaller than the MOS resistance of the transistor 33, and the drain current Id of the transistor 32 increases more than the drain current of the transistor 33. Therefore, the drain potential of the transistor 32, that is, the gate voltage of the transistor 35 increases, and the transistor 35 is driven to the ON side. Then, when the gate voltage of the transistor 42 decreases and the transistor 42 shifts to the off side, the drain potential of the transistor 42 increases and exceeds the Vth of the NOT gate 43. That is, the output buffer 4 outputs a high-level signal to the inverter 51. Inverter 51
Inverts the input high level signal to a low level and outputs it to the output terminal 5.

As described above, the output of the power-on reset circuit of the first embodiment is at a high level until time t = t2, and at a low level after t = t2. At this time, since the MOS transistor 32 forming the reference voltage Vref 'is of the enhancement type and a bias voltage is applied to its substrate, the reference voltage Vref' is not affected by the power supply voltage and the predetermined reset pulse Can be generated.

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment. The same members as those in the first embodiment are denoted by the same reference numerals, and the description will focus on differences.

As in the first embodiment, the differential amplifier 3a is entirely constituted by an enhancement type MOSFET, and the substrate potential of the transistor 133 is set to the power supply Vdd, and the substrate potential of the transistor 132 is set to the source potential of the transistor. That is, only the substrate of the transistor 133 is reverse-biased for the same reason as described above. Further, a voltage Vdd ′ obtained by dividing the power supply voltage Vdd by the resistors 11 and 12 is provided at the gate of the transistor 132.
Is applied through the input terminal 15 of the voltage comparison circuit 1a, and the resistor 13 and the input terminal 14
Is applied with the ground voltage Vss.

FIG. 5 is a time chart showing the change over time of the voltage of each part of the circuit shown in FIG. 4, and FIG.
The operation of this embodiment will be described.

The transistor 1 is used until t = t3 after the power supply Vdd is turned on.
33, the drain-source voltage Vref ′ is higher than the drain-source voltage Vdd ″ of the transistor 132, that is, the MOS resistance of the transistor 133 is larger than the MOS resistance of the transistor 132, and the drain current Id of the transistor 132 is
It is larger than the drain current Id of 33. Therefore, the drain potential of the transistor 132 that determines the gate voltage of the transistors 34 and 35 increases, and the transistors 34 and 35 are driven to the ON side. Then, the drain potential of the transistor 35 decreases, and the transistor 42 is turned off. As a result, when the drain potential of the transistor 42 rises and exceeds the Vth of the NOT gate 43, the output buffer 4 outputs a high-level signal to the output terminal 5.

Next, when t = t3, when the drain-source voltage Vref ′ of the transistor 133 becomes lower than the drain-source voltage Vdd ″ of the transistor 132, the MOS resistance of the transistor 133 becomes smaller than that of the transistor 132, and
Is the drain current Id of the transistor 132
Larger than. Drain current Id of transistor 132
Decreases, the drain potential of the transistor decreases, and the transistor 35 is driven to the off side. Therefore, the transistor 35 cannot fully flow the drain current of the transistor 133, the drain potential increases, and the transistor 43 is turned on. further,
The drain potential of the transistor 42 drops and the NOT gate 43
, And the output buffer 4 outputs a low-level signal from the output terminal 5.

As described above, the power-on reset circuit of the second embodiment outputs a high-level signal until time t = t3, and outputs a low-level signal after t = t3, and affects the power supply voltage for the same reason as described above. It can stabilize without receiving and output reset pulse.

Although the substrate bias is applied to the transistors 32 and 132 in the first and second embodiments, the same effect can be obtained by applying a substrate bias to the transistors 33 and 133. Further, although P-channel MOSFETs are used for the transistors 32, 33, 132, and 133 of the differential amplifiers 3, 3a, they may be configured using N-channel MOSFETs. At this time, the transistors 21, 22, 31, and 41 must also be N-channel MOSFETs, and the transistors 34, 35, and 42 must be P-channel MOSFETs, and the power supply and the ground must be reversed.

F. Effects of the Invention As described above, according to the present invention, a differential amplifier is configured using an enhancement-type MOSFET, and furthermore, one of a transistor to which a reference voltage is applied and a transistor to which a power supply voltage is applied. Since the circuit is used to bias the substrate, the influence of the fluctuation of the threshold voltage during operation is reduced, and the fluctuation of the reset time of the power-on reset circuit is reduced by the rise time of the power supply. In addition, the configuration using the enhancement type MOSFET reduces the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing a relationship between a substrate bias voltage and a threshold voltage, and FIG. 3 is a circuit of FIG. 1 showing a first embodiment. FIG. 4 is a circuit diagram showing the second embodiment, FIG. 4 is a circuit diagram showing the second embodiment, FIG. 5 is a time chart showing the temporal change of the voltage of each circuit shown in FIG. 4, and FIG. Traditional
FIG. 7 is a circuit diagram of a CR type power-on reset circuit, FIG. 7 is a circuit diagram of a conventional voltage detection type power-on reset circuit, and FIG. 8 is a time chart showing a temporal change of the voltage of each circuit shown in FIG. 1: Voltage comparison circuit, 2: Current source 3: Differential amplifier, 4: Output buffer 5: Output, 11, 12, 13: Resistor 21, 22, 31 to 35, 41, 42: MOSFET 43, 44: NOT Gate, 51: inverter

Claims (1)

(57) [Claims] A first MOSFET for obtaining a drain current according to a gate voltage applied to a gate according to a power supply voltage; a first MOSFET and a source connected in parallel; A second MOSFET that obtains a drain current according to an applied gate voltage, and until the magnitudes of the drain currents of the first and second MOSFETs are inverted due to a rise in the gate voltage of the first MOSFET accompanying power-on. Is a power-on reset circuit using a MOSFET having output means for outputting a reset signal, wherein the first and second MOSFETs are formed of an enhancement type, and a bias voltage is applied to a substrate of the first or second MOSFET. A power-on reset circuit using a MOSFET, which is applied.