JP3071654B2 - Power-on reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit, and more particularly to a CMOS (complementary) circuit.
y metal-oxide semiconductor
or a power on / off circuit that is mounted on a semiconductor integrated circuit of a type that generates a predetermined reset signal when the power is turned on or when the power of the semiconductor integrated circuit drops.
It relates to a reset circuit.

[0002]

2. Description of the Related Art Referring to FIG. 7, which is a circuit diagram showing an example of a conventional power-on reset circuit of this type, a high power supply potential (hereinafter, referred to as a power supply potential) VDD and a low power supply potential (hereinafter, referred to as a power supply potential). , A ground potential), a first conductivity type MOS transistor (hereinafter, referred to as a P-type MOS transistor) P6 having a gate and a drain connected to each other, and a resistance element R7 connected in series. Is D. A resistance element R7 is connected in parallel with a capacitance element C2, and a series connection point D is connected to a resistance element R8 and a second conductivity type MOS connected in series between a power supply potential VDD and a ground potential GND.
Transistor (hereinafter referred to as N-type MOS transistor)
Connected to the gate of N3. Capacitive element C3 is connected in parallel to resistance element R8, and resistance element R8 and N-type MO are connected.
The series connection point E of the S transistor N3 is connected to the input terminal of the inverter 6 and its output terminal is connected to the output terminal OUT.

Referring to FIG. 8 showing voltage / time characteristics for explaining the operation together with FIG. 7 described above, the power-on reset circuit first has a power supply potential VDD at time t0.
Is supplied, and as time elapses, the potential increases toward the power supply potential VDD at time t3. This potential VDD becomes P
When the time t1 exceeds the threshold voltage VTP of the p-type MOS transistor P6, the p-type MOS transistor P6
With conduction (ON), the potential of the connection point D also starts to rise, and the potential (V
DD-VTP).

Furthermore, the power supply potential VDD rises, and the connection point D
Is the threshold voltage V of the N-type MOS transistor N3.
At time t2 exceeding TN, the N-type MOS transistor N3 is turned on, and the potential at the connection point E goes to the low level of the logic level. This low level is inverted by the inverter 6 to become a logical high level, which is output to the output terminal OUT. This low level period is used as a power-on reset signal.

Another example of a conventional power-on reset circuit is described in Japanese Patent Application Laid-Open No. Hei 3-206709. Referring to FIG. 9, which shows a circuit diagram of a power-on reset circuit described in the publication, the circuit includes a comparison voltage generator 7, a reference voltage generator 9, and a voltage detector 8 which compares output voltages of these circuits. And an inverting amplifying unit 10 for inverting and outputting the output of the voltage detecting unit 8.
A resistance element R9 and a capacitance element C4 are connected in series between DD and the ground potential GND, and this connection point is used as a comparison voltage output.

[0006] On the other hand, the reference voltage generator 9 is connected to the power supply potential VDD.
MOS transistor N which connects resistance element R10 and gate and drain between ground and ground potential GND
7 are connected in series, and this series connection point is used as a reference voltage output terminal.

The voltage detector 8 includes an N-type MOS transistor N having a power supply potential VDD and a source connected to the ground potential, and a gate commonly connected to the gate and drain of the N-type transistor N7.
7, a series connection circuit of a P-type MOS transistor P7 and an N-type MOS transistor N4 and a series connection circuit of a P-type MOS transistor P8 and an N-type MOS transistor N5 are inserted in parallel with each other,
In addition, the gates of P-type MOS transistors P7 and P8 are connected to the other drains, respectively.
The comparison voltage output terminal is connected to the gate of the OS transistor N4.
A reference voltage output terminal is connected to the gate of the N-type MOS transistor N5. Further, the P-type MOS transistor P8 has a P-type MOS connecting a gate and a drain to each other.
The transistor P9 is inserted in parallel connection, and the drain of the P-type MOS transistor P8 becomes the output terminal of the voltage detection unit.

The output terminal of the voltage detector is connected to the input terminal of the inverting amplifier 10. The inverting amplifier 10 is connected to the power supply voltage VD
D and the other end and input terminal of a capacitive element C5 connecting one end to the ground potential GND, each gate of the inverter 10 including a P-type MOS transistor P10 and an N-type MOS transistor N8 inserted in series between the ground potential GND. And the output terminal of the inverter is connected to the output terminal OUT.

In the power-on reset circuit having the above-described configuration, when the supplied power supply potential VDD starts to rise from 0 V, the potentials at the comparison voltage output terminal and the reference voltage output terminal also rise, and these voltages are supplied. The gates of the N-type MOS transistors N4 and N5 also rise.

Since the threshold voltage VTN5 of the N-type MOS transistor N5 is set lower than the threshold voltages of the N-type MOS transistors N4 and N6, the N-type MOS transistor N5 is turned on first. Become.

Further, the power supply potential VDD rises and the N-type MO
When the P-type MOS transistors P7, P8, and P9 are turned on together with the S-transistors N6 and N7, the drain voltage of the N-type MOS transistor N5 is reduced because the N-type MOS transistor N5 is already turned on. Since P7 is further deeply biased, the drain voltage of the N-type MOS transistor N4 increases.

When the power supply potential VDD further rises, the N-type M
The current flowing through the N-type MOS transistor N4 is larger than the current flowing through the OS transistor N5,
The drain voltage of S transistor N4 decreases.

When the drain voltage of the N-type MOS transistor N4 further exceeds the threshold voltage of the P-type MOS transistor P8, the drain voltage of the N-type MOS transistor N5 sharply rises and becomes almost equal to the power supply potential VDD. The P-type MOS transistor P7 turns off, and the drain of the N-type MOS transistor N4 goes to low level.

At this time, the high level, which is the drain voltage of the N-type MOS transistor N5, is inverted by the inverting amplifier 10 to a low level, and is output from the output terminal OUT as a power-on reset signal.

[0015]

In one example of the above-described conventional power-on reset circuit, a detection voltage (hereinafter, referred to as a detection voltage) is used.
VPOC) is determined by the sum of VT as shown in the following equation.

VPOC ≒ VTN + | VTP | (1) Here, VTN is a threshold voltage of N3, and VTP is a threshold voltage of P6.

Therefore, the manufacturing variation of the threshold voltage is limited to ±
If it is 0.2 [V], the room temperature variation of the detection voltage VPOC becomes ± 0.4 [V]. If the temperature characteristic of the threshold voltage is −2 mV, the temperature characteristic of the detection voltage VPOC is −4 [mV / ° C.].

In another example of the above-described conventional power-on reset circuit, for example, the detection voltage VPOC at the time of rising of the power supply potential VDD is determined by the following equation.

VPOC = | VTP | + VDS (N4) + VDS (N6) = | VTP | + VDS (N4) + VTN (N7) −VTN (N5) (2) Here VTP: threshold voltage of P8 VTN (N7): threshold voltage of N7 VTN (N5): threshold voltage of N5 where VTN (N7)> VTN (N5) VDS (N4): N4 Drain-source voltage VDS (N6): The drain-source voltage of N6. If the manufacturing variation of the threshold voltage is ± 0.2 [V] even if VDS (N4) is ignored, the detection voltage VPOC is Normal temperature variation is ± 0.6 [V],
The temperature characteristic of the detection voltage VPOC is about −2 [mV / ° C.].

Further, the threshold voltage of N5 is N4, N
In order to set the threshold voltage lower than 6, the number of manufacturing steps needs to be increased by one.

In recent years, when a power-on reset circuit is built in to prevent a CPU runaway of a microcomputer, the room temperature variation of the detection voltage VPOC is ± 0 [mV /
° C].

However, this requirement cannot be realized by the conventional power-on reset circuit as described above.

An object of the present invention is to obtain a stable detection voltage which is not affected by manufacturing variations of the threshold voltage without increasing the number of manufacturing steps, and that the detection voltage does not depend on temperature. It is to provide a reliable power-on reset circuit.

[0024]

A power-on reset circuit according to the present invention is characterized in that a power-on reset signal is generated at the start of supply of a power supply voltage of a semiconductor device and at the time of a power supply voltage drop to initialize an internal circuit. In an on-reset circuit, a start-up voltage generating means for generating a start-up voltage for shortening an initial state time from immediately after supply of a power supply voltage to an activation of the internal circuit, and a resistor for generating a first divided voltage A first reference voltage control unit having control voltage generating means also serving as voltage dividing means and a first first conductivity type MOS transistor which conducts during the active state and raises the start-up voltage to a higher power supply potential; second first-conductivity type MOS transistor to one of the constant current source connected to the side supply potential is added in parallel, the second of the Conductivity type MOS transistor is the initial state time to the first first-conductivity type MOS with conductive for a start-up voltage becomes non-conductive at the start-up voltage became high power-supply potential in the active state
A reference voltage generator for controlling the transition to the active state by generating a control voltage for turning on the transistor, wherein a reference voltage output terminal of the reference voltage generator is connected to a first terminal.
And the other input terminal is connected to the first divided voltage output terminal of the control voltage generating means, and the output of the first comparator is powered on.・ It may be a reset signal.

Further, the first in place of the reference voltage control unit, the start-up voltage and the first divided voltage
Together with the second partial pressure of the high-conductive position than this first divided voltage
A second reference voltage control unit that also outputs a voltage,
One second comparator is added in addition to the first comparator.
And the output terminal of the second divided voltage is connected to the second
Connected to one input terminal of the parator and the other input terminal
The collector of the second first conductivity type MOS transistor is
The connection point between the electrode and the constant current source.
The output terminal of the second comparator is connected to one side of a logic circuit.
And the other input terminal is connected to the first comparator.
Data output terminals of the logic circuit
It can be a power-on reset signal .

Furthermore, the power supply voltage supplied simultaneously with the start of the path
The warm-on reset signal becomes active and the logic circuit
It may be Rukoto the inactive state in the logical operation result of the road.

Further, beforeNote2 reference voltage controlDepartment
But theStartupVoltage and said1 divided voltage and
And the second divided voltageSharing means for generating
You can also.

Further, the first reference voltage generating section includes a third first conductivity type MOS transistor and a first second conductivity type MOS transistor connected in series between a higher power supply potential and a lower power supply potential. A second series connection in which a first series-connected body, a fourth first conductivity-type MOS transistor, a second second conductivity-type MOS transistor, and a first resistor connected in series are connected in series. And the third first
The gate of the conductivity type MOS transistor and the gate and drain of the second first conductivity type MOS transistor are connected to each other, and this connection point is used as the output terminal of the control voltage, and the output terminal of the control voltage is connected to the gate. A fifth first conductivity type MOS transistor, a second resistance element, and a first diode having the resistance element as an anode are connected in series between a higher power supply potential and a lower power supply potential;
Resistance element and the fifth first conductivity type MOS transistor
A series connection point of the static as well as an output terminal of said reference voltage, said third first-conductivity-type MOS transistors in parallel the second first-conductivity type MOS transistor is connected to a second first conductivity type of that of The output terminal of the start-up voltage is connected to the gate of the MOS transistor .

Further, the reference voltage generation section includes the first voltage generator.
Second conductivity type MOS transistor and lower power supply potential
A second diode having the lower power supply potential side as a cathode.
Connected to the first resistor element and the lower power supply.
The position third diode you the low-potential-side power supply potential side and the cathode during the Ru can be configured connect to.

Furthermore, the first reference voltage controlDepartment
Is between the higher power supply potential and the lower power supply potential.The first
Of the first conductivity type and the third and fourth resistors.
The resistance element is connected in seriesConnectionThe said1First conductivity type M
The drain of the OS transistor is connected via the first capacitor.
Connected to the lower power supply potential andStart up
StepA voltage output terminal, and said third and fourth resistance elements
The series connection point of thePartial pressure ofCan be configured as a voltage output
SuccessCan alsoYou.

Further, the second reference voltage control section includes a sixth first conductivity type MOS transistor, fifth, sixth and seventh resistance elements between a higher power supply potential and a lower power supply potential. There is an output terminal of said start-up voltage with the drain of the sixth first conductivity type MOS transistors are connected in series is connected to the low-potential power supply potential via a second capacitor, and the sixth and A series connection point of a seventh resistance element is set as an output terminal of the first divided voltage,
And a series connection point of the sixth resistance element Ru can also be an output end of the second divided voltage to configure.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Referring to FIG. 1, the power-on reset circuit of the present embodiment has a start-up function for shortening the time from the start of supply of the power supply voltage to the active state, the first control voltage output during the active state, A reference voltage generator 1a for generating a reference voltage in response to the voltage, a second control voltage for forcibly setting a start-up function of the reference voltage generator 1a to an active state simultaneously with the start of supply of the power supply voltage, and a first control voltage;
A reference voltage controller 2a that outputs a comparison voltage obtained by dividing the power supply voltage at a predetermined ratio in response to the control voltage,
A comparator that compares the comparison voltage and the reference voltage and outputs a comparison result as a detection voltage (reset signal) when the comparison voltage is lower than the reference voltage.

The reference voltage generator 1a is connected between the power supply potential VDD and the ground potential GND by a P-type MOS transistor P1.
And a P-type MOS transistor P2 and N-type MOS transistor N1.
And a series connection circuit in which a type MOS transistor N2 and a resistance element R1 are inserted in series.

The gates and drains of the P-type MOS transistors P1 and P2 are connected to each other and serve as an output terminal of a voltage VCT (hereinafter, referred to as a first control voltage VCT) at the connection point CT, and a gate of the N-type MOS transistor N1. And the drain and the gate of the N-type MOS transistor N2 are connected to each other.

The output terminal of the first control voltage VCT is a P-type MOS.
The P-type MOS transistor P3, the resistance element R2, and the diode D1 having the resistance element as an anode are connected in series between the power supply potential VDD and the ground potential GND, and are connected to the gate of the transistor P3.
ef voltage Vref (hereinafter referred to as reference voltage Vref)
Output end.

Further, a P-type MOS transistor P4 is connected in parallel with the P-type MOS transistor P1, and the gate thereof has a second control voltage VST of the reference voltage control unit 2a described below.
Output terminals are connected to form a start-up function.

Further, the reference voltage control unit 2a supplies the power supply potential V
P-type MOS transistor P5 and resistance elements R3 and R4 are inserted in series between DD and ground potential GND, and the drain of P-type MOS transistor P5 is connected to ground potential GND via capacitive element C1. , A voltage VST at a connection point ST between the P-type MOS transistor P5 and the capacitance element C1 (hereinafter, referred to as a second control voltage VST).
And an output terminal of a voltage Va (hereinafter, referred to as a comparison voltage Va) at a series connection point A of the resistance elements R3 and R4.

In the reference voltage generator 1a having the above-described configuration, for example, the gate lengths and the gate widths of the P-type MOS transistors P1, P2 and P3 are set to the same size, and the gate length of the N-type MOS transistor N1 is set to N2 If the gate width is set to M times with the same size, IEEE JOURNAL OF SOLID-S
TATE CIRCUITS, VOL. SC-14, N
O. 3, 1979, P656, the reference voltage V
ref can be expressed by the following equation.

Vref = N ・ (k ・ T / q) ・ lnM + VF (D1) (3) where: N; (resistance of R2) / (resistance of R1) q; charge of electron Amount, k: Boltzmann's constant, T: absolute temperature VF (D1); forward voltage of D1 Temperature characteristics of reference voltage Vref can be expressed by the following equation.

(Δ / ΔT) · (Vref) = N · (k / q) · lnM + (Δ / ΔT) · (VF (D1)) (4) where (Δ / ΔT) · (VF (D1)); about -2 mV in the temperature coefficient of D1 From the above equation, it is possible to set an arbitrary value by appropriately selecting the coefficients N and M, and obtain the reference voltage Vref whose temperature is guaranteed.

Next, the operation of the reference voltage control section 2a will be described. First, the operation of generating the second control voltage VST for controlling the start-up function will be described.

When the power is turned on, a constant voltage Vref is output in order to start the operation of the drain of N1 from the ground potential and the drain of P2 from the power supply potential due to the parasitic capacitance mainly including the gate capacitance of each MOS transistor. It takes a long time, and the reference voltage generator 1a cannot be used as it is.

Therefore, when the power is turned on, the gate of P4 is grounded via the capacitive element C1, thereby turning on P4, setting the second control voltage VST to low level, turning on P4, and forcing the reference voltage generator 1a. To work. Thereafter, a drain current is passed through P2 and P5 constituting a mirror, and the second control voltage VST is set to a high level by charging the capacitive element C1, and P4 of the reference voltage generating unit 1a is turned off to stop the start-up function. Let it.

Next, the operation of generating the comparison voltage Va is as follows. When the power is turned on, the drain voltage of P5 is at the ground potential GND.
By this low level, the start-up P-type MOS transistor P4 is turned on to activate the reference voltage generator 1a, and the first voltage output from the reference voltage generator 1a is output.
P5 is turned on by the low level of the control voltage VCT,
5 is substantially equal to the power supply voltage VDD.

Accordingly, the potential Va at the connection point A of the series connection of the resistance elements R3 and R4 is determined and operated as in the following equation.

Va = VDD · (R4 / (R3 + R4)) (5) Next, refer to FIG. 2 showing voltage / time characteristics for explaining the operation of the present embodiment. Then, when the power is turned on at time t0, first, the first control voltage VST of the startup generated by the reference voltage control unit 2a becomes low level, and the P-type MOS transistor P4 of the reference voltage generation unit 1a is turned on. At time t1, the first control voltage VST goes high, turning off the P-type MOS transistor P4.

After time t1, the resistance elements R3 and R4
And outputs a comparison voltage Va obtained by dividing the power supply potential VDD by resistance according to the equation (5).

The reference voltage generator 1a enters an active state for generating the reference voltage Vref after time t1, and the voltage Vre
Start outputting f. At time t2 when this voltage Vref exceeds the divided voltage Va, the comparator 3 outputs the high level corresponding to the rising power supply potential VDD level to the output terminal OU.
Output to T.

After time t3 when reference voltage Vref reaches power supply potential VDD necessary for outputting a constant voltage,
The reference voltage Vref determined by the equation (3) is output.

Further, as the time elapses, the power supply potential VDD
Continues to rise, and at time t4, the voltage Va becomes the reference voltage Vref.
, And the output of the comparator 3 is inverted to a low level, and the low level is output from the output terminal OUT as a power-on reset signal. Thereafter, after time t5, the power supply potential VDD becomes constant . Next, a specific example of the variation of the voltage VPOC and the temperature characteristics of the power-on reset circuit according to the present embodiment will be described.

First, the theoretical expression of the voltage VPOC of the power-on reset circuit of the present embodiment is obtained from the expressions (3) and (5) as follows: VPOC = Vref · (1 + R3 / R4) = ｛N · (k
・ T / q) ・ lnM + VF (D1)｝ × (1 + R3 / R
4) .............................. (6)
Further, the temperature characteristic is obtained from the equations (4) and (6) as follows: (Δ / ΔT) · (VPOC) = ｛N · (k / q) · ln
M + (Δ / ΔT) ・ (VF (D1 ) ｝ × (1 + R3 / R
4) ... (7), but the variation at room temperature is, as can be seen from the above equation (6), the value of Vref of (1 + R3 / R
4) times, and is determined by the voltage dividing resistance ratio, the gate width ratio M of N2 to N-type MOS transistor N1, and the forward voltage VF (D1) of diode D1.

Referring to FIG. 3 showing the characteristics of the experimental results of the reference voltage generator 1a of this embodiment, the P-type MOS transistors P1, P2, P3, and N-type MOS of the reference voltage generator 1a are shown.
The sum S of the gate areas of the transistors N1 and N2
(Hereinafter, referred to as gate area S), the reference voltage Vr
variations in room temperature ef 3σ _n-1 (hereinafter, 3 [sigma] _n-1 and referred) on the vertical axis respectively plotted experimental results of (1 [mu] m rule CMOS process).

At this time, the P-type MOS transistors P1, P
2, the gate length and gate width of P3 are the same, and the gate length of N2 is the same as that of the N-type MOS transistor N1, and the gate length is 6 times. 3
σ _n-1 decreases in proportion to the gate area S. As a specific example, an experimental result of 3σ _n-1 = 15 mV at A = 0.1 mm ² (actual size) has been obtained.

[0055] VPOC is, to be independent of the temperature, N · (k / q) · lnM + (Δ / ΔT) · V F (D
1)) = 0 (see equation ( 7 )) When N and M are selected, the reference voltage Vref becomes 1.25 V, and this value is consistent between the calculation and the actual measurement.

Here, if (1 + R3 / R4) = 1.2 so that VPOC = 1.5 V, the variation of the VPOC at room temperature is 3σ _n-1 · (1 + R3 / R4) =
15 × 1.2 = 18 mV.

As described above, without increasing the number of manufacturing steps and regardless of the manufacturing variation of the threshold voltage, the variation of the detection voltage is small, and the power-on with high accuracy without the dependency of the detection voltage on the temperature.・ Reset circuit can be realized.

Referring to FIG. 4 showing a circuit diagram of a second embodiment of the present invention, the difference from the first embodiment is that the N-type MOS transistor of the reference voltage generator 1a shown in FIG. N
1 and a ground potential GND, and a diode D2 is added between the resistance element R1 and the ground potential GND. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

Also in the reference voltage generator 1b of the present embodiment, the relations of the above-mentioned equations (3), (4), (5), (6) and (7) hold. However, the N-type MOS transistors N1 and N2 have the same size, and instead, the value corresponding to M is a diode D3 and a diode D2.
And the same result was obtained.

Further, as shown in FIG. 3, an experimental result has been obtained in which 3σ _n-1 is reduced to 1 / 1.5 times with the same gate area as that of the first embodiment. Therefore, also in this embodiment, it is possible to reduce the variation of the detection voltage at normal temperature.

Referring to FIG. 5, which shows a circuit diagram of the third embodiment of the present invention, the difference from the second embodiment is that the reference voltage controller 2a is replaced with a higher voltage than the comparison voltage Va. Another one
The reference voltage control unit 2 divides the resistance element R3 into a resistance element R5 and a resistance element R6 so as to further include two comparison voltages (hereinafter, the voltage at the series connection point B is referred to as a comparison voltage Vb).
b , the result of comparing the reference voltage Vref and the comparison voltage Va by the comparator 3, and the inverted voltage of the reference voltage Vref (the voltage at the node C of the drain of the P-type MOS transistor P1; hereinafter, referred to as the reference voltage Vc). And the result of comparison of the comparison voltage Vb by the comparator 4 with the OR gate 5
Is output as a reset signal. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

Referring to FIG. 6 showing the voltage / time characteristics for explaining the operation of this embodiment in addition to FIG. 5, the time t
When the power is turned on at 0 and the power supply potential VDD starts to rise,
Since the comparison voltage Va and the reference voltage Vref are compared by the comparator 3 and the remaining operation is the same as that of the second embodiment, the description is omitted here.

On the other hand, up to the power supply voltage VDD required for turning on both the diode D3 and the N-type MOS transistor N1 at time t3 when the power supply potential VDD rises, either of the P-type MOS transistors P4 or P1 Since it is on, it follows the rise of the power supply voltage VDD.

After time t3, the voltage is constant at a voltage determined by the forward voltage of the diode D3 and the drain-source voltage of the N-type MOS transistor N1, regardless of the power supply potential VDD.

Further, at time t4 when the voltage Vb exceeds the voltage Vc after a lapse of time, the output of the comparator 4 changes from the power supply potential VDD at that time to a low level. From time t0 to t4 when this comparator 4 becomes high level
And the period from t2 when the comparator 3 goes high to t
The OR of the outputs up to 4 'is taken by the OR gate 5, and is output to the output terminal OUT as a power-on reset signal.

At this time, the power-on reset signal VPO
Equations (6) and (7) hold because C is determined by the output of the comparator 3, that is, time t4 '. That is,
This embodiment is an example in which a reset signal is guaranteed from a power supply voltage VDD = 0 V as a power-on reset circuit.

The reference voltage controller 2b in the third embodiment is replaced by the reference voltage controller 2b in the first and second embodiments.
a, and the comparator 4 and the OR gate 5
The same effect as in the third embodiment can be obtained by adding

As can be seen from the description of each of the embodiments, the present invention has a start-up function in the reference voltage generators 1a and 1b and the reference voltage controllers 2a and 2b.
Share a circuit for generating a start-up control voltage and a comparison voltage (voltage of a resistive divider).

[0069]

As described above, according to the present invention, the start-up means for shortening the time from the start of the supply of the power supply voltage to the active state, the first control voltage outputted in the active state and the response to this voltage are provided. And a second control voltage and a first control voltage to be supplied to the start-up means so as to forcibly activate the reference voltage generation means simultaneously with the start of supply of the power supply voltage. And reference voltage control means for outputting a first reference voltage obtained by dividing the power supply voltage at a predetermined ratio in response to the reset voltage. Therefore, the number of manufacturing steps for setting the threshold voltage, which was conventionally required low, is not increased, and the manufacturing voltage of the threshold voltage of the field-effect transistor is reduced. Since not affected by luck can reduce variations in the detection voltage, furthermore, there is an effect that the detection voltage is not dependent on temperature, thus built a reliable power-on reset circuit in a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing voltage / time characteristics for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a graph of a reference voltage Vref variation characteristic showing experimental results of a reference voltage generation unit in the embodiment of FIGS.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing voltage / time characteristics for explaining the operation of the embodiment of FIG. 5;

FIG. 7 is a circuit diagram of an example of a conventional power-on-clear circuit.

8 is a diagram showing voltage / time characteristics for explaining the operation of the circuit in FIG. 7;

FIG. 9 is a circuit diagram of another example of a conventional power-on-clear circuit.

[Description of Signs] 1a, 1b Reference voltage generation units 2a, 2b Reference voltage control units 3, 4 Comparator 5 OR gate 6 Inverter 7 Comparison voltage generation unit 8 Voltage detection unit 9 Reference voltage generation unit 10 Inverting amplification units P1 to P10 P MOS transistors N1 to N7 N-type MOS transistors D1 to D3 Diodes R1 to R10 Resistance elements C1 to C5 Capacitance elements

Continuation of the front page (56) References JP-A-6-296125 (JP, A) JP-A-4-265012 (JP, A) JP-A-6-213941 (JP, A) JP-A-4-35523 (JP) , A) JP-A-59-198024 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/22 H03K 17/14 H03K 17/24

Claims (8)

(57) [Claims] 1. A power-on reset circuit for generating a power-on reset signal when a power supply voltage of a semiconductor device starts and when a power supply voltage drops, thereby initializing an internal circuit. Conduction in the active state with control voltage generating means serving also as a start-up voltage generating means for generating a start-up voltage for reducing an initial state time until an active state and a resistive voltage dividing means for generating a first divided voltage A first reference voltage control unit having a first first conductivity type MOS transistor for raising the start-up voltage to a higher power supply potential; and a second constant current source connected to the higher power supply potential.
The first conductivity type MOS transistor is added in parallel, its
The second first conductivity type MOS transistor becomes conductive at the start-up voltage during the initial state time, becomes nonconductive at the start-up voltage at the higher power supply potential in the active state, and has the first first conductivity type. A reference voltage generator for controlling a transition to the active state by generating a control voltage for turning on a MOS transistor, wherein a reference voltage output terminal of the reference voltage generator is connected to one input of a first comparator. And the other input terminal is connected to the first divided voltage output terminal of the control voltage generating means, and the output of the first comparator is used as a power-on reset signal. A power-on reset circuit characterized by the following. Wherein instead of the first reference voltage control unit, the start-up voltage and the first divided voltage together with
Second divided voltage of high-voltage level than the first divided voltage to
A second reference voltage control unit that outputs the first reference voltage
A second comparator in addition to the second comparator, and an output terminal of the second divided voltage is connected to the second comparator.
Connected to one input terminal of the
Is a collector of the second first conductivity type MOS transistor.
Connect the connection point between the electrode and the constant current source and
The output terminal of the second comparator is connected to one input of a logic circuit.
Terminal of the first comparator and the other input terminal of the first comparator.
The output terminal is connected, and the output of the logic circuit is
The power-on circuit according to claim 1, which is an on-reset signal.
Reset circuit. 3. A power supply voltage supplied simultaneously with the start of the power-
The reset signal becomes active, and the logic circuit logic
3. The power-on reset circuit according to claim 2, wherein the power-on reset circuit becomes inactive according to a result of the logical operation . 4. A previous SL second reference voltage control unit, the static
And the first divided voltage and the second divided voltage.
3. The power-on reset circuit according to claim 2, wherein means for generating the divided voltage is shared. 5. The first reference voltage generator, wherein a third first conductivity type M is provided between a higher power supply potential and a lower power supply potential.
A first series connected body in which an OS transistor and a first second conductivity type MOS transistor are connected in series;
First conductivity type MOS transistor and second second conductivity type M
An OS transistor and a second series connection body in which a first resistance element is connected in series, wherein a gate of the third first conductivity type MOS transistor and the fourth first conductivity type MOS transistor are provided. are mutually the gate and a drain connected to the connection point between the output terminal of the control voltage, the fifth first-conductivity-type MOS transistor of which the output terminal of the control voltage is connected to the gate and a second resistor element A first diode having the resistor element as an anode is connected in series between a higher power supply potential and a lower power supply potential, and
Resistance element and the fifth first conductivity type MOS transistor
A series connection point of the static as well as an output terminal of said reference voltage, said third first-conductivity-type MOS transistors in parallel the second first-conductivity type MOS transistor is connected to a second first conductivity type of that of 2. The power-on reset circuit according to claim 1, wherein an output terminal of the start-up voltage is connected to a gate of a MOS transistor . 6. The method according to claim 1, wherein the reference voltage generation unit is configured to output the first and second voltages.
Between the conductivity type MOS transistor and the lower power supply potential
The second diode whose cathode is on the lower power supply potential side
Connected, said first resistive element and the low-potential power supply electric position third you the low-potential-side power supply potential side and the cathode during the diode
Power-on reset circuit of claim 5, wherein constituted connect to the. 7. The first reference voltage control section , wherein the first first conductivity type MOS transistor and third and fourth resistance elements are connected in series between a higher power supply potential and a lower power supply potential. the drain of the connected said first first-conductivity type MOS transistor connected to the output end of the start-up voltage is connected to the low-potential power supply potential via a first capacitor, and the third and fourth 2. The power-on reset circuit according to claim 1 , wherein a series connection point of the resistance elements is configured as an output terminal of the first divided voltage. 8. The second reference voltage control section includes a sixth first conductivity type MO connected between a higher power supply potential and a lower power supply potential.
S transistor and the fifth, the drain of the sixth and seventh resistor element is connected in series to the sixth first conductivity type MOS transistor is connected to the low-potential power supply potential via a second capacitor wherein the output end of the start-up voltage, and the output terminal of the sixth and seventh said first divided voltage and the series connection point of the resistor elements, the series connection point of the fifth and sixth resistance element with a power-on reset circuit of claim 2, wherein consists in the output end of the second divided voltage.