JPH08186484A - Power-on reset circuit - Google Patents

Abstract

PURPOSE: To provide the power-on reset circuit where the variance of a detection voltage (reset signal) is small and the detection voltage is not dependent upon the temperature change. CONSTITUTION: This system is provided with a start-up function which shortens the time required to enter into the active state after the supply start of a supply voltage VDD, a reference voltage generation part 1a which generates a control voltage VCT to be outputted in the active state and generates a prescribed reference voltage Vref in response to this control voltage, a control voltage VST which is supplied to the start-up function so as to forcibly set the reference voltage generation part 1a to the active state simultaneously with the supply start of the supply voltage VDD, and a reference voltage control part 2a which outputs a comparison voltage Va obtained by dividing the supply voltage VDD at a prescribed ratio in response to the voltage VCT. Since the reset signal for power-on and power fall is obtained from the comparison result between the reference voltage Vref and the comparison voltage Va, the power-on reset circuit of high reliability is incorporated in a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit, and more particularly to a CMOS (complementar).
y metal-oxide semiconductor
or a transistor type semiconductor integrated circuit, and generates a predetermined reset signal when the semiconductor integrated circuit is powered on or powered down.
Regarding the reset circuit.

[0002]

2. Description of the Related Art Referring to FIG. 7, which is a circuit diagram showing an example of a conventional power-on reset circuit of this type, a high-side power supply potential (hereinafter referred to as a power supply potential) VDD and a low-side power supply potential (hereinafter referred to as a power supply potential). , A first conductivity type MOS transistor (hereinafter referred to as a P-type MOS transistor) P6 having a gate and a drain connected to each other, and a resistance element R7, which are connected in series to each other. Be D. A capacitive element C2 is connected in parallel to the resistive element R7, and a series connection point D is a resistive element R8 and a second conductivity type MOS connected in series between the power supply potential VDD and the ground potential GND.
Transistor (hereinafter referred to as N-type MOS transistor)
Connected to the gate of N3. The capacitive element C3 is connected in parallel to the resistive element R8, and the resistive element R8 and the N-type MO are connected.
The serial connection point E of the S transistor N3 is connected to the input end of the inverter 6 and its output end is connected to the output terminal OUT.

Referring to FIG. 8 showing the voltage / time characteristic for explaining the operation in addition to FIG. 7 described above, the power-on reset circuit firstly supplies the power supply potential VDD at time t0.
Is supplied, and the potential rises toward the power supply potential VDD at time t3 with the lapse of time. This potential VDD is P
At time t1 when the threshold voltage VTP of the P-type MOS transistor P6 is exceeded, the P-type MOS transistor P6 becomes
The potential at the connection point D starts to rise as well as to be conductive (ON), and the potential (V
DD-VTP) is reached.

Further, the power supply potential VDD rises, and the connection point D
Is the threshold voltage V of the N-type MOS transistor N3.
At time t2 that exceeds TN, the N-type MOS transistor N3 is turned on, and the potential at the connection point E becomes a logic low level. This low level is inverted by the inverter 6 and becomes a logic high level, which is output to the output terminal OUT. This low level period is used as a power-on reset signal.

Another example of the conventional power-on reset circuit is described in Japanese Patent Laid-Open No. 3-206709. Referring to FIG. 9 showing a circuit diagram of a power-on reset circuit described in the publication, this circuit includes a comparison voltage generation unit 7, a reference voltage generation unit 9 and a voltage detection unit 8 for comparing output voltages of these circuits. And an inverting amplifier 10 that inverts and outputs the output of the voltage detector 8, and the comparison voltage generator 7 includes a power supply potential V
A resistance element R9 and a capacitance element C4 are connected in series between DD and the ground potential GND, and this series connection point serves as a comparison voltage output.

On the other hand, the reference voltage generating section 9 has a power supply potential VDD.
And a grounding potential GND between the resistance element R10 and the N-type MOS transistor N for connecting the gate and the drain to each other.
7 are connected in series, and this connection point is used as a reference voltage output terminal.

The voltage detection unit 8 has an N-type MOS transistor N having a power supply potential VDD, a source connected to the ground potential, and a gate commonly connected to the gate and drain of the N-type transistor N7.
A series connection circuit of the P-type MOS transistor P7 and the N-type MOS transistor N4 and a series connection circuit of the P-type MOS transistor P8 and the N-type MOS transistor N5 are inserted in parallel with each other between the drain and the drain of 7.
The gates of the P-type MOS transistors P7 and P8 are connected to the drains of the other, respectively, and the N-type M
The gate of the OS transistor N4 has a comparison voltage output terminal,
A reference voltage output terminal is connected to the gate of the N-type MOS transistor N5. Further, the P-type MOS transistor P8 has a P-type MOS whose gate and drain are connected to each other.
The transistor P9 is inserted in parallel connection, and the drain of the P-type MOS transistor P8 becomes the output terminal of the voltage detection unit.

The output terminal of the voltage detecting section is connected to the input terminal of the inverting amplifier section 10. The inverting amplification unit 10 uses the power supply voltage VD
The other end and the input end of the capacitive element C5, which connects the gate and one end of the inverter 10 including the P-type MOS transistor P10 and the N-type MOS transistor N8 inserted in series between D and the ground potential GND, to the ground potential GND Is connected in common and the output terminal of the inverter is connected to the output terminal OUT.

In the power-on reset circuit having the above-described structure, when the supplied power supply potential VDD starts to rise from 0V, the respective potentials of the comparison voltage output end and the reference voltage output end also rise, and these voltages are supplied. The gates of the N-type MOS transistors N4 and N5 are also raised.

Since the threshold voltage VTN5 of the N-type MOS transistor N5 is set lower than the threshold voltages of the N-type MOS transistors N4 and N6, the N-type MOS transistor N5 is turned on first. Become.

Further, the power supply potential VDD rises, and the N-type MO
When the P-type MOS transistors P7, P8, and P9 are turned on together with the S transistors N6 and N7, the drain voltage of the N-type MOS transistor N5 is lowered because the N-type MOS transistor N5 is already turned on, and the P-type MOS transistor N5 is turned on. Since P7 is biased deeper, the drain voltage of the N-type MOS transistor N4 rises.

When the power supply potential VDD further rises, an N-type M
The current flowing through the N-type MOS transistor N4 is larger than the current flowing through the OS transistor N5.
The drain voltage of the S transistor N4 decreases.

When the drain voltage of the N-type MOS transistor N4 further exceeds the threshold voltage of the P-type MOS transistor P8, the drain voltage of the N-type MOS transistor N5 sharply rises and becomes substantially equal to the power supply potential VDD voltage. The P-type MOS transistor P7 is turned off, and the drain of the N-type MOS transistor N4 becomes low level.

The high level, which is the drain voltage of the N-type MOS transistor N5 at this time, is inverted by the inverting amplifier 10 to a low level, and is output as a power-on reset signal from the output terminal OUT.

[0015]

In one example of the conventional power-on reset circuit described above, the detection voltage (hereinafter, referred to as
VPOC) is determined by the sum of VT as shown in the following equation.

VPOC≈VTN + | VTP | ………………………… (1) Here, it is assumed that the threshold voltage of VTN: N3 and the threshold voltage of VTP: P6.

Therefore, the manufacturing variation of the threshold voltage is ±
At 0.2 [V], the room temperature variation of the detection voltage VPOC is ± 0.4 [V]. When the temperature characteristic of the threshold voltage is −2 mV, the temperature characteristic of the detection voltage VPOC is −4 [mV / ° C.].

In the case of another example of the conventional power-on reset circuit described above, for example, the detection voltage VPOC at the rise of the power supply potential VDD is determined by the following equation.

VPOC = | VTP | + VDS (N4) + VDS (N6) = | VTP | + VDS (N4) + VTN (N7) -VTN (N5) ……………………………… (2) Here VTP: P8 threshold voltage VTN (N7): N7 threshold voltage VTN (N5): N5 threshold voltage However, VTN (N7)> VTN (N5) VDS (N4): N4 Drain-source voltage VDS (N6): N6 drain-source voltage Therefore, even if VDS (N4) is ignored, if the manufacturing variation of the threshold voltage is ± 0.2 [V], the detected voltage VPOC Room temperature variation is ± 0.6 [V],
The temperature characteristic of the detection voltage VPOC is about −2 [mV / ° C.].

Further, the threshold voltage of N5 is N4, N
In order to set it lower than the threshold voltage of 6, it is necessary to increase the number of manufacturing steps by one.

In recent years, when a power-on reset circuit is built in to prevent CPU runaway in a microcomputer, the room temperature variation of the detection voltage VPOC is ± 0 [mV / mV
℃] is coming out.

However, this requirement cannot be realized by the conventional power-on reset circuit as described above.

The object of the present invention is to obtain a stable detection voltage which is not affected by manufacturing variations in the threshold voltage without increasing the number of manufacturing steps, and the detection voltage does not depend on temperature. It is to provide a highly reliable power-on reset circuit.

[0024]

The feature of the power-on reset circuit of the present invention is that the power-on reset circuit generates a reset signal at the start of the power supply voltage supply of the semiconductor device and at the time of the power supply voltage drop to initialize the internal circuit. The circuit has a start-up means for shortening the time from the start of the supply of the power supply voltage to the active state, and outputs the first control voltage in the active state and generates a predetermined reference voltage in response to this voltage. A reference voltage generating means and a second power supply voltage that is supplied to the start-up means at the same time when the power supply voltage starts to be forced to activate the reference voltage generating means and the first control voltage to set a predetermined power supply voltage. And a first comparison voltage divided by the ratio of
The reference voltage control means is provided, the reference voltage and the comparison voltage are compared by the comparison means, and the comparison result is output as the reset signal.

Further, in place of the first reference voltage control means, there is provided second comparison voltage control means further comprising a second comparison voltage higher than the first comparison voltage, and the reference voltage and the second comparison voltage control means are provided. It is possible to output a logical sum result of the comparison result of one comparison voltage and the comparison result of the inversion voltage of the reference voltage and the second comparison voltage as the reset signal.

Further, the reset signal can be activated at the same time when the supply of the power supply voltage is started, and can be deactivated according to the comparison result of the first comparison voltage.

Furthermore, the first and second reference voltage control means may share the means for generating the second control voltage and the first and second comparison voltages.

Further, the reference voltage generating means has a first first conductivity type M between the high potential side power source potential and the low potential side power source potential.
A first series connection circuit having an OS transistor and a first second conductivity type MOS transistor inserted in series connection, a second first conductivity type MOS transistor, a second second conductivity type MOS transistor, and a first resistor. An element and a second series connection circuit inserted in series connection, and the first first
The gate of the conductivity type MOS transistor and the gate and the drain of the second first conductivity type MOS transistor are connected to each other, and the connection point serves as an output terminal of the first control voltage, and the first second conductivity type MOS transistor A third first-conductivity-type MOS transistor in which a gate and a drain of the transistor are connected to each other and a gate of the second second-conductivity-type MOS transistor is connected to each other, and an output terminal of the first control voltage is connected to the gate; The second resistance element and the first diode having the resistance element side as an anode are inserted in series between the high-potential power supply potential and the low-potential power supply potential, and the series connection point is used as an output end of the reference voltage. First first conductivity type MOS
A fourth first conductivity type MOS transistor is connected in parallel with the transistor, and the gate of the fourth first conductivity type MOS transistor is connected to the output end of the second control voltage.

Further, the reference voltage generating means includes a second and a second low-side power supply potential side having a cathode as a cathode between the first second-conductivity-type MOS transistor and the first resistance element and the low-side power supply potential. It is configured by inserting third diodes, respectively.

Furthermore, in the first reference voltage control means, the fifth first-conductivity-type MOS transistor and the third and fourth resistance elements are connected in series between the high potential side power source potential and the low potential side power source potential. The fifth MOS of the first conductivity type inserted by connection
The drain of the transistor is connected to the low-potential side power supply potential via the first capacitive element, serves as the output terminal of the second control voltage, and the series connection point of the third and fourth resistive elements is connected to the first comparison point. It is configured as a voltage output terminal.

The second reference voltage control means includes a sixth first-conductivity-type MOS transistor and fifth, sixth, and seventh resistance elements between the high-potential-side power source potential and the low-potential-side power source potential. Is inserted in series and the sixth MOS of the first conductivity type is inserted.
The drain of the transistor is connected to the low-potential side power supply potential via the second capacitance element, serves as the output terminal of the first control voltage, and the series connection point of the sixth and seventh resistance elements is connected to the first comparison voltage. The output end of the fifth and sixth
The series connection points of the resistance elements are each configured as an output terminal of the second comparison voltage.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Referring to FIG. 1, the power-on / reset circuit of the present embodiment has a start-up function for shortening the time from the start of power supply voltage supply to the active state, and a first control voltage output in the active state and A reference voltage generator 1a that generates a reference voltage in response to this voltage, and a second control voltage and a first control voltage that forcefully activate the startup function of the reference voltage generator 1a at the same time when the supply of the power supply voltage is started.
A reference voltage control unit 2a which outputs a comparison voltage obtained by dividing the power supply voltage at a predetermined ratio in response to the control voltage,
The comparator 3 compares the comparison voltage and the reference voltage, and outputs the comparison result as a detection voltage (reset signal) when the comparison voltage is lower than the reference voltage.

The reference voltage generating section 1a has a P-type MOS transistor P1 between the power supply potential VDD and the ground potential GND.
And a series connection circuit in which N-type MOS transistors N1 are inserted in series connection, and P-type MOS transistors P2 and N
Type MOS transistor N2 and resistance element R1 are inserted in series connection.

The gates and drains of the P-type MOS transistors P1 and P2 are connected to each other and serve as the output terminal of the voltage VCT at the connection point CT (hereinafter referred to as the first control voltage VCT), and the gate of the N-type MOS transistor N1. And the drain and the gate of the N-type MOS transistor N2 are connected to each other.

The output terminal of the first control voltage VCT is a P-type MOS
The P-type MOS transistor P3, the resistance element R2, and the diode D1 having the resistance element side as an anode, which are connected to the gate of the transistor P3, are inserted in series between the power supply potential VDD and the ground potential GND, and the series connection point r
Voltage Vref of ef (hereinafter referred to as reference voltage Vref)
The output end of.

Further, a P-type MOS transistor P4 is connected in parallel with the P-type MOS transistor P1 and its gate has a second control voltage VST of the reference voltage control unit 2a described below.
The output end of is connected to form the start-up function.

Further, the reference voltage control unit 2a has the power supply potential V
A P-type MOS transistor P5 and resistance elements R3 and R4 are inserted in series between DD and the ground potential GND, and the drain of the P-type MOS transistor P5 is connected to the ground potential GND via the capacitive element C1. , The voltage VST at the connection point ST between the P-type MOS transistor P5 and the capacitive element C1 (hereinafter referred to as the second control voltage VST)
And the series connection point A of the resistance elements R3 and R4 is configured as the output terminal of the comparison voltage Va.

In the reference voltage generator 1a having the above-described structure, for example, the P-type MOS transistors P1, P2 and P3 have the same gate length and the same gate width, and the N-type MOS transistor N1 has a gate length N2. If the size is the same and the gate width is set to M times, the reference voltage Vref can be expressed by the following equation.

Vref = N (kT / q) lnM + VF (D1) ... (3) where N; (R2 resistance value) / (R1 resistance value) q; electron charge Quantity, k; Boltzmann's constant, T; absolute temperature VF (D1); forward voltage of D1 Further, the temperature characteristic of the reference voltage Vref can be expressed by the following equation.

(Δ / ΔT) · (Vref) = N · (k / q) · lnM + (Δ / ΔT) · (VF (D1)) (4) where (Δ / ΔT) · (VF (D1)); Temperature coefficient of D1 is about -2 mV From the above equation, the coefficients N and M can be set to arbitrary values by appropriate selection, and the temperature-guaranteed reference voltage Vref can be obtained.

Next, the operation of the reference voltage controller 2a will be described. First, the operation of generating the second control voltage VST for controlling the start-up function will be described.

When the power is turned on, a constant voltage Vref is output because the drain of N1 starts its operation from the ground potential and the drain of P2 starts its operation from the power supply potential due to the parasitic capacitance mainly consisting of the gate capacitance of each MOS transistor. It takes time until the reference voltage generator 1a cannot be used as it is.

Therefore, when the power is turned on, the gate of P4 is grounded via the capacitive element C1 to turn on P4 and set the second control voltage VST to low level to turn on P4, forcing the reference voltage generator 1a. To operate. After that, a drain current is caused to flow through P2 and P5 that form a mirror to charge the capacitive element C1 to set the second control voltage VST to a high level, and P4 of the reference voltage generation unit 1a is turned off to stop the start-up function. Let

Next, in the operation of generating the comparison voltage Va, the drain voltage of P5 when the power is turned on is at the ground potential GND.
This low level causes the reference voltage generation unit 1a to be in an operating state by turning on the P-type MOS transistor P4 at startup, and the first voltage output from the reference voltage generation unit 1a
P5 is turned on by the low level of the control voltage VCT, and P5
The drain voltage of 5 becomes substantially equal to the power supply voltage VDD.

Therefore, the potential Va of the series connection point A of the resistance elements R3 and R4 is determined by the following equation and operates.

Va = VDD · (R4 / (R3 + R4)) (5) Next, refer to FIG. 2 showing the voltage / time characteristics for explaining the operation of the present embodiment. Then, when the power is turned on at time t0, first, the first control voltage VST of the startup generated by the reference voltage control unit 2a becomes low level, and the P-type MOS transistor P4 of the reference voltage generation unit 1a is turned on, At time t1, the first control voltage VST becomes high level and the P-type MOS transistor P4 is turned off.

After time t1, the resistance elements R3 and R4 are
And operates as a voltage dividing circuit according to the formula (5) to output a comparison voltage Va obtained by resistance-dividing the power supply potential VDD according to the equation (5).

The reference voltage generator 1a is in an active state for generating the reference voltage Vref after the time t1, and the voltage Vre is reached.
Start to output f. At time t2 when this voltage Vref exceeds the divided voltage Va, the comparator 3 outputs a high level corresponding to the rising power supply potential VDD level to the output terminal OU.
Output to T.

After the time t3 when the reference voltage Vref reaches the power supply potential VDD necessary for outputting a constant voltage,
The reference voltage Vref determined by the equation (3) is output.

Further, the power supply potential VDD increases with time.
Continues to rise, and at time t4, the voltage Va changes to the reference voltage Vref.
Becomes a power supply potential VDD (= VPOC), and the output of the comparator 3 is inverted to a low level, and the low level is output from the output terminal OUT as a power-on reset signal. After that, the power supply potential VDD becomes constant after time 5, and then a concrete example of the variation in the voltage VPOC and the temperature characteristic of the power-on reset circuit according to the present embodiment will be shown.

First, from the equations (3) and (5), the theoretical formula of the voltage VPOC of the power-on reset circuit of this embodiment is as follows: VPOC = Vref. (1 + R3 / R4) = {N. (k.T / q) · lnM + VF (D1)} × (1 + R3 / R4) …………………………………… (6), and the temperature characteristics are calculated from equations (4) and (6). (Δ / ΔT) · (VPOC) = {N · (k / q) · lnM + (Δ / ΔT) · (VF (D1} · (1 + R3 / R4)… (7), but there are variations at room temperature. As can be seen from the above equation (6), Vref is (1 + R3 / R4) times, and the voltage dividing resistance ratio, the gate width ratio M of N2 to the N-type MOS transistor N1, and the quasi-directional voltage VF (D1) of the diode D1. Is determined by

Referring to FIG. 3 showing the characteristics of the experimental results of the reference voltage generator 1a of this embodiment, the P-type MOS transistors P1, P2, P3 and N-type MOS of the reference voltage generator 1a are shown.
The sum S of the gate areas of the transistors N1 and N2
(Hereinafter, referred to as gate area S), the reference voltage Vr is plotted on the horizontal axis.
The experimental result (1 μm rule CMOS process) in which the variation of ef at room temperature 3σ _n-1 (hereinafter referred to as 3σ _n-1 ) is plotted on the vertical axis is shown.

At this time, the P-type MOS transistors P1 and P
The gate length and the gate width of each of P2 and P3 are the same size, and the gate length of N2 is the same size as that of the N-type MOS transistor N1, and the gate length is 6 times. Three
σ _n-1 decreases in proportion to the gate area S. As a specific example, the experimental result of 3σ _n-1 = 15 mV at A = 0.1 mm ² (actual size) is obtained.

Select N and M such that N · (k / q) · lnM + (Δ / ΔT) · (VF (D1)) = 0 (see equation (8)) so that VPOC does not depend on temperature. Then, the reference voltage Vref = 1.25 V is obtained, and this value is in agreement with the calculation.

Assuming that (1 + R3 / R4) = 1.2 so that VPOC = 1.5V, the variation of VPOC at room temperature is 3σ _n-1 · (1 + R3 / R4) =
15 × 1.2 = 18 mV.

From the above, a highly accurate power-on that does not increase the number of manufacturing steps, is small in the variation of the detection voltage regardless of the variation in the threshold voltage, and does not depend on the temperature of the detection voltage.・ Reset circuit can be realized.

Referring to FIG. 4 which is a circuit diagram of the second embodiment of the present invention, the difference from the first embodiment is that the N-type MOS transistor of the reference voltage generator 1a shown in FIG. N
That is, the diode D3 is added between 1 and the ground potential GND, and the diode D2 is added between the resistance element R1 and the ground potential GND. The other constituents are the same, and the same constituents are designated by the same reference numerals and the description thereof will be omitted.

Also in the reference voltage generator 1b of this embodiment, the relationships of the equations (3), (4), (5), (6), and (7) described above are established. However, the N-type MOS transistors N1 and N2 have the same size, and instead of the values corresponding to M, the diode D3 and the diode D2 are used.
The same result was obtained by using the ratio of the bonding area of and.

Further, as shown in FIG. 3, an experimental result has been obtained that 3σ _n-1 is as small as 1 / 1.5 times in the same gate area as in the first embodiment. Therefore, also in this embodiment, the variation in the detected voltage at room temperature can be reduced.

Referring to FIG. 5 showing the circuit diagram of the third embodiment of the present invention, the difference from the second embodiment is that the reference voltage control unit 2a is replaced by a voltage higher than the comparison voltage Va. Another one
A reference voltage control unit 1 in which the resistance element R3 is divided into a resistance element R5 and a resistance element R6 so as to further include one comparison voltage (hereinafter, the voltage at the series connection point B is referred to as a comparison voltage Vb).
b, and the result of comparing the reference voltage Vref and the comparison voltage Va with the comparator 3 and the inversion voltage of the reference voltage Vref (the voltage at the connection point C of the drain of the P-type MOS transistor P1. Hereinafter referred to as the reference voltage Vc). And the result of comparison of the comparison voltage Vb by the comparator 4 with the OR gate 5
That is, the result of the logical sum is output as a reset signal. The other constituents are the same, and the same constituents are designated by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 6 showing the voltage / time characteristic for explaining the operation of the present embodiment in addition to FIG. 5 described above, the time t
When the power is turned on at 0 and the power supply potential VDD starts to rise,
The operation of comparing the comparison voltage Va with the reference voltage Vref by the comparator 3 is the same as that of the second embodiment, so the description thereof is omitted here.

On the other hand, the reference voltage Vc is either the P-type MOS transistor P4 or P1 up to the power-supply voltage VDD required to turn on both the diode D3 and the N-type MOS transistor N1 at time t3 when the power supply potential VDD rises. Is on, it follows the rise of the power supply voltage VDD.

After time t3, the voltage is constant regardless of the power supply potential VDD and is determined by the forward voltage of the diode D3 and the drain-source voltage of the N-type MOS transistor N1.

Further, after a lapse of time, at time t4 when the voltage Vb exceeds the voltage Vc, the output of the comparator 4 changes from the power supply potential VDD at that time to the low level. From the time t0 when the comparator 4 becomes high level to t4
Period from t2 to t when the comparator 3 becomes high level
By ORing the outputs of the periods up to 4 ′ with the OR gate 5, it is output to the output terminal OUT as a power-on reset signal.

At this time, the power-on reset signal VPO
Since C is determined by the output of the comparator 3, that is, at the time t4 ', the equations (6) and (7) hold. That is,
The present embodiment is an example in which a power-on reset circuit guarantees a reset signal from a power supply voltage VDD = 0V.

The reference voltage control unit 2b in the third embodiment described above is replaced by the reference voltage control unit 2 in the first and second embodiments.
applied in place of a, the comparator 4 and the OR gate 5
It is also possible to obtain the same effect as that of the third embodiment by adding.

As can be seen from the above description of each embodiment, the present invention has the reference voltage generators 1a and 1b having a start-up function, and the reference voltage controllers 2a and 2b.
Shares the generation circuit of the control voltage for start-up and the comparison voltage (voltage of divided voltage by resistance).

[0069]

As described above, according to the present invention, the start-up means for shortening the time from the start of supplying the power supply voltage to the active state, the first control voltage output in the active state and the response to this voltage. The reference voltage generating means for generating a predetermined comparison voltage, and the second control voltage and the first control voltage supplied to the start-up means so as to forcefully activate the reference voltage generating means at the same time when the supply of the power supply voltage is started. And a reference voltage control means for respectively outputting a first reference voltage obtained by dividing the power supply voltage at a predetermined ratio in response, and a reset signal at power-on and power-down based on the comparison voltage and the comparison result of the reference voltages. Therefore, it is possible to obtain the threshold voltage of the field-effect transistor without increasing the manufacturing process for setting the threshold voltage to be low, which was required in the past. Since not affected by luck can reduce variations in the detection voltage, furthermore, there is an effect that the detection voltage is not dependent on temperature, thus built a reliable power-on reset circuit in a semiconductor device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing voltage / time characteristics for explaining the operation of the embodiment of FIG.

FIG. 3 is a diagram of reference voltage Vref variation characteristics showing an experimental result of the reference voltage generation unit in the embodiments of FIGS.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing voltage / time characteristics for explaining the operation of the embodiment of FIG.

FIG. 7 is a circuit diagram of an example of a conventional power-on / clear circuit.

8 is a diagram showing voltage / time characteristics for explaining the circuit operation of FIG.

FIG. 9 is a circuit diagram of another example of a conventional power-on-clear circuit.

[Explanation of Codes] 1a, 1b Reference voltage generation unit 2a, 2b Reference voltage control unit 3,4 Comparator 5 OR gate 6 Inverter 7 Comparison voltage generation unit 8 Voltage detection unit 9 Reference voltage generation unit 10 Inversion amplification unit P1 to P10 P Type MOS transistors N1 to N7 N type MOS transistors D1 to D3 Diodes R1 to R10 Resistive elements C1 to C5 Capacitive elements

Claims (8)

[Claims] 1. A power-on reset circuit for generating a reset signal to initialize an internal circuit when power supply voltage starts to be supplied to a semiconductor device and when the power supply voltage drops. And a reference voltage generating means for outputting a first control voltage when activated and generating a predetermined reference voltage in response to this voltage; A second control voltage which is supplied to forcibly activate the reference voltage generating means and a first comparison voltage which is obtained by dividing the power supply voltage by a predetermined ratio in response to the first control voltage; 1 reference voltage control means, the reference voltage and the comparison voltage are compared by the comparison means, and the comparison result is output as the reset signal. A power-on reset circuit characterized in that 2. A second comparison voltage control means further comprising a second comparison voltage higher than the first comparison voltage in place of the first reference voltage control means, the reference voltage and the second comparison voltage control means. 2. The power-on reset circuit according to claim 1, wherein a logical sum result of the comparison result of one comparison voltage and the inversion voltage of the reference voltage and the comparison result of the second comparison voltage is output as the reset signal. 3. The power-on reset circuit according to claim 2, wherein the reset signal becomes active at the same time when the supply of the power supply voltage is started, and becomes inactive as a result of the comparison of the first comparison voltage. 4. The power according to claim 1, wherein the first and second reference voltage control means share the means for generating the second control voltage and the first and second comparison voltages. On-reset circuit. 5. The first reference conductivity type MOS is arranged between the high-potential side power source potential and the low-potential side power source potential.
A first series connection circuit in which a transistor and a first second conductivity type MOS transistor are inserted in series connection, a second first conductivity type MOS transistor and a second second conductivity type MO
An S transistor and a second series connection circuit in which a first resistance element is inserted in series connection, and a gate of the first first conductivity type MOS transistor and the second first conductivity type MOS transistor. Of the first and second MOS transistors are connected to each other, and the connection point is used as an output terminal of the first control voltage, and the gate and drain of the first second conductivity type MOS transistor and the second second conductivity type MOS transistor are connected. A third first-conductivity-type MOS transistor having gates connected to each other and an output terminal of the first control voltage connected to the gate; a second resistance element; and a first diode having the resistance element side as an anode. Is inserted in series between the high-potential side power source potential and the low-potential side power source potential, and this series connection point is used as the output terminal of the reference voltage and in parallel with the first first-conductivity-type MOS transistor. The first conductivity type MOS transistor is connected to POWER ON reset circuit according to claim 1 or 2 wherein Pas configured to include the start-up means for the output end of the second control voltage to the gate is connected to 4. 6. The reference voltage generating means comprises a second and a second low-side power supply potential side having a cathode as a cathode between the first second-conductivity-type MOS transistor and the first resistance element and the low-side power supply potential. The power-on reset circuit according to claim 5, wherein the power-on reset circuit is formed by inserting each third diode. 7. The first reference voltage control means comprises a fifth first conductivity type M between a high-potential side power source potential and a low-potential side power source potential.
The OS transistor and the third and fourth resistance elements are inserted in series connection, and the drain of the fifth first-conductivity-type MOS transistor is connected to the low-potential side power supply potential via the first capacitance element and 2 Control voltage output terminal,
The power-on reset circuit according to claim 1, wherein a series connection point of the third and fourth resistance elements is configured as an output terminal of the first comparison voltage. 8. The second reference voltage control means comprises a sixth first conductivity type M between a high potential side power source potential and a low potential side power source potential.
The OS transistor and the fifth, sixth, and seventh resistance elements are inserted in series, and the drain of the sixth first-conductivity-type MOS transistor is connected to the low-potential-side power supply potential via the second capacitance element. And a series connection point of the sixth and seventh resistance elements as a first comparison voltage output terminal, and a series connection point of the fifth and sixth resistance elements as a first connection point. The power-on reset circuit according to claim 2, wherein the power-on reset circuit is configured as an output terminal of each of the two comparison voltages.