JP2008048298A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device equipped with a low-power-consumption and high-precision power source detection circuit. <P>SOLUTION: The semiconductor integrated circuit device has a startup circuit which operates at a first supply voltage, a constant current source of self-bias type, a reference voltage generating part and a voltage comparison circuit. The constant current source of self-bias type forms a constant current corresponding to the differential voltage between threshold voltages of a first transistor and a second transistor by a first resistance element and applies it also to the first transistor through the second transistor and a current mirror circuit. The reference voltage generating part forms the reference voltage by using the constant current and supplies it to the voltage comparison circuit. The voltage comparison circuit compares the reference voltage with a second supply voltage and forms a power source detection signal. The startup circuit forms a starting voltage in such a way that the reference voltage is a voltage corresponding to the first supply voltage only until the first supply voltage reaches a specific voltage which is equal to or less than the reference voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when used for a device having a power supply detection circuit for generating a power-on signal, for example.

Examples of a semiconductor integrated circuit device provided with a power-on circuit include Japanese Unexamined Patent Application Publication Nos. 2002-042459 and 2001-210076. In Japanese Patent Laid-Open No. 2002-042459, a power-on detection circuit (determined by capacitive coupling or charging voltage by a capacitor and a resistor) is provided for any power supply voltage among a plurality of power supply voltages, and each of the circuits that operate at the power supply voltage Therefore, a power-on reset signal is generated. For the internal circuit using a different potential, the main power-on detection circuit generates another power-on reset signal while at least one of the previous power-on reset signals is in an active state (during reset). In Japanese Patent Laid-Open No. 2001-210076, an external power supply voltage is supplied instead of the internal power supply voltage during a period when the external power supply voltage is low. The period is defined by a power-on reset signal generated by a reset signal generation circuit (determined by the gate voltage of the MOSFET based on the voltage dividing ratio of the resistor).
JP 2002-042459 A JP 2001-210076

  LSIs with multiple power supply systems (Vint / Vext) with different potentials are more than an order of magnitude higher than the normal operating current of LSIs when power is turned on and off as a normal operation or when power supply is interrupted as an abnormal operation. A large through current is generated, and abnormal operation and heat generation, destruction of the LSI itself and characteristic deterioration often occur in the entire system on which the LSI is mounted. For example, as shown in FIG. 16, when a power supply voltage Vint is low in a circuit having a level shift circuit LS used for signal transmission between different potentials in an LSI and an output buffer OB that receives the output signal. A phenomenon occurs that a through current is generated in the level shift circuit LS itself and the output circuit OB because the internal state of the level shift circuit LS becomes unstable in potential. In order to avoid this phenomenon, it is necessary to fix the signal of the level shift circuit by a power-on reset signal generated inside or outside the LSI.

  When the reference voltage generation circuit is not used as in the above-mentioned Patent Document 1, the power supply reset signal is generated by detecting the rise and fall of the external power supply voltage (Vext) and the internal power supply voltage (Vint). In general, a circuit that uses a logic circuit (such as an inverter) that adjusts the logic threshold value, a circuit that uses a resistance voltage dividing ratio, or a circuit that simply uses the charge / discharge time of a capacitor. A device using a logic circuit (inverter or the like) having a logic threshold value constituted by CMOS generally adjusts a detection voltage, so that it is easily affected by variations in CMOS (3σ) and environmental temperature (Ta). As the detection level deviates from a voltage level of 1/2 of this, the detection accuracy becomes rough, and the power-on reset signal may be canceled with a voltage far from the voltage that is originally desired to be detected, causing a malfunction in the LSI.

  The resistor voltage dividing ratio is a static method for determining the voltage level, and it is easy to reliably generate a power-on reset signal. However, since a leak current always flows because of static operation, the current consumption is reduced. In many cases, however, an increase in area / mounting cost becomes a problem because a large resistance is required inside or outside the chip. Dynamic devices using simple charge / discharge times are often used in LSIs that aim to reduce current consumption because there is almost no leakage current. However, when the rise time of the power supply voltage is slow, There is a problem that the power-on reset state is released before reaching the power supply voltage at which the internal circuit can operate even if the process is terminated. In addition, this method generates a power-on reset signal without any problem when the power supply voltage rises from 0 V. However, if an instantaneous interruption of the power supply voltage occurs, the remaining charge remains in the capacitor that generates the time constant, so the reset pulse period There is a problem of causing a malfunction such as a case where the pulse becomes shorter or a pulse not generated at all.

  FIG. 17 shows a circuit diagram of a power-on reset circuit studied prior to the present invention. This power-on reset circuit forms a reference voltage Vbgr using the bandgap reference circuit 2 and detects the internal power supply voltage Vint by the voltage comparison circuit CMP. That is, when the internal power supply voltage Vint becomes higher than the reference voltage Vbgr, the output signal of the voltage comparison circuit CMP changes from low level to high level, and the reset signal rst is changed from high level to low level through the inverter circuit INV. The reset signal rst becomes a high level corresponding to the rise of the power supply voltage Vext, the output signal of the level shift circuit LS is forced to a fixed level, and a through current in the level shift circuit due to the low internal power supply voltage Vint and The generation of the through current in the output circuit OB due to the intermediate level of the output signal is prevented.

  The startup circuit 1 supplies the current to the MOSFET MN30 of the bandgap reference circuit 2 by turning on the P-channel MOSFET MP33 when the power supply voltage Vext rises. When a current flows through the MOSFET MN30, a current flows through the MOSFETs MN30, MN31, MP37, and MP36, and a current also flows through the MOSFETs MP35 and MP34, and the bandgap reference circuit 2 is activated.

  The reset signal rst becomes low level when the internal power supply voltage Vint becomes higher than the reference voltage Vbgr, and releases the reset state of the level shift circuit LS. As a result, the level shift circuit LS performs a level shift operation corresponding to the input signal in. When the power supply voltage Vext rises to a predetermined voltage, the start-up circuit 1 turns on the MOSFET MP33 because the on-resistance value of the MOSFET MP30 is smaller than the combined on-resistance value of the MOSFETs MP31 and 32. As a result, the startup circuit 1 is prevented from affecting the operating state of the bandgap reference circuit 2.

  When the bandgap reference circuit 5 is used as the power-on reset circuit shown in FIG. 17, if it is equal to or higher than the minimum operating voltage of the bandgap reference circuit 2 (for example, 2.5V with respect to the reference voltage Vbgr of 1.2V). Although the voltage can be judged with high accuracy, the power-on reset signal may not be generated because the reference voltage Vbgr is undefined below the minimum operating voltage. Further, since the resistors R2 and R3 and the bipolar transistors T1 to T3 are frequently used, the trade-off relationship between the self-consumption current and the area becomes a problem.

  An object of the present invention is to provide a semiconductor integrated circuit device provided with a highly accurate power supply detection circuit with low current consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor integrated circuit device includes a startup circuit that operates at the first power supply voltage, a self-biased constant current source, a reference voltage generation unit, and a voltage comparison circuit. In the self-bias type constant current source, a constant current corresponding to a differential voltage between a first transistor in a diode form and a second transistor having a smaller threshold voltage is generated by the first resistance element. Form. This constant current is passed through the first transistor via the second transistor and the current mirror circuit. The reference voltage generation unit forms a reference voltage by a second resistance element through which a constant current is formed by a current mirror circuit of the self-bias type constant current source and a third transistor in a current mirror form, and compares the voltage. Supply to the circuit. The voltage comparison circuit compares a second power supply voltage different from the reference voltage and the first power supply voltage to generate a power supply detection signal. The start-up circuit uses, as a self-biased constant current source, a start-up voltage that causes a start-up current to flow through the first transistor or the second transistor until the first power supply voltage reaches a predetermined voltage equal to or lower than the reference voltage. When the control voltage is supplied to the reference voltage generation unit so that the reference voltage becomes a voltage corresponding to the first power supply voltage, and the first power supply voltage reaches the predetermined voltage, The supply of the starting voltage to the self-bias type constant current source and the control voltage to the reference voltage generator is stopped.

  A highly accurate power supply detection circuit with low current consumption can be realized.

  FIG. 1 shows a circuit diagram of an embodiment of a power supply detection circuit according to the present invention. This embodiment is directed to a semiconductor integrated circuit device that operates with two different power supply voltages Vext and Vint. The power supply voltage Vext is not particularly limited, but is a voltage such as 3.3 V, and is an operating voltage of the input / output circuit I / O that exchanges signals with an external device of the semiconductor integrated circuit device. The power supply voltage Vint is not particularly limited, but is set to a voltage such as 1.5 V, which is an operating voltage of the internal circuit LOG of the semiconductor integrated circuit device. The input / output circuit I / O is provided with a level shift circuit LS. The Vint amplitude signal formed by the internal circuit LOG is converted into a Vext amplitude signal by the level shift circuit LS and output from the external terminal TEX through the output circuit OB. An input signal input from the external terminal TEX is taken into the input circuit IB, converted into a Vint amplitude signal by the level shift circuit LS, and transmitted to the internal circuit LOG. The input circuit IB may be provided with a level shift function.

  A power supply detection circuit VINTDET is provided to prevent generation of a through current in the level shift circuit LS and the output circuit OB. The power supply detection circuit VINTDET includes a startup circuit 1, a self-biased constant current source 2, a reference voltage generation unit 3, a voltage comparison circuit CMP, and an inverter circuit INV.

  The self-bias type constant current source 2 includes the following circuit. The N-channel MOSFETs MN3 and MN4 have a large threshold voltage when the current density of the N-channel MOSFET MN3 is made larger than that of MN4. The drain and gate of the MOSFET MN3 are connected to form a diode, and the circuit ground potential (VSS) is supplied to the source. The gates of the MOSFETs MN3 and MN4 are connected in common, and a resistor R1 is provided between the source and the ground potential (VSS) of the circuit. A constant voltage corresponding to the threshold voltage difference between the MOSFETs MN3 and MN4 is supplied to the resistor R1. The constant current flowing through the MOSFET MN4 is fed back to the MOSFET MN3 via P-channel MOSFETs MP8 and MN7 in the form of current mirrors. When the size ratios of the MOSFETs MP7 and MP8 are made equal to allow the same current to flow through the MOSFETs MN3 and MN4, the size of the MN4 is N times that of the MOSFET MN3. As a result, the current density of the MOSFETs MN3 and MN4 is set to N: 1.

  The self-bias type constant current source 2 has a circuit configuration in which the current mirror circuits of the P-channel MOSFETs MP7 and MP8 and the N-channel MOSFETs MN3 and MN4 are respectively stacked in one stage (for Vth), and are mirrors from the P-channel MOSFET side. The current is supplied to the node pbis, and the mirror current from the N-channel MOSFET side is supplied to another analog circuit (for example, the bias current of the OP amplifier) by the bias terminal of the node nbis.

  The self-bias type constant current source 2 is connected to the startup circuit 1. Since the self-bias type constant current source 2 has two stable states in which the current mirror is turned on or off even when the external power supply voltage Vext reaches an operable power supply voltage, the startup circuit 1 is necessarily required. . In the startup circuit 1, current mirror MOSFETs MP1 and MN1 that have received bias terminals (pbis and nbis) from a self-biased constant current source are connected to diode-connected MOSFETs MP2, MP3, MP4, and MP5, respectively. When the external power supply voltage Vext is 0V, the MOSFETs MP2, MP3, MP4, and MP5, which are diode-connected to the current mirror MOSFETs MP1 and MN1 of the startup circuit 1, are also turned off.

  As the external power supply voltage Vext increases, the gate potential of the current injection MOSFET MP6 is low even if the current mirror MOSFET MP1 is off, so that the current injection MOSFET MP6 is turned on and the potential of the node nbis is increased to the external power supply voltage Vext. Although the current mirror MOSFET MN1 is also turned off, the diode-connected MOSFETs MP4 and MP5 are turned on as the external power supply voltage Vext rises, so that the gate potential of the current injection MOSFET MN2 rises and the potential of the node pbis falls to the ground potential VSS (0V). . Therefore, the self-bias type constant current source 2 is activated.

  When the external power supply voltage Vext further increases, the current mirror MOSFETs MP1 and MN1 are turned on, so that the current injection MOSFETs MP6 and MN2 are turned off. The constants of the current mirror MOSFETs MP1 and MN1 are determined so that the W / L (size) ratio is larger than that of the diode-connected MOSFETs MP2 and MP3 and MP4 and MP5.

  A reference voltage generator 3 is provided for such a self-biased constant current source 2. A circuit in which a MOSFET (diode-connected P-channel MOSFET) MP12 that operates in a saturation region and a MOSFET (P-channel MOSFET in which the gate potential is fixed to the ground potential VSS so as to be always on) MP10 and MP11 are vertically stacked. By passing a constant current formed by the self-bias type constant current source 2 through the current mirror MOSFET MP9, the positive polarity of the MOSFET MP10 and MP11 operating linearly with the gate-source voltage Vgs of the MOSFET MP12 operating in the saturation region and having a negative temperature characteristic. The voltage Vgs between the gate and the source having the temperature characteristics cancels each other, and a reference voltage Vthref (about 1.0 to 1.2 V) having a relatively flat temperature dependence is generated.

  The voltage comparison circuit CMP compares the reference voltage Vthref and the internal power supply voltage Vint to form an output signal. This comparison output signal is amplified by the inverter circuit INV to generate a power-on reset signal rst, which is transmitted to the input / output circuit I / O, forcing the output signal of the level shift circuit LS to prevent a through current. As will be described later, the through-current in the level shift circuit LS due to the low internal power supply voltage Vint and the through-current in the output circuit OB due to the intermediate level of the output signal are prevented.

  FIG. 2 is a characteristic diagram for explaining the operation of the power supply detection circuit of FIG. When the external power supply voltage Vext is low, the start-up circuit 1 of the self-bias type constant current source 2 lowers the bias terminal pbis to the ground potential VSS, so that the current mirror MOSFET MP9 of the reference voltage generator 3 operates in the linear region, so that the reference voltage Vthref Rises to near the external power supply voltage Vext. Therefore, in the voltage range A until the reference voltage Vthref reaches a normal voltage (about 1.0 V to 1.2 V), if the internal power supply voltage Vint is less than or equal to the external power supply voltage Vext, the output of the voltage comparison circuit CMP is There is no inversion. Therefore, the level shift circuit LS remains fixed by the reset signal rst. On the other hand, after the reference voltage Vthref reaches a normal voltage (about 1.0 V to 1.2 V), the voltage comparison circuit is used when the internal power supply voltage Vint crosses the reference voltage Vthref as in the voltage range B. The output of CMP is inverted to a high level, the reset signal rst that has passed through the inverter circuit INV is released to a low level, and the level shift circuit LS can operate normally. Note that a reference voltage Vbgr corresponding to the band gap reference circuit 2 of FIG. 17 is shown for comparison.

  FIG. 3 is a circuit diagram showing another embodiment of the power supply detection circuit according to the present invention. In this embodiment, the internal circuit LOG, the input circuit IB of the input / output circuit I / O, and the external terminal TEX are omitted. The reference voltage generation unit 3 that generates the reference voltage Vthref is configured by MOSFETs MP10 and MP11 that linearly operate with two PMOS-side and NMOS-side current mirror MOSFETs MP9 and MN5. The MOSFET MN5 is replaced by the diode-type P-channel MOSFET MP12, and the basic operation is similar to that of the embodiment of FIG.

  FIG. 4 is a circuit diagram showing another embodiment of the power supply detection circuit according to the present invention. In this embodiment, as in FIG. 3, the internal circuit LOG, the input circuit IB of the input / output circuit I / O, and the external terminal TEX are omitted. The reference voltage generator 3 for generating the reference voltage Vthref is formed of a current mirror MOSFET MN5 on the NMOS side similar to FIG. In this embodiment, the MOSFET MP12 that operates in the diode-connected saturation region is deleted from the current path that generates the reference voltage Vthref, and is configured by the MOSFET MOSFETMP10 and MP11 that operate linearly with the NMOS current mirror MOSFET MN5 similar to FIG. is there. In the voltage range A until the reference voltage Vthref reaches a normal voltage (approximately 1.0 V to 1.2 V), and until the node nbis becomes constant, the gate is supplied with the circuit ground potential P As described above, the reference voltage Vthref rises from the channel MOSFET MP9 to near the external power supply voltage Vext. As described above, the basic operation is similar to that shown in FIGS.

  FIG. 5 shows a circuit diagram of still another embodiment of the power supply detection circuit according to the present invention. Unlike the embodiment shown in FIGS. 1 and 3, the power supply detection circuit of this embodiment detects an external power supply voltage. Also in the drawing, the internal circuit LOG, the input circuit IB of the input / output circuit I / O, and the external terminal TEX are omitted in the same manner as described above. The power supply voltage detection circuit VEXTDET of this embodiment includes a self-bias type constant current source 2 having a startup circuit 1 similar to the above, a voltage comparison circuit CMP, and an inverter circuit INV. That is, the reference voltage generator 3 shown in FIGS. 1 and 3 is not provided.

  As described in the description of the operation of the embodiment, when the external power supply voltage (Vext) is 0 V, the current mirror MOSFETs MP1 and MN1 of the startup circuit 1 and the diode-connected MOSFETs MP2, MP3 and MP4 and MP5 are also turned off. . As the external power supply voltage Vext rises, even if the current mirror MOSFET MP1 is off, the gate potential of the current injection MOSFET MP6 is low, so that the current injection MOSFET MP6 is turned on and the potential of the node nbis rises to the external power supply voltage Vext. Although the current mirror MOSFET MN1 is also off, the diode-connected MOSFETs MP4 and MP5 are turned on as the external power supply voltage Vext rises, so that the gate potential of the current injection MOSFET MN2 rises and the potential of the node pbis falls to the circuit ground potential VSS. Therefore, the self-bias type constant current source 2 is activated.

  When the external power supply voltage Vext is further increased, the current mirror MOSFETs MP1 and MN1 are turned on so that the current injection MOSFETs MP6 and MN2 are turned off. Therefore, as shown in the characteristic diagram of FIG. 6, there is always a cross point between the nodes pbis and nbis, which is almost the same as the sum 2Vth of the threshold values of the P-channel MOSFET and the N-channel MOSFET operating at the external power supply voltage Vext. It is. By comparing this cross point with the voltage comparison circuit CMP, the power-on reset signal rst is generated through the inverter circuit INV as described above. That is, when the external power supply voltage Vext becomes higher than the cross point, the output signal of the voltage comparison circuit CMP becomes high level, and similarly, the output signal of the inverter circuit INV becomes low level and the power-on reset signal rst becomes low level. Release the reset state.

  FIG. 7 shows a circuit diagram of still another embodiment of the power supply detection circuit according to the present invention. In this embodiment, an external power supply voltage detection circuit VEXTDET is configured by applying the power supply voltage detection circuit VINTDET of FIG. In other words, the input voltage input to the voltage comparison circuit CMP in FIG. 1 is a voltage dividing circuit constituted by diode-connected P-channel MOSFETs MP13, MP14, MP15, and MP16 instead of the internal power supply voltage Vint in FIG. A reference voltage Vthref having a relatively flat temperature dependency formed by the reference voltage generating unit 3 by forming a divided voltage Vext / n obtained by dividing the external power supply voltage Vext (around 1.0V to 1.2V) To detect the rise and fall of the external power supply voltage Vext and generate the power-on reset signal rst. The external power supply voltage Vext to be detected is set according to the relationship between the reference voltage Vthref and the divided voltage Vext / n.

  FIG. 8 is a schematic block diagram showing an embodiment of the semiconductor integrated circuit device according to the present invention. An external power supply voltage detection circuit VEXTDET and an internal power supply voltage detection circuit VINTDET are mounted on a semiconductor integrated circuit device LSI having an external power supply voltage Vext and an internal power supply voltage Vint that are different potentials. The external power supply voltage detection circuit VEXTDET is configured by a circuit as shown in FIG. 5 or FIG. The internal power supply voltage detection circuit VINTDET is constituted by a circuit as shown in FIG. 1, FIG. 3 or FIG.

  An input / output circuit IOB is arranged along the outer periphery of the chip of the semiconductor integrated circuit device LSI. The input / output circuit IOB operates with the external power supply voltage Vext. Inside the semiconductor integrated circuit device LSI, a central processing unit (microprocessor or control logic circuit) CPU and a memory RAM are provided as internal circuits. These CPU and RAM are made to operate at the internal power supply voltage Vint. The circuit area that operates with these internal power supply voltages Vint is indicated by hatching. The signal S4 between the CPU and RAM is set to a signal level corresponding to the internal power supply voltage Vint. Signal exchange between the RAM and the input / output circuit IOB is performed through the level shift circuit LS1.

  The RAM side signal S0 is transmitted through the level shift circuit LS1 after converting the signal amplitude corresponding to the internal power supply voltage Vint to the signal amplitude S1 corresponding to the external power supply voltage Vext. Conversely, the signal S1 on the input / output circuit IOB side is transmitted through the level shift circuit LS1 after being converted into a signal amplitude S0 corresponding to the internal power supply voltage Vint. Similarly, the CPU side signal S2 is transmitted through the level shift circuit LS2 by converting the signal amplitude corresponding to the internal power supply voltage Vint to the signal amplitude S3 corresponding to the external power supply voltage Vext. Conversely, the signal S3 on the input / output circuit IOB side is transmitted after being converted into a signal amplitude S2 corresponding to the internal power supply voltage Vint through the level shift circuit LS2. The level shift circuits LS1 and LS2 are operated by the internal power supply voltage Vint and the external power supply voltage Vext. The level shift circuits LS1 and LS2 and the input / output circuit IOB constitute the input / output circuit I / O.

  The external power supply voltage detection circuit VEXTDET is placed in a region where a circuit operating with the external power supply voltage Vext of the semiconductor integrated circuit device LSI is arranged, and the internal power supply voltage detection circuit VINTDET is placed with a circuit operating with the internal power supply voltage Vint. Placed in the area. A circuit for supplying the power-on reset signal rst formed by processing these output signals rst-in and rst-ex with control logic (OR circuit or the like) to the level shift circuit LS so that the indefinite level does not occur. Used to fix the node.

  FIG. 9 is a waveform diagram for explaining the operation of the semiconductor integrated circuit device of FIG. The external power supply voltage Vext is set to 3.3V, for example, and the internal power supply voltage Vint is set to 1.5V, for example. In this example, the reset signal rst is at a high level until the reference voltage Vthref such as about 1.0 reaches the internal power supply voltage Vint, and the circuit nodes of the level shift circuits LS1 and LS2 do not become the indefinite level. Generation of a through current is prevented by setting to a fixed level.

  FIG. 10 is a waveform diagram for explaining another operation of the semiconductor integrated circuit device of FIG. In the semiconductor integrated circuit device of FIG. 8, an external power supply voltage detection circuit VEXTDET and an internal power supply voltage Vint are provided. Therefore, the external power supply voltage Vext decreases due to the instantaneous power interruption that occurs as an abnormal operation during the time period indicated by a in the figure, but the internal power supply voltage Vint remains unchanged due to the effect of stabilization or parasitic capacitance. Even when maintained, since the external power supply voltage detection circuit VEXTDET forms the detection signal rst-ex in response to the decrease in the external power supply voltage Vext, the power-on reset signal rst is formed through the control logic, and the level shift circuits LS1, LS1,. LS2 can be fixed.

  FIG. 11 is a schematic block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, an external power supply voltage detection circuit VEXTDET and an internal power supply are added to a semiconductor integrated circuit device LSI having an external power supply voltage Vext having a different potential, an internal power supply voltage Vint2 for the CPU, and an internal power supply voltage Vint1 for the memory RAM. A voltage detection circuit VINTDET1 and an internal power supply voltage detection circuit VINTDET2 are provided. In this embodiment, the internal power supply voltage Vint1 for the memory RAM and the internal power supply voltage Vint2 for the CPU are supplied independently. In response to this, two internal power supply voltage detection circuits VINTDET1 and 2 are provided as described above. This semiconductor integrated circuit device LSI has an internal power supply cutoff function, for example, and stops supply of the internal power supply voltage Vint2 in order to suppress the leakage current of the CPU during standby. On the other hand, only the internal power supply voltage Vint1 can be supplied for data retention. When the internal power supply voltage Vint2 is cut off, the signal between the RAM and the CPU becomes indefinite, so that the signal is fixed to a desired signal level by the clinching circuit.

  The external power supply voltage detection circuit VEXTTDET is placed in a region where a circuit that operates with the external power supply voltage Vext of the semiconductor integrated circuit device LSI is disposed, and the internal power supply voltage detection circuit VINTDET2 is a circuit that operates with the internal power supply voltage Vint2 for the CPU. Is placed in the area where it is placed. The internal power supply voltage detection circuit VINTDET1 is placed in a region where a circuit operating with the internal power supply voltage Vint1 for RAM is arranged. The output signals rst-ex and rst-in1 and rst-in2 of the external power supply voltage detection circuit VEXTDET and internal power supply voltage detection circuits VINTDET1 and 2 are logically processed by control logic (OR circuit or the like) to generate a power-on reset signal rst. It is formed and used for fixing to level shift circuits LS1 and LS2 and fixing an indefinite level of the clinch circuit.

  FIG. 12 is a waveform diagram for explaining the operation of the semiconductor integrated circuit device of FIG. When the supply of the internal power supply voltage Vint2 is stopped to suppress the leakage current of the CPU during standby, the reset signal rst is formed based on the output signal rst-in2 formed by the internal power supply voltage detection circuit VINTDET2. As a result, the reset signal rst is formed when the power supply voltage Vint2 of only the CPU is cut off and when it is turned on again, and the level shift circuits LS1 and LS2 are fixed and the indefinite level of the clinch circuit is fixed.

  FIG. 13 is a waveform diagram for explaining another operation of the semiconductor integrated circuit device of FIG. The external power supply voltage Vext decreases due to the instantaneous power interruption that occurs as an abnormal operation during the time period indicated by a in the figure, but the internal power supply voltages Vint1 and Vint2 remain unchanged due to stabilization or parasitic capacitance. Even when maintained, since the external power supply voltage detection circuit VEXTDET forms the detection signal rst-ex in response to the decrease in the external power supply voltage Vext, the power-on reset signal rst is formed through the control logic, and the level shift circuits LS1, LS1,. LS2 can be fixed.

  FIG. 14 is a circuit diagram showing one embodiment of the level shift circuit LS and the output circuit OB used in the semiconductor integrated circuit device according to the present invention. The level shift circuit LS includes a circuit portion that operates with the external power supply voltage Vext and a circuit portion that operates with the internal power supply voltage Vint. The circuit portion operating at the internal power supply voltage Vint is a CMOS inverter circuit comprising a P-channel MOSFET MP26 and an N-channel MOSFET MN24 operating at Vint. The CMOS inverter circuits (MP26, MN24) form an inverted signal of the Vint level input signal in. Therefore, if there is an inverted signal of the input signal in in the internal circuit for forming the input signal in of Vint level, it can be omitted.

  The input signal in is supplied to the gates of the P-channel MOSFET MP20 and the N-channel MOSFET MN20. The ground potential of the circuit is supplied to the source of the N-channel MOSFET MN20. A P-channel MOSFET MP21 is provided between the source of the P-channel MOSFET MP20 and the external power supply voltage Vext. The input signal in is inverted by the CMOS inverter circuit and supplied to the gates of the P-channel MOSFET MP22 and the N-channel MOSFET MN22. The ground potential of the circuit is supplied to the source of the N-channel MOSFET MN22. A P-channel MOSFET MP23 is provided between the source of the P-channel MOSFET MP22 and the external power supply voltage Vext. The gate of the P-channel MOSFET MP21 is connected to the drains of the MOSFETs MP22 and MN22, and the gate of the P-channel MOSFET MP23 is connected to the drains of the MOSFETs MP20 and MN20 to constitute a latch circuit.

  An N-channel MOSFET MN21 is provided between the gate of the P-channel MOSFET MP23, which is one input / output of the latch circuit, a connection node between the P-channel MOSFET MP20 and the drain of the N-channel MOSFET MN20, and the ground potential of the circuit. Further, a P-channel MOSFET MN24 is provided between the gate of the P-channel MOSFET MP21 which is the other input / output of the latch circuit, a connection node between the P-channel MOSFET MP22 and the drain of the N-channel MOSFET MN22, and the external power supply voltage Vext. The power-on reset signal rst is transmitted to the gate of the N-channel MOSFET MN21. The power-on reset signal rst is inverted through the inverter circuit INV1 and transmitted to the gate of the P-channel MOSFET MP24.

  The output circuit OB is configured by the following circuit. A complementary signal is formed by the inverter circuit INV2 that receives the output signal LSout of the level shift circuit and the inverter circuit INV3 that inverts the output signal. The output signal of the inverter circuit INV2 is transmitted to the gate of the N-channel output MOSFET MN23 through the inverter circuit INV5 as a drive circuit. The output signal of the inverter circuit INV3 is transmitted to the gate of the P-channel output MOSFET MP25 through the inverter circuit INV4 as a drive circuit. The source of the output MOSFET MP23 is given a circuit ground potential, and the drain is connected to a pad PAD connected to the external terminal TEX. The source of the output MOSFET MP25 is supplied with an external power supply voltage Vext, and the drain is connected to a pad PAD connected to the external terminal TEX.

  The MOSFETs constituting the level shift circuit LS and the output circuit OB are high breakdown voltage MOSFETs corresponding to the external power supply voltage Vext except for the P-channel MOSFET MP26 and the N-channel MOSFET MN24 operating with the internal power supply voltage Vint.

  In this embodiment, when the potential of the input signal in is indefinite, the reset signal rst is set to a high level by the external power supply voltage detection circuit VEXTDET or the internal power supply voltage detection circuit VINTDET, the MOSFET MN21 is turned on and the P-channel MOSFET MP23 is turned on. To do. Further, in response to the high level of the reset signal rst, the output signal of the inverter circuit (MP26, MN24) becomes low level, and the P-channel MOSFET MP24 is turned on and the P-channel MOSFET MP21 is turned off. As a result, the output signal LSout of the level shift circuit LS is fixed at a high level corresponding to the external power supply voltage Vext, and an intermediate level is not supplied to the output circuit OB, and the level shift circuit LS itself and the output circuit IB The through current as shown in FIG. 16 can be prevented.

  FIG. 15 is a circuit diagram showing one embodiment of a power supply voltage detection circuit used in the semiconductor integrated circuit device according to the present invention. This figure shows a specific circuit of the voltage comparison circuit CMP corresponding to FIG. This voltage comparison circuit CMP can be used as a voltage comparison circuit of another power supply voltage detection circuit VINTDET or an operational amplifier formed in a semiconductor integrated circuit device.

  An N-channel MOSFET MN10 is provided as a current source that generates an operating current between the common source of the differential N-channel MOSFETs MN6 and MN7 and the ground potential of the circuit. The gate of the MOSFET MN10 is supplied with the node nbis of the self-bias type constant current source 2 to be a current mirror. A current mirror circuit composed of P-channel MOSFETs MP20 and MP21 is provided between the drain of the one differential MOSFET MN6 and the power supply voltage Vext. A current mirror circuit composed of N-channel MOSFETs MN8 and MN9 is provided between the drain of the MOSFET M21 and the ground potential of the circuit. A current mirror circuit composed of P-channel MOSFETs MP22 and MP23 is provided between the drain of the other differential MOSFET MN7 and the power supply voltage Vext. The drain of the P-channel MOSFET MP23 and the drain of the N-channel MOSFET MN9 are connected to form an output signal capable of full amplitude up to the power supply voltage Vext and the ground potential of the circuit. This output signal is inverted through the inverter circuit INV to form the power-on reset signal rst.

  It is possible to prevent a through current from being generated inside the semiconductor integrated circuit device LSI when the power is turned on and off as a normal operation or when the power supply is interrupted as an abnormal operation. In order to prevent all such through currents, the voltage level 2Vth determined by the transition of the internal state of the logic circuit or the like operating at the internal power supply voltage Vint on the input side of the level shift circuit LS from the saturation region to the linear region. It operates with the external power supply voltage Vext on the output side of the level shift circuit LS from a voltage level higher than −in (sum of threshold voltages of CMOS N-channel MOSFET or P-channel MOSFET: about 0.4 V, for example) Voltage level 2Vth-ex determined by transition of the internal state of the logic circuit or the like from the saturation region to the linear region (sum of threshold voltages of N channel MOSFET and P channel MOSFET of CMOS for IOB circuit: 8V) The output of the level shifter may be fixed with the power-on reset signal rst until an abnormality occurs.

  The internal power supply voltage detection circuit VINTDET of the above embodiment compares the internal power supply voltage Vint with a reference voltage Vthref (for example, about 1.0 V) having a voltage level of 2Vth-in and 2Vth-ex or higher and a power-on reset. A signal rst is generated. In other words, the reference voltage generator 3 uses a constant current mirrored from a self-bias type constant current source 3 in which current mirror circuits of P-channel MOSFETs MP7 and MP8 and N-channel MOSFETs MN3 and MN4 are stacked in one stage (Vth). A reference voltage Vthref having a relatively flat temperature dependency (about 1.0 V to 1.2 V) is generated and compared with the internal power supply voltage Vint. When the power supply voltage Vext is equal to or higher than the reference voltage Vthref, normal operation is always possible. When the power supply voltage Vext is equal to or lower than the reference voltage Vthref, the characteristics of the startup circuit 1 of the self-bias type constant current source 2 are used. By setting Vext, the voltage comparison circuit CMP can determine that the internal power supply voltage Vint has not risen, and the power-on reset signal rst can be reliably formed.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the internal power supply voltage Vint may be a voltage obtained by internally reducing the external power supply voltage Vext in addition to being supplied from an external terminal. The reference voltage Vthref may be used to form this step-down voltage. The power-on reset signal rst is widely used as a power supply voltage detection signal such as a signal that prevents a through current due to the internal indefinite level, and an initial value of an internal circuit, for example, an initial value of a register or a latch circuit. it can. The present invention can be widely used for a semiconductor integrated circuit device (eg, microcomputer, system LSI, etc.) having a power supply voltage detection circuit.

1 is a circuit diagram showing an embodiment of a power supply detection circuit according to the present invention. FIG. FIG. 2 is a characteristic diagram for explaining the operation of the power supply detection circuit of FIG. 1. It is a circuit diagram which shows another Example of the power supply detection circuit based on this invention. It is a circuit diagram which shows another Example of the power supply detection circuit based on this invention. It is a circuit diagram which shows another Example of the power supply detection circuit based on this invention. FIG. 6 is a characteristic diagram for explaining the operation of the power supply detection circuit of FIG. 5. It is a circuit diagram which shows another Example of the power supply detection circuit based on this invention. 1 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 9 is a waveform diagram for explaining the operation of the semiconductor integrated circuit device of FIG. 8. FIG. 9 is a waveform diagram for explaining another operation of the semiconductor integrated circuit device of FIG. 8. It is a schematic block diagram which shows another Example of the semiconductor integrated circuit device based on this invention. 12 is a waveform diagram for explaining the operation of the semiconductor integrated circuit device of FIG. FIG. 12 is a waveform diagram for explaining another operation of the semiconductor integrated circuit device of FIG. 11. 2 is a circuit diagram showing one embodiment of a level shift circuit LS and an output circuit OB used in the semiconductor integrated circuit device according to the present invention. FIG. 1 is a specific circuit diagram showing an embodiment of a power supply voltage detection circuit used in a semiconductor integrated circuit device according to the present invention. FIG. 3 is a circuit diagram of a level shift circuit LS and an output circuit OB studied prior to the present invention. It is a circuit diagram of the power-on reset circuit examined prior to the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Startup circuit, 2 ... Self-bias type constant current source, 3 ... Reference voltage generation part, 4 ... Voltage divider circuit, 5 ... Band gap reference circuit, LS ... Level shift circuit, OB ... Output circuit, IOB ... Input / output Circuit, I / O ... Input / output circuit, CMP ... Voltage comparison circuit, INV, INV1-INV5 ... Inverter circuit, MP1-MP39 ... P-channel MOSFET, MN1-MN31 ... N-channel MOSFET, T1-T3 ... Bipolar transistor, VINTDET ... Internal power supply voltage detection circuit, VEXTDET ... external power supply voltage detection circuit, RAM ... memory, CPU ... central processing unit, LOG ... internal circuit, TEX ... external terminal.

Claims (12)

A first circuit operating at a first power supply voltage;
A second circuit operating at a second power supply voltage lower than the first power supply voltage;
A startup circuit operating at the first power supply voltage;
A self-biased constant current source operating at the first power supply voltage;
A reference voltage generator that operates with the first power supply voltage and forms a reference voltage using a constant current formed by the self-bias type constant current source;
A voltage comparison circuit that operates at the first power supply voltage and receives the reference voltage and a voltage corresponding to the second power supply voltage to form a power supply detection signal;
The self-biased constant current source is
A first transistor in the form of a diode;
A second transistor having a threshold voltage lower than that of the first transistor;
A current mirror circuit for receiving a current flowing through the second transistor and forming a current flowing through the first transistor;
A first resistance element that causes a constant current corresponding to a voltage difference between threshold voltages of the first transistor and the second transistor to flow through the second transistor;
The reference voltage generator is
A current mirror circuit of the self-bias type constant current source and a third transistor in the form of a current mirror;
A second resistance element that is supplied with a constant current of the third transistor and forms the reference voltage;
The startup circuit is
Supplying a starting voltage to the self-bias type constant current source so that a starting current flows in the first transistor or the second transistor until the first power supply voltage reaches a predetermined voltage equal to or lower than the reference voltage; Supplying a control voltage such that the reference voltage is a voltage corresponding to the first power supply voltage to the reference voltage generator;
When the first power supply voltage reaches the predetermined voltage, the semiconductor integrated circuit device stops supplying the start-up voltage to the self-bias type constant current source and the control voltage to the reference voltage generation unit. In claim 1,
A semiconductor integrated circuit device using a band gap voltage corresponding to a current density ratio of currents flowing through the first transistor and the second transistor as a difference voltage between threshold voltages of the first transistor and the second transistor. In claim 2,
The first to third transistors are MOSFETs,
The second resistance element is a semiconductor integrated circuit device including a series circuit of a MOSFET that operates linearly and a MOSFET that performs saturation operation. In claim 3,
The current mirror circuit is composed of a P-channel MOSFET,
The first and second transistors are N-channel MOSFETs,
The three transistors are P-channel MOSFETs whose gates and drains are commonly connected to the output-side P-channel MOSFET of the current mirror circuit,
The linearly operating MOSFET is a P-channel MOSFET in which the circuit ground potential is supplied to the gate and the reference voltage is supplied to the substrate gate,
The MOSFET that performs the saturation operation is a P-channel MOSFET in which a circuit ground potential is supplied to a gate and a drain. In claim 3,
The current mirror circuit is composed of a P-channel MOSFET,
The first and second transistors are N-channel MOSFETs,
The three transistors are N-channel MOSFETs in the form of a current mirror with the first transistor,
The linearly operating MOSFET is a P-channel MOSFET in which the circuit ground potential is supplied to the gate and the reference voltage is supplied to the substrate gate,
The saturation operation MOSFET is a semiconductor integrated circuit device which is a P-channel MOSFET in which a circuit ground potential is supplied to a gate and the first power supply voltage is supplied to a source. In claim 5,
The first circuit includes:
A level conversion circuit that receives a signal formed by the second circuit and converts the signal to a signal amplitude corresponding to the first power supply voltage; and an output circuit that outputs an output signal of the level conversion circuit to an external terminal. ,
The voltage detection signal is a semiconductor integrated circuit device that turns on a MOSFET that fixes the output signal of the level conversion circuit to the first power supply voltage or the ground potential of the circuit. A startup circuit operating at the first power supply voltage;
A self-biased constant current source operating at the first power supply voltage;
A voltage comparison circuit that operates at the first power supply voltage to form a power supply detection signal;
The self-biased constant current source is
A first transistor in the form of a diode;
A second transistor having a threshold voltage lower than that of the first transistor;
A current mirror circuit for receiving a current flowing through the second transistor and forming a current flowing through the first transistor;
A first resistance element that causes a constant current corresponding to a voltage difference between threshold voltages of the first transistor and the second transistor to flow through the second transistor;
The voltage comparison circuit
A differential amplifier circuit having a constant current formed by the self-bias type constant current source as an operating current;
The differential input of the differential amplifier circuit is supplied with a bias voltage supplied to the current mirror circuit and a bias voltage supplied to the first transistor,
The startup circuit is
Supplying a starting voltage such that a starting current flows through the first transistor or the second transistor until the first power supply voltage reaches a predetermined voltage, to the self-bias type constant current source;
A semiconductor integrated circuit device that stops supplying the start-up voltage to the self-biased constant current source when the first power supply voltage reaches a predetermined voltage.
In claim 5, In claim 7,
A semiconductor integrated circuit device using a band gap voltage corresponding to a current density ratio of currents flowing through the first transistor and the second transistor as a difference voltage between threshold voltages of the first transistor and the second transistor. In claim 8,
A semiconductor integrated circuit device in which the current mirror circuit and the first and second transistors are MOSFETs. A startup circuit operating at the first power supply voltage;
A self-biased constant current source operating at the first power supply voltage;
A reference voltage generator that operates with the first power supply voltage and forms a reference voltage using a constant current formed by the self-bias type constant current source;
A voltage comparison circuit that operates at the first power supply voltage and that receives the reference voltage and the divided voltage of the first power supply voltage to form a power supply detection signal;
The self-biased constant current source is
A first transistor in the form of a diode;
A second transistor having a threshold voltage lower than that of the first transistor;
A current mirror circuit for receiving a current flowing through the second transistor and forming a current flowing through the first transistor;
A first resistance element that causes a constant current corresponding to a voltage difference between threshold voltages of the first transistor and the second transistor to flow through the second transistor;
The reference voltage generator is
A current mirror circuit of the self-bias type constant current source and a third transistor in the form of a current mirror;
A second resistance element that is supplied with a constant current of the third transistor and forms the reference voltage;
The startup circuit is
Supplying a starting voltage to the self-bias type constant current source so that a starting current flows in the first transistor or the second transistor until the first power supply voltage reaches a predetermined voltage equal to or lower than the reference voltage; Supplying a control voltage such that the reference voltage is a voltage corresponding to the first power supply voltage to the reference voltage generator;
When the first power supply voltage reaches the predetermined voltage, the semiconductor integrated circuit device stops the supply of the starting voltage to the self-bias type constant current source and the control voltage to the reference voltage generator. In claim 10,
A semiconductor integrated circuit device using a band gap voltage corresponding to a current density ratio of currents flowing through the first transistor and the second transistor as a difference voltage between threshold voltages of the first transistor and the second transistor. In claim 11,
A semiconductor integrated circuit device in which the current mirror circuit and the first to third transistors are MOSFETs.

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