JP2018170689A - Semiconductor device and power-on reset device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device capable of generating a power-on reset signal, ensuring power-on reset of the internal circuit, even if there are manufacturing variations, and to provide a power-on reset device.CONSTITUTION: A semiconductor device has a regulator receiving a reference voltage, and generating a constant power supply voltage having a voltage value corresponding to the reference voltage in response to power-up, and a power-on reset circuit generating a power-on reset signal, having a first voltage value for prompting reset from the moment in time of power-up over a prescribed period, and transiting to a second voltage value for prompting reset release upon elapsing a prescribed period from the moment in time of power-up, on the basis of the reference voltage and the constant power supply voltage. The power-on reset circuit includes a drive node, a current difference acquisition part for supplying a first current corresponding to the voltage value of the reference voltage to the drive node, and extracting a second current corresponding to the constant power supply voltage from the drive node, and a comparator for obtaining a power-on reset signal based on the comparison result of the voltage value of the drive node and a prescribed threshold level.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device, in particular, a semiconductor device including a power-on reset circuit that resets an internal circuit in response to power-on, and a power-on reset device.

  The semiconductor device is provided with a power-on reset circuit that initializes the state of the internal circuit when the power is turned on. As such a power-on reset circuit, it has a voltage value that prompts resetting immediately after power-on based on the comparison result between the voltage for comparison that divided the power supply voltage and the monitored voltage generated by the regulator. There has been proposed one that generates a voltage that transitions to a voltage value that prompts release (see, for example, Patent Document 1).

  The power-on reset circuit outputs a differential pair that receives the comparison voltage and the monitored voltage, and a voltage that prompts the reset or reset release based on a current flowing through the differential pair by the monitored voltage. And a generation circuit for generating a bias current flowing through the differential pair and the output circuit.

Japanese Patent Laid-Open No. 2006-127480

  By the way, in the above configuration, the threshold voltage Vt of the transistors constituting the differential pair may fluctuate due to manufacturing variations. At this time, it may be difficult to set a voltage value that prompts reset (or a voltage value that prompts reset release) to a desired voltage value, and power-on reset (or reset release) may not be performed on the internal circuit. there were.

  Therefore, the present invention provides a semiconductor device including a power-on reset circuit and a power-on reset device that can reliably perform a power-on reset to an internal circuit even when manufacturing variations occur. Objective.

  A semiconductor device according to the present invention receives a reference voltage, generates a constant power supply voltage having a voltage value corresponding to the reference voltage when the power is turned on, and powers on based on the reference voltage and the constant power supply voltage. A power-on reset that generates a power-on reset signal that has a first voltage value that prompts resetting for a predetermined period from the time point, and that transitions to a second voltage value that prompts reset release after the elapse of the predetermined period from the power-on time point The power-on reset circuit supplies a first current corresponding to a voltage value of the reference voltage to the drive node, and a second current corresponding to the constant power supply voltage. The power-on reset signal is obtained based on a current difference acquisition unit that draws current from the drive node and a comparison result between the voltage value of the drive node and a predetermined threshold value. It includes a comparator, a.

  The power-on reset device according to the present invention has a first voltage value that prompts resetting for a predetermined period from the time of power-on, and has a second voltage value that prompts reset release after the elapse of the predetermined period from the time of power-on. A power-on reset device that generates a power-on reset signal that transitions, a regulator that receives a reference voltage and generates a constant power supply voltage having a voltage value corresponding to the reference voltage when power is turned on, a drive node, A current difference acquisition unit that supplies a first current corresponding to the voltage value of the reference voltage to the drive node and extracts a second current corresponding to the constant power supply voltage from the drive node; and a voltage of the drive node A comparator that obtains the power-on reset signal based on a comparison result between the value and a predetermined threshold value.

  In the present invention, a first current corresponding to the reference voltage received by a regulator that generates a constant power supply voltage having a voltage value corresponding to the reference voltage when the power is turned on, a second current corresponding to the constant power supply voltage, , Generate. Then, a power-on reset signal is generated based on the difference between the currents obtained by subtracting the second current corresponding to the constant power supply voltage from the first current corresponding to the reference voltage. According to such a difference in current, since the variation due to the manufacturing variation occurring in the first current and the second current is offset, the voltage value that prompts the reset even if the variation occurs. Therefore, it is possible to reliably obtain a power-on reset signal that makes a transition from the current state to the state of the voltage value that prompts the reset release.

1 is a block diagram showing a configuration of a semiconductor device 100 according to the present invention. 2 is a circuit diagram showing an example of internal configurations of a regulator 12 and a power-on reset circuit 13. FIG. It is a time chart which shows an example of the waveform of constant power supply voltage VDC and the power-on reset signal POR at the time of power activation. 6 is a circuit diagram showing another example of the internal configuration of the regulator 12 and the power-on reset circuit 13. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to the present invention. As shown in FIG. 1, the semiconductor device 100 includes an internal circuit 10 that performs the main function as the semiconductor device, a reference voltage generation unit 11, a regulator 12, and a power-on reset circuit 13.

  The reference voltage generator 11 generates a reference voltage VR having a predetermined constant voltage value based on the power supply potential VDD and supplies the reference voltage VR to the regulator 12.

  The regulator 12 uses a constant power supply voltage VDC having a voltage value corresponding to the voltage value of the reference voltage VR as a power supply voltage for operating a circuit element (not shown) formed in the internal circuit 10 based on the power supply potential VDD. Generate. The regulator 12 supplies the constant power supply voltage VDC to the internal circuit 10 and the power-on reset circuit 13.

  Further, the regulator 12 generates a reference voltage signal S1 representing the voltage value of the reference voltage VR and a constant power supply voltage signal S2 representing the voltage value of the constant power supply voltage VDC, and supplies them to the power-on reset circuit 13.

  The power-on reset circuit 13 generates the following power-on reset signal POR based on the reference voltage signal S1, the constant power supply voltage signal S2, the constant power supply voltage VDC, and the power supply potential VDD. That is, the power-on reset circuit 13 has a low voltage value (for example, zero volts) that prompts resetting until a predetermined period elapses after the power supply potential VDD is turned on, and after a predetermined period elapses A power-on reset signal POR having a voltage value is generated.

  The power-on reset circuit 13 supplies the power-on reset signal POR to the internal circuit 10. Circuit elements such as flip-flops and functional modules included in the internal circuit 10 are set in a reset state while the power-on reset signal POR is in a low voltage value state. Thereafter, when the power-on reset signal POR transitions from a low voltage value to a predetermined high voltage value, the reset state of the circuit element and the functional module is released.

  FIG. 2 is a circuit diagram showing an example of the internal configuration of the regulator 12 and the power-on reset circuit 13.

  As shown in FIG. 2, the regulator 12 includes p-channel MOS (metal oxide semiconductor) transistors M3, M5 to M7, n-channel MOS transistors M4, M9 to M13, Mna, resistors R1 and R2, And a so-called error amplifier including a current source G1.

  The current source G1 generates a predetermined constant current based on the power supply potential VDD, and supplies this to the gate end and drain end of the transistor M9 and the gate end of the transistor M11. The ground potential VSS is applied to the source ends of the transistors M9 and M11.

  The source ends of the transistors M12 and M13 as a differential pair are connected to the drain end of the transistor M11.

  The reference voltage VR generated by the reference voltage generator 11 is applied to the gate terminal of the transistor M13 as one transistor in the differential pair. The drain end of the transistor M13 is connected to the drain end and gate end of the primary side transistor M6 of the first current mirror circuit CM1 and the gate end of the secondary side transistor M5 via the node L1. A power supply potential VDD is applied to the source ends of the transistors M5 and M6. The drain end of the transistor M5 is connected to the gate end of the transistor Mna and the drain end of the transistor M4 via the node La.

Here, the voltage generated at the node L1 is supplied to the power-on reset circuit 13 as the reference voltage signal S1. The power supply potential VDD is applied to the drain terminal of the transistor Mna, and the source terminal is connected to the output node L0. Is connected to one end of the resistor R1. One end of the resistor R2 and the gate end of the transistor M12 are connected to the other end of the resistor R1. A ground potential VSS is applied to the other end of the resistor R2.

  Here, due to the current sent from the transistor Mna to the output node L0 and the resistor R1, a voltage generated at one end of the resistor R1 and the output node L0 is supplied to the internal circuit 10 and the power-on reset circuit 13 as a constant power supply voltage VDC. Is done. Further, a voltage obtained by dividing the constant power supply voltage VDC by a voltage dividing circuit including resistors R1 and R2 is supplied as a divided voltage INN to the gate terminal of the transistor M12.

  The resistors R1 and R2 are resistors that make the voltage value of the divided voltage INN obtained when the voltage value of the constant power supply voltage VDC is in a steady state equal to the voltage value of the reference voltage VR in the steady state. Has a value.

  The drain end of the transistor M12 as the other transistor in the differential pair is connected to the drain end and gate end of the primary side transistor M3 of the second current mirror circuit CM2 via the node L2, and the gate of the secondary side transistor M7. Connected to the end. A power supply potential VDD is applied to the source ends of the transistors M3 and M7. The drain end of the transistor M7 is connected to the gate end and drain end of the transistor M10 and the gate end of the transistor M4 via the node Lb. A ground potential VSS is applied to the source terminals of the transistors M4 and M10.

  Here, the voltage generated at the node Lb by the current Ib is supplied to the power-on reset circuit 13 as the constant power supply voltage signal S2.

  The power-on reset circuit 13 includes p-channel MOS transistors M31 and M32, n-channel MOS transistors M0 and M20 to M22, and a current source G2.

  The power supply potential VDD is applied to the source terminal of the transistor M31, and the reference voltage signal S1 is supplied to the gate terminal. The drain end of the transistor M31 is connected to the drain end of the transistor M0, the drain end of the transistor M20, and the gate ends of the transistors M22 and M32 via the drive node LQ.

  The constant power supply voltage signal S2 is supplied to the gate terminal of the transistor M0, and the ground potential VSS is applied to the source terminal.

  The ground potential VSS is applied to the source ends of the transistors M20 and M21 constituting the first offset adjustment unit CT1. The drain end of the transistor M20 is connected to the drive node LQ. The current source G2 generates a predetermined constant current based on the power supply potential VDD, and supplies this to the gate end and drain end of the transistor M21 and the gate end of the transistor M20.

  With this configuration, the offset adjustment unit CT1 extracts the adjustment current Io1 having a current value corresponding to the constant current generated by the current source G2 from the drive node LQ via the transistor M20.

  The constant power supply voltage VDC generated by the regulator 12 is applied to the source end of the transistor M32 via the output node L0, and the drain end is connected to the drain end of the transistor M22 via the output node Lr. ing. The ground potential VSS is applied to the source terminal of the transistor M22.

  When the voltage value of the drive node LQ is higher than its own threshold voltage, the inverter constituted by these transistors M22 and M32 outputs a power-on reset signal POR having a low voltage value VL corresponding to the ground potential VSS. Output via Lr. Further, when the voltage value of drive node LQ is equal to or lower than the threshold voltage, the inverter outputs a power-on reset signal POR having a high voltage value VH corresponding to constant power supply voltage VDC via output node Lr.

  By the way, the inverter constituted by the transistors M22 and M32 functions as a so-called comparator that compares the voltage value of the drive node with a predetermined threshold value by using its own threshold voltage. Therefore, hereinafter, the inverter composed of the transistors M22 and M32 will be referred to as a comparator (M22, M32).

  Hereinafter, the operation of generating the constant power supply voltage VDC and the operation of generating the power-on reset signal POR with the configuration shown in FIG. 2 will be described with reference to the time chart shown in FIG.

[Generation operation of constant power supply voltage VDC]
First, since the power supply potential VDD is in a state of zero volts before the power is turned on, the constant power supply voltage VDC is also in a state of a low voltage value VL of zero volts as shown in FIG.

  When the power supply is turned on, the power supply potential VDD increases. When the potential exceeds a predetermined potential, the voltage value of the reference voltage VR generated by the reference voltage generation unit 11 follows the increase in the power supply potential VDD. To increase.

  Thereby, the transistor M13 of the regulator 12 causes the current I1 corresponding to the voltage value of the increasing reference voltage VR to flow to the node L1. Then, the current mirror circuit CM1 sends a current Ia corresponding to the current I1 of the node L1 to the node La, and increases the voltage value of the node La. At this time, the transistor Mna sends a current corresponding to the voltage value of the node La to the output node L0. As a result, the voltage of the output node L0, that is, the voltage value of the constant power supply voltage VDC increases as shown in FIG.

  During this time, the divided voltage INN obtained by dividing the constant power supply voltage VDC is supplied to the gate terminal of the transistor M12. The transistor M12 passes a current I2 corresponding to the divided voltage INN to the node L2. Then, the current mirror circuit CM2 sends a current Ib corresponding to the current I2 of the node L2 to the node Lb, and increases the voltage of the node Lb. At this time, the transistor M4 extracts the current Ic corresponding to the voltage value of the node Lb from the node La. Accordingly, a voltage corresponding to the current (Ia-Ic) is generated at the node La.

  Therefore, the transistor Mna generates the constant power supply voltage VDC as described above by sending a current corresponding to the voltage value corresponding to the current (Ia-Ic) to the output node L0.

  Incidentally, there is a delay until the voltage value of the reference voltage VR is reflected in the constant power supply voltage VDC. Therefore, during the increase period of the reference voltage VR immediately after the power is turned on, the voltage value of the reference voltage VR becomes higher than the voltage value of the divided voltage INN that is a divided voltage of the constant power supply voltage VDC. Therefore, during this time, the current Ia corresponding to the voltage value of the reference voltage VR becomes larger than the current Ic corresponding to the voltage value of the divided voltage INN. Therefore, since the current (Ia-Ic) becomes larger than zero, the transistor Mna sends out the current (Ia-Ic), thereby increasing the voltage value of the constant power supply voltage VDC as shown in FIG.

  After that, as shown in FIG. 3, when the steady state where the power supply potential VDD becomes a predetermined constant potential is reached and the voltage value of the reference voltage VR also reaches the steady state, the voltage value of the reference voltage VR and the divided voltage The voltage value of the voltage INN becomes equal. Thereby, the current Ia corresponding to the voltage value of the reference voltage VR becomes equal to the current Ic corresponding to the voltage value of the divided voltage INN, and the current (Ia−Ic) becomes zero. Therefore, the voltage of the node La becomes a low voltage value, and the transistor Mna is turned off. Therefore, as shown in FIG. 3, the increase of the constant power supply voltage VDC stops at the time point t1, and is maintained at the high voltage value VH that is the voltage value in the steady state.

[Generation of power-on reset signal POR]
A reference voltage signal S1 representing the voltage value of the node L1 of the regulator 12, that is, the voltage value of the reference voltage VR is supplied to the gate terminal of the transistor M31 of the power-on reset circuit 13. Further, a constant power supply voltage signal S2 representing the voltage value of the node Lb of the regulator 12, that is, the voltage value of the divided voltage INN corresponding to the constant power supply voltage VDC is supplied to the gate terminal of the transistor M0 of the power-on reset circuit 13. Has been.

  As a result, the transistor M31 supplies the current Ir corresponding to the reference voltage VR to the drive node LQ, and the transistor M0 extracts the current Ip corresponding to the constant power supply voltage VDC from the drive node LQ. Further, the offset adjustment unit CT1 included in the power-on reset circuit 13 extracts the adjustment current Io1 having a predetermined constant current value from the drive node LQ.

  Therefore, the drive current Isub represented by the following mathematical formula is supplied to the gate terminals of the transistors M22 and M32 constituting the comparator.

Isub = Ir-Ip-Io1
Here, as described above, the voltage value of the reference voltage VR is the divided voltage INN during the period from the time when the power is turned on until the time t1 when the voltage value of the constant power supply voltage VDC reaches the high voltage value VH in the steady state. Higher than the voltage value. Therefore, during this time, the current Ir corresponding to the voltage value of the reference voltage VR becomes larger than the current Ip corresponding to the divided voltage INN, and the current value of the drive current Isub becomes larger than zero. Due to the drive current Isub, the voltage of the drive node LQ (hereinafter referred to as reset drive voltage PWB) increases.

  That is, the voltage value of the reset drive voltage PWB is maintained higher than the threshold voltage of the comparators (M22, M32) over the reset period from the power-on time point to the time point t1 shown in FIG. Accordingly, during this time, the transistor M32 is turned off and the transistor M22 is turned on, and the comparator generates a power-on reset signal POR having a low voltage value VL as shown in FIG.

  Thereafter, as shown in FIG. 3, when the voltage value of the constant power supply voltage VDC reaches the high voltage value VH, the voltage value of the reference voltage VR becomes substantially equal to the voltage value of the divided voltage INN. Therefore, during this time, the current Ir corresponding to the voltage value of the reference voltage VR is substantially equal to the current Ip corresponding to the divided voltage INN.

  As a result, since the current supply to the drive node LQ is stopped after the time t1 shown in FIG. 3, the voltage of the drive node LQ, that is, the voltage value of the reset drive voltage PWB is lower than the threshold voltage of the comparators (M22, M32). Transition to the low voltage value VL. Therefore, after time t1 shown in FIG. 3, the transistor M22 is turned off and the transistor M32 is turned on, and the comparators (M22, M32) receive the power-on reset signal POR having the high voltage value VH as a voltage value for prompting reset release. Generate.

  As described above, in the power-on reset circuit 13, the current Ir corresponding to the voltage value of the reference voltage VR is supplied to the drive node LQ by the current difference acquisition unit including the transistors M0 and M31, and also corresponds to the constant power supply voltage VDC. The extracted current Ip is extracted from the drive node LQ. The comparators (M22, M32) generate the power-on reset signal POR based on the comparison result between the voltage value generated in the drive node LQ by the current (Ir-Ip) and the predetermined threshold value.

  Therefore, according to the above-described current difference, the variation in the threshold voltage of each transistor due to manufacturing variations is canceled out. Therefore, even if manufacturing variations occur, it is possible to reliably generate the power-on reset signal POR that makes a transition from the low voltage value VL state that prompts resetting to the high voltage value VH state that prompts reset release. Become.

  Furthermore, the power-on reset circuit 13 is provided with an offset adjustment unit CT1 that adjusts the threshold voltage of the comparators (M22, M32).

  The offset adjustment unit CT1 draws out the adjustment current Io1 corresponding to the constant current generated by the current source G2 from the drive node LQ, thereby relatively increasing the threshold voltage of the comparators (M22, M32) accordingly. That is, the threshold voltage of the comparator (M22, M32) is adjusted by the amount of constant current generated by the current source G2.

  According to the adjustment by the offset adjustment unit CT1, it is possible to reliably maintain the transistor M32 in the on state after reset is released, for example. Therefore, after the time point t1 shown in FIG. 3, the voltage value of the power-on reset signal POR is maintained in the state of the high voltage value VH that urges reset release reliably.

  FIG. 4 is a circuit diagram showing another example of the internal configuration of the regulator 12 and the power-on reset circuit 13. 4 is the same as that shown in FIG. 2 except that the power-on reset circuit 13 is newly provided with a second offset adjustment unit CT2.

  Therefore, the configuration and operation will be described below with a focus on the offset adjustment unit CT2.

  As shown in FIG. 4, the offset adjustment unit CT2 includes n-channel MOS transistors M34 and M35. The drain end of the transistor M34 is connected to the drive node LQ. A constant current generated by the current source G2 is supplied to the gate terminal of the transistor M34, similarly to the gate terminals of the transistors M20 and M21 of the offset adjustment unit CT1. The source end of the transistor M34 is connected to the drain end of the transistor M35. The ground potential VSS is applied to the source terminal of the transistor M35, and the power-on reset signal POR is supplied to the gate terminal.

  With this configuration, in the offset adjustment unit CT2, when the power-on reset signal POR is in the low voltage value VL state, that is, during the reset period shown in FIG. 3, the transistor M35 is in the off state. Therefore, during this time, the offset adjustment unit CT2 is set to an inactive state, and the power-on reset circuit 13 is a circuit substantially equivalent to the configuration shown in FIG.

  Further, when the power-on reset signal POR is in the state of the high voltage value VH, that is, after the time t1 shown in FIG. 3, the transistor M35 of the offset adjustment unit CT2 is turned on. Thereby, the adjustment current Io2 having a current amount corresponding to the constant current generated by the current source G2 is extracted from the drive node LQ via the transistors M34 and M35.

  That is, the offset adjustment unit CT2 stops operating during the reset period, but starts operating immediately after the end of the reset period, and changes the threshold voltage of the comparators (M22, M32) with the adjustment current Io2.

  Therefore, according to the offset adjustment unit CT2, it is possible to provide the power-on reset circuit 13 with hysteresis.

  After the reset period, the threshold voltage of the comparators (M22, M32) is adjusted by the adjustment current Io1 from the offset adjustment unit CT1 and the adjustment current Io2 from the offset adjustment unit CT2. That is, the adjustment range can be increased as compared with the case where the threshold voltage of the comparators (M22, M32) is adjusted only by the offset adjustment unit CT1.

  In the embodiment shown in FIG. 4, the power-on reset circuit 13 is provided with two offset adjustment units CT1 and CT2, but only the offset adjustment unit CT2 of CT1 and CT2 is provided in the power-on reset circuit 13. Anyway. At this time, a current source G2 of the offset adjusting unit CT1 is provided in the offset adjusting unit CT2.

  In addition, as long as the power-on reset signal POR that reliably transitions from the low voltage value VL state to the high voltage value VH state can be generated without using the offset adjustment units CT1 and CT2, as shown in FIG. The offset adjustment units CT1 and CT2 need not be provided.

  In the embodiment shown in FIG. 2 or FIG. 4, n-channel MOS transistors are employed as the differential pair (M12, M13) of the regulator 12, but p-channel MOS transistors may be employed. good.

  The power-on reset circuit 13 receives the voltage at the node L1 of the regulator 12 as the reference voltage signal S1 representing the voltage value of the reference voltage VR, and receives the voltage at the node Lb of the regulator 12 as the voltage value of the constant power supply voltage VDC. Is received as a constant power supply voltage signal S2.

  However, the power-on reset circuit 13 may be configured to directly receive the reference voltage VR and the constant power supply voltage VDC.

  In short, the semiconductor device 100 only needs to include the following regulator and power-on reset circuit.

  That is, the regulator (12) receives the reference voltage (VR) and generates a constant power supply voltage (VDC) having a voltage value corresponding to the reference voltage when the power is turned on. The power-on reset circuit (13) has a first voltage value (VL) that prompts a reset for a predetermined period from the time of turning on the power based on the reference voltage and the constant power supply voltage, and is reset after the lapse of the predetermined period from the time of turning on the power. A power-on reset signal (POR) that makes a transition to the second voltage value (VH) that prompts the release is generated. The power-on reset circuit (13) includes the following current difference acquisition unit and comparator. The current difference acquisition unit (M0, M31) supplies the first current (Ir) corresponding to the voltage value of the reference voltage to the drive node (LQ) and the second current (Ip) corresponding to the constant power supply voltage. Is removed from the drive node. The comparators (M22, M32) obtain a power-on reset signal (POR) based on the comparison result between the voltage value of the drive node (LQ) and the threshold voltage.

DESCRIPTION OF SYMBOLS 10 Internal circuit 11 Reference voltage generation part 12 Regulator 13 Power-on reset circuit 100 Semiconductor device

Claims (8)

A regulator that receives a reference voltage and generates a constant power supply voltage having a voltage value corresponding to the reference voltage when the power is turned on;
Based on the reference voltage and the constant power supply voltage, the second voltage has a first voltage value that prompts resetting for a predetermined period from the power-on time point, and prompts reset release after the predetermined period from the power-on time point. A power-on reset circuit that generates a power-on reset signal that transitions to a value, and
The power-on reset circuit is
A driving node;
Supplying a first current corresponding to the voltage value of the reference voltage to the drive node, and extracting a second current corresponding to the constant power supply voltage from the drive node;
And a comparator that obtains the power-on reset signal based on a comparison result between the voltage value of the drive node and a predetermined threshold value. The regulator is
A voltage dividing circuit for obtaining a divided voltage obtained by dividing the constant power supply voltage;
A differential pair for flowing a current corresponding to the reference voltage to the first node and a current corresponding to the divided voltage to the second node;
A current mirror circuit for supplying a current corresponding to a current flowing through the second node to a third node;
The current difference acquisition unit
A first transistor having a control terminal connected to the first node and supplying a current corresponding to a voltage of the first node to the drive node as the first current;
A control terminal connected to the third node, and a second transistor that draws a current corresponding to the voltage of the third node from the drive node as the second current,
The comparator is
When the voltage of the drive node is larger than the threshold voltage, the power-on reset signal having a ground potential is output as the first voltage value, and when the voltage of the drive node is equal to or lower than the threshold voltage, The semiconductor device according to claim 1, wherein the power-on reset signal having the constant power supply voltage is output as a second voltage value.   3. The semiconductor device according to claim 1, further comprising a first adjustment unit that draws a predetermined first adjustment current from the drive node. The first adjustment unit includes:
A current source for generating a predetermined constant current;
The semiconductor device according to claim 3, further comprising: a current mirror circuit that generates a current corresponding to the constant current as the first adjustment current.   5. The semiconductor according to claim 3, further comprising a second adjustment unit that draws a predetermined second adjustment current from the drive node when the power-on reset signal has the second voltage value. 6. apparatus. The second adjustment unit includes:
A third transistor that generates a current corresponding to the constant current as the second adjustment current; and a third transistor that is turned on when the power-on reset signal has the second voltage value. The semiconductor device according to claim 5, further comprising: a fourth transistor that extracts the generated second adjustment current from the drive node.   The semiconductor device according to claim 1, further comprising a reference voltage generation unit that generates the reference voltage when power is turned on. Power that generates a power-on reset signal that has a first voltage value that prompts reset for a predetermined period from the time of power-on, and that transitions to a second voltage value that prompts reset release after the elapse of the predetermined period from the time of power-on An on-reset device,
A regulator that receives a reference voltage and generates a constant power supply voltage having a voltage value corresponding to the reference voltage when the power is turned on;
A driving node;
Supplying a first current corresponding to the voltage value of the reference voltage to the drive node, and extracting a second current corresponding to the constant power supply voltage from the drive node;
A power-on reset device comprising: a comparator that obtains the power-on reset signal based on a comparison result between the voltage value of the drive node and a predetermined threshold value.

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