JP2018205814A - Power supply circuit - Google Patents

Abstract

To provide a power supply circuit in which overshoot is suppressed and undershoot is not caused in an input transient response in a state in which the input voltage is insufficient.SOLUTION: An error amplifier 14 includes: a pair of differential connection input transistors M2 and M3 for comparing a reference voltage VREF and a feedback voltage VFB; current sources 141 and 142 for supplying operating current to the pair of differential connection input transistors; a pair of current mirror connection transistors M6 and M7 for generating the control voltage for an output transistor M1 according to the comparison result of the pair of differential connection input transistors; a pair of gate-grounded transistors M4 and M5 connected between each drain of the pair of differential connection input transistors and each drain of the pair of current mirror connection transistors; and a detector 144 for making the detection signal valid only during a period in which the difference between the drain voltages of the pair of differential connection input transistors exceeds a threshold value. The current source 142 causes a current I2 to flow according to the detection signal of the detector.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply circuit that suppresses overshoot that occurs in a region where an input voltage is insufficient.

  FIG. 3 shows a power supply circuit 10B that controls the output voltage VOUT to a constant voltage. 11 is an input terminal, 12 is a ground terminal, 13 is an output terminal, 14B is an error amplifier, 15 is a reference voltage source, M1 is a PMOS output transistor, and R1 and R2 are voltage dividing resistors for dividing the output voltage VOUT of the output terminal 13. , R3 are bias resistors of the output transistor M1. An input voltage source 21 of voltage VIN is connected to the input terminal 11, an output capacitor C1 is connected to the output terminal 13, and a load 22 is connected in parallel to the output capacitor C1.

  In normal operation, the difference between the feedback voltage VFB obtained at the common connection point of the resistors R1 and R2 connected between the output terminal 13 and the ground terminal 12 and the reference voltage VREF generated by the reference voltage source 15 is an error amplifier. The output voltage VOUT is controlled to a target value corresponding to the reference voltage VREF by controlling the gate voltage of the output transistor M1 so that VFB = VREF by the output voltage of the error amplifier 14B.

  By the way, in recent power supply circuits, there is a strong demand for low current consumption from various fields (cars, home appliances, industrial equipment, etc.), and it is required to design without increasing current consumption. In order to reduce the current consumption, it is necessary to reduce the operating current (tail current) of the error amplifier 14B. However, if the operating current is reduced, a quick response cannot be realized. In particular, the input transient response when the input voltage VIN is insufficient is a condition where overshoot is likely to occur, and some countermeasure is required.

  FIG. 4 is a characteristic diagram showing a change in the output voltage VOUT when the input voltage VIN of the power supply circuit 10B in FIG. 3 rises, and FIG. 5 is a diagram showing a transient response characteristic at that time. In FIG. 4, when the input voltage VIN reaches a predetermined value (2V), the output voltage VOUT rises along the slope of the dotted line, and when the input voltage VIN reaches the target voltage (3.3V), the voltage value is maintained thereafter. Controlled.

  However, in the insufficient region P1 before the input voltage VIN reaches the target value, the gate-source voltage VGS1 of the output transistor M1 is large (2.6 V) as shown in FIG. When the input voltage VIN rises, it takes a long time for the gate-source voltage VGS1 to reach an appropriate value (2V), the output transistor M1 is driven greatly, and the output voltage VOUT becomes abnormally high. Occur.

  In recent years, there is a market demand for lower current consumption in semiconductor devices, and the operating current of the error amplifier 14B tends to be reduced. Therefore, the discharge time until the gate-source voltage VGS1 of the output transistor M1 becomes an appropriate value. However, there are increasing cases of overshooting and problems.

  Therefore, in Patent Document 1, a current feedback circuit is newly provided to detect an increase in input voltage, and the output transistor is forcibly turned off during this period.

JP 2007-157071 A

  However, although the method of Patent Document 1 suppresses the amount of overshoot with respect to an increase in input voltage, there is a problem that undershoot occurs as a trade-off until the output transistor is turned on again.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a power supply circuit that suppresses overshoot and does not cause undershoot in an excessive input response when the input voltage is insufficient. Is to provide.

In order to achieve the above object, a power supply circuit according to a first aspect of the present invention includes an output transistor that generates an output voltage by adjusting an input voltage, and a difference between a feedback voltage corresponding to the output voltage and a reference voltage. An error amplifier that generates a control voltage of the output transistor, the error amplifier including a differentially connected input transistor pair that compares the reference voltage and the feedback voltage, and the differentially connected input A current source that supplies an operating current to the transistor pair; a current mirror-connected transistor pair that generates the control voltage according to the comparison result of the differential-connected input transistor pair; and drains of the differential-connected input transistor pair And a common-gate transistor pair connected between each drain of the current mirror-connected transistor pair, and the feedback voltage is A detector that outputs a detection signal only during a period that is lower than a quasi-voltage and a difference between drain voltages of the differentially connected input transistor pair exceeds a threshold, and the current source includes the detection of the detector The current is increased by a signal.
The invention according to claim 2 is the power supply circuit according to claim 1, further comprising a hold capacitor that holds the detection signal of the detector for a predetermined time.
According to a third aspect of the present invention, in the power supply circuit according to the first or second aspect, the differential connection input transistor pair has a first conductivity type in which a source is connected to the current source and the reference voltage is input to a gate. The second transistor is composed of a third transistor of a first conductivity type whose source is connected to the current source and the feedback voltage is input to the gate, and the common-gate transistor pair has a source connected to the drain of the second transistor. And a first conductivity type fourth transistor in which a bias voltage is input to the gate, and a first conductivity type fifth transistor in which a source is connected to the drain of the third transistor and the bias voltage is input to the gate. The current mirror-connected transistor pair has a second conductivity type sixth transistor having a drain connected to the drain of the fourth transistor. And Njisuta, drain and gate is constituted by the drain and the seventh transistor of the second conductivity type connected to a gate of the sixth transistor of said fifth transistor, and wherein the.
According to a fourth aspect of the present invention, in the power supply circuit according to the first, second, or third aspect, the current source is a fixed current source that is always turned on, and a variable current source that is turned on by the detection signal of the detector. It is characterized by being connected in parallel.

  According to the present invention, since the operating current of the error amplifier is increased in a region where the input voltage is insufficient, overshoot due to an increase in the gate-source voltage of the output transistor in that region can be suppressed. Since the increase in the operating current is performed only in a region where the input voltage is insufficient, the current consumption during the normal operation does not increase. Further, since overshoot is suppressed without forcibly turning off the output transistor, undershoot does not occur.

It is a circuit diagram of the power supply circuit of 1st Example of this invention. It is an operation | movement waveform diagram of the power supply circuit of FIG. It is a circuit diagram of the conventional power supply circuit. FIG. 4 is an input / output waveform diagram of the power supply circuit of FIG. 3. FIG. 4 is an operation waveform diagram of the power supply circuit of FIG. 3.

  FIG. 1 shows a power supply circuit 10A according to an embodiment of the present invention. The same components as those described with reference to FIG. The error amplifier 14A of the present embodiment includes an NMOS type transistor M2, which constitutes a differentially connected input transistor pair whose source is commonly connected to a current source consisting of a fixed current source 141 having a current I1 and a variable current source 142 having a current I2. The reference voltage VREF is input from the reference voltage source 15 to the gate of the transistor M2, and the feedback voltage VFB is input to the gate of the transistor M3.

  M4 and M5 constitute an NMOS type grounded-gate transistor pair. The source of the transistor M4 is connected to the drain of the transistor M2, the source of the transistor M5 is connected to the drain of the transistor M3, and a common bias voltage VBIAS is input to each gate by the bias voltage source 143.

  M6 and M7 are PMOS transistors constituting a current mirror connection transistor pair that functions as an active load of the transistors M2 and M3. The transistor M6 has a source connected to the input terminal 11 and a drain connected to the drain of the transistor M4 and the gate of the output transistor M1. The transistor M7 has a source connected to the input terminal 11, and a gate and a drain connected to the gate of the transistor M6 and the drain of the transistor M5.

  Reference numeral 144 denotes a detector that detects that the input voltage is in an insufficient state, and takes in the voltage VA of the node A that is the drain of the transistor M2 and the voltage VB of the node B that is the drain of the transistor M3, and the difference (VB -VB) outputs a detection signal only during a period when it exceeds a preset threshold value VT. When this detection signal is output, the variable current source 142 is turned on and operates to add the current I2 to the current I1 of the fixed current source 141. C2 is a hold capacitor connected between the output side of the detector 144 and the ground terminal 12. Even when (VB-VA) becomes smaller than the threshold value VT, the detection signal of the detector 144 is supplied for a predetermined time. The operation of the variable current source 142 is continued by holding.

  During normal operation, the feedback voltage VFB obtained by dividing the output voltage VOUT by the resistors R1 and R2 and the reference voltage VREF are compared by the transistors M2 and M3. When the output voltage VOUT is higher than the target value, VREF <VFB, so the voltages VA and VB of the nodes A and B become VA> VB, the drain voltage of the transistor M6 rises, and the output transistor M1 Control is performed such that the gate-source voltage VGS1 decreases and the output voltage VOUT decreases. Conversely, when the output voltage VOUT is lower than the target value, VREF> VFB, so VA <VB, the drain voltage of the transistor M6 decreases, and the gate-source voltage VGS1 of the output transistor M1 increases, Control is performed to increase the output voltage VOUT.

  In this way, negative feedback control is performed so that the output voltage VOUT becomes the target voltage corresponding to the reference voltage VREF. At this time, the voltages VA and VB of the nodes A and B are controlled to be “VBIAS−VGS” (VGS is a gate-source voltage of the transistors M4 and M5) by the common-gate transistor M4 and M5. When the output voltage VOUT changes, the negative feedback control described above is performed in accordance with the change. However, during normal operation, VA = VB is maintained.

  Next, in a region where the input voltage VIN is low, the error amplifier 14A satisfies VREF> VFB, and at this time, the output voltage VOUT operates to increase to a voltage as close as possible to the set voltage. At this time, the voltage VA at the node A is lower than the voltage VB at the node B, and the gate-source voltage VGS1 of the output transistor M1 becomes larger than when the input voltage VIN is sufficiently high.

  As described above, when the input voltage VIN is insufficient, the gate-source voltage VGS1 of the output transistor M1 is larger than usual. When the input voltage VIN rises from this state, the output transistor M1 is left as it is. As described above, the time until the gate-source voltage VGS1 of M1 becomes an appropriate value increases and the overshoot of the output voltage VOUT increases.

  However, in this embodiment, the detector 144 operates at this time, and the overshoot of the output voltage VOUT is suppressed. That is, when the input voltage VIN is insufficient, the voltage VA of the node A and the voltage VB of the node B are VA <VB, and “VB−VA” exceeds the threshold value VT. Detection is performed and a detection signal is output, the variable current source 142 is operated, and the operating current of the error amplifier 14A is increased to “I1 + I2”.

  As a result, the charge between the gate and the source of the output transistor M1 is largely discharged, so that the gate-source voltage VGS1 is quickly reduced and the overshoot of the output voltage VOUT is suppressed. When the input voltage VIN returns to the predetermined value, “VB−VA” becomes smaller than the threshold value VT, and the detector 144 does not operate.

  The detector 144 itself stops outputting the detection signal when the input voltage VIN becomes a predetermined voltage and “VB−VA” falls below the threshold value VT as described above, but the hold capacitor C2 has a charge of the detection signal. Therefore, the variable current source 142 continues to flow the current I2 for a predetermined time by the electric charge.

  The detector 144 stops outputting the detection signal when the output voltage VOUT reaches the target value. When the operating current of the error amplifier 14A is immediately switched from “I1 + I2” to I1, the output transistor The charge between the gate and the source of M1 cannot be sufficiently discharged, and the output voltage VOUT may further rise and the overshoot suppression may be insufficient.

  However, by connecting the hold capacitor C2 as described above, the discharge of the charge between the gate and the source of the power transistor M1 is continued for a predetermined time thereafter, and the overshoot is more effectively suppressed. The above operation waveforms are shown in FIG. The dotted line in FIG. 2 shows the characteristics (FIG. 5) in the case of the conventional power supply circuit 10B in FIG.

  As described above, in the power supply circuit 10A of this embodiment, the current consumption increases when the input voltage VIN decreases, but the current source 142 does not operate and the current consumption does not increase in the normal operation.

  Since overshoot is suppressed without forcibly turning off the output transistor, undershoot does not occur.

  In the power supply circuit 10A described above, when the polarity of the input voltage source 21 is reversed, the polarity of the reference voltage source 15 and the bias voltage source 143 is also reversed, and the NMOS transistors M2 to M5 are replaced with PMOS transistors. The transistors M1, M6, and M7 may be replaced with NMOS transistors. In the claims, one of the NMOS transistor and the PMOS transistor is described as the first conductivity type, and the other is described as the second conductivity type.

10A, 10B: power supply circuit, 11: input terminal, 12: ground terminal, 13: output terminal, 14A, 14B: error amplifier, 141: fixed current source, 142: variable current source, 143: bias voltage source, 144: detection 15: Reference voltage source 21: Input voltage source 22: Load

Claims (4)

A power supply circuit comprising: an output transistor that generates an output voltage by adjusting an input voltage; and an error amplifier that generates a control voltage of the output transistor according to a difference between a feedback voltage corresponding to the output voltage and a reference voltage There,
The error amplifier includes: a differential connection input transistor pair that compares the reference voltage and the feedback voltage; a current source that supplies an operation current to the differential connection input transistor pair; and the comparison of the differential connection input transistor pair A current mirror connection transistor pair that generates the control voltage according to the result of the above, and a common-gate transistor pair connected between each drain of the differential connection input transistor pair and each drain of the current mirror connection transistor pair And a detector that outputs a detection signal only during a period when the feedback voltage is lower than the reference voltage and the difference between the drain voltages of the differentially connected input transistor pair exceeds a threshold,
The power source circuit, wherein the current source increases current by the detection signal of the detector. The power supply circuit according to claim 1,
A power supply circuit comprising a hold capacitor for holding the detection signal of the detector for a predetermined time. The power supply circuit according to claim 1 or 2,
The differentially connected input transistor pair includes a first conductivity type second transistor having a source connected to the current source and a reference voltage input to a gate, and a source connected to the current source and the feedback voltage input to the gate. And a third transistor of the first conductivity type.
The grounded-gate transistor pair includes a first conductivity type fourth transistor whose source is connected to the drain of the second transistor and a bias voltage is input to the gate, and a source connected to the drain of the third transistor and the gate connected to the gate. A first conductivity type fifth transistor to which a bias voltage is input;
The current mirror-connected transistor pair includes a second conductivity type sixth transistor having a drain connected to the drain of the fourth transistor, and a drain and a gate connected to the drain of the fifth transistor and the gate of the sixth transistor. And a seventh transistor of the second conductivity type. In the power supply circuit according to claim 1, 2, or 3,
The power source circuit is characterized in that the current source is configured by connecting in parallel a fixed current source that is always ON and a variable current source that is ON by the detection signal of the detector.

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