KR20070084879A - Negative back bias voltage detector - Google Patents

Abstract

A negative back bias voltage detector is provided to perform back bias voltage detection stably by adopting a differential amplifier less influenced by process, voltage and temperature, rather than an inverter type transistor. A reference voltage generation part generates a reference voltage according to the resistance value ratio of resistors comprised between an internal power supply voltage and a ground. A back bias voltage input part generates an input voltage according to the resistance ratio of resistors comprised between the internal power supply voltage and a back bias voltage. A single end differential amplifier detects the variation of the back bias voltage level to the reference voltage by comparing the reference voltage with the input voltage.

Description

Substrate Bias Voltage Detector

1 is a block diagram of a general substrate bias voltage generation and detection device;

2 is a timing diagram related to the substrate bias boosted voltage charge pumping operation of FIG. 1;

3 is a circuit diagram of a conventional substrate bias voltage level detector;

4 is a block diagram of a substrate bias generator according to the present invention;

5 is a circuit diagram of a substrate bias voltage level detector according to a preferred embodiment of the present invention.

* Brief description of symbols for the main parts of the drawings *

100: Vbb level detector 200: oscillator

300: Vbb charge pumping part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to substrate bias generators used in semiconductors, and more particularly to detectors for detecting negative substrate bias voltages.

Substrate bias voltage (also called back bias voltage, hereinafter referred to as Vbb) is applied to the P well surrounding the NMOS transistor and is generated by an internal substrate bias circuit that generates a voltage of about -2V to -3V from a power supply of Vdd 5V. do. There are various reasons for applying Vbb. There are generally the following reasons.

1. The PN junction in the semiconductor memory is prevented from being partially forward biased to prevent data loss or latchup of the memory cell.

2. Stabilize the circuit operation by reducing the change of the threshold voltage of the MOS transistor according to the body effect. In the semiconductor memory device, if the change of the threshold voltage is too large, the step-up width of the word line voltage should be increased by that much. If the change of the threshold voltage is small, the step-up width of the word line voltage is also reduced, thereby improving the reliability of the device.

1 is a block diagram of a general substrate bias voltage generation and detection device. Referring to FIG. 1, a level detector 1 that detects a potential of feedback Vbb and generates an activation (EN) / deactivation signal of a pump, and a signal output from the level detector 1 as an input and corresponding oscillation. It consists of an oscillator 2 for generating a conversion signal and a charge pumping unit 3 for generating and outputting a Vbb potential in a pumping operation according to the oscillator 2 signal.

2 is a timing diagram illustrating a substrate bias boosted voltage charge pumping operation of FIG. 1. As shown in Fig. 2, when the potential is raised to + by detecting the Vbb voltage, charge pumping is performed to lower the potential to the-potential. When charge pumping is sufficiently performed to lower the Vbb potential, the oscillator may be stopped to maintain the Vbb potential at a constant value.

In the conventional Vbb generator, as shown in FIG. 1, a Vbb level detector for detecting a potential of the feedback Vbb and generating a turn-on / turn-off signal of a charge pump, and a signal output from the Vbb level detector is received. And a control unit for outputting an oscillation signal and a signal for controlling the charge pump, and a Vbb potential generating unit for generating and outputting a Vbb potential in response to a signal output from the control unit.

The Vbb level detector typically detects a vbb potential proportional to the power supply potential.

3 is a circuit diagram of a conventional substrate bias voltage level detector. Referring to FIG. 3, a conventional substrate bias voltage detector includes a Vbb bias output unit 11 for outputting a bias signal, a first inverting unit 12 for first inverting a signal of the Vbb bias output unit 11, The second inverting unit 13 inverts the signal of the first inverting unit 12 again.

In the Vbb bias output unit 11, a plurality of MOS devices MP and MN are connected in series between an internal power supply voltage Vintd terminal and a ground Vss terminal, and a gate of the upper MOS device is commonly grounded (Vss). ) And the gate of the lower MOS device are commonly connected to the substrate bias voltage Vbb. The signal of the Vbb bias output unit 11 is inverted by the first inverter 12 and then inverted again by the second inverter 13 to output the Vbb bias signal. The Vbb bias signal is applied to the oscillator 2 of FIG. 1 to determine whether the charge pumping 3 is driven.

If the Vbb bias signal is at the 'high' level, the oscillator 2 is driven to operate the charge pump 3 according to the driving of the oscillator 2 to repeat the operation of pumping the negative substrate bias voltage to a predetermined level. do.

On the other hand, when the Vbb bias signal is at the 'low' level, the oscillator 2 is not driven, and thus the charge pumping unit 3 does not perform a separate operation so that an operation process such as 'leakage' of FIG. 2 is performed. do.

Since the conventional substrate bias voltage level detector is an inverter-type detector composed of transistors, it is not stable because the change of PVT is large because the process P, the voltage V, and the temperature T are sensitive.

An object of the present invention is to provide a substrate bias voltage level detector that is less affected by process, voltage, and temperature.

The substrate bias voltage level detector according to the present invention for achieving this object comprises a reference voltage generator for generating a reference voltage in accordance with the ratio of the resistance value of the resistors provided between the internal power supply voltage and ground; A substrate bias voltage input unit configured to generate an input voltage according to a ratio of resistance values of resistors provided between the internal power supply voltage and the substrate bias voltage; And a single-ended differential amplifier comparing the reference voltage with the input voltage to detect a change in the substrate bias voltage level with respect to the reference voltage.

The output voltage level of the substrate bias voltage input unit increases when the substrate bias voltage level increases, and decreases when the substrate bias voltage level decreases, and when the output voltage of the substrate bias voltage input unit is higher than the voltage of the reference voltage generator. The differential amplifier generates a 'low' level output signal, and the differential amplifier generates a 'high' level output signal when the output voltage of the substrate bias voltage input unit is lower than that of the reference voltage generator.

The differential amplifier includes a first PMOS transistor and a first NMOS transistor connected in series between the internal power supply voltage and ground, and a second PMOS transistor connected in series between the internal power supply voltage and a substrate bias voltage. And a third NMOS transistor for outputting a circuit activation signal to a common source of the first NMOS transistor and the second NMOS transistor, wherein the first PMOS transistor and the second PMOS transistor are provided. The common gate of is connected to the drain of the first NMOS transistor, it characterized in that for generating an output signal to the connection node of the second NMOS transistor and the second PMOS transistor.

The sum of the resistance provided between the internal power supply voltage and the ground and the sum of the resistance provided between the internal power supply voltage and the substrate bias voltage are set to the same value, but the internal power supply voltage of the resistor provided between the internal power supply voltage and the ground is set to the same value. The value of the connected resistor is set to be greater than the value of the resistor connected to the internal power supply voltage among the resistors provided between the internal power supply voltage and the bias voltage.

The Vbb activation signal is output when the voltage Vintd-Vb for driving the second NMOS transistor MN2 is higher than the voltage Vintd-Va for driving the first NMOS transistor.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

The present invention provides a circuit in which a conventional inverter-type substrate bias voltage level detector is replaced with a current mirror type differential amplifier which receives a small change in process, voltage, and temperature.

4 is a block diagram of a substrate bias generator according to the present invention. Referring to FIG. 4, the substrate bias voltage generator of the present invention senses the potential of the feedback Vbb to generate a turn-on / turn-off signal of the charge pump, and outputs the Vbb level detector 100 from the Vbb level detector 100. The oscillator 20 performs an oscillating operation according to the signal, and the charge pumping unit 300 performs a charge pumping operation according to the oscillation state of the oscillator 20.

When the Vbb level detector 100 detects the level of the Vbb signal by inputting the Vbb signal output from the charge pumping unit 300 and determines that the Vbb potential has leaked above a predetermined value, the Vbb-EN (activation) is activated. ) Is output to the oscillator 200 to pump the negative substrate bias voltage.

On the other hand, when the degree of leakage of the Vbb potential is less than or equal to a predetermined value, the deactivation signal is output to the oscillator 200 so that no separate operation occurs in the charge pumping unit 300. In this section, the Vbb voltage continuously leaks, and when a predetermined time is reached, the Vbb potential leaks above a predetermined value. When the state is detected by the Vbb level detector 100, the Vbb-EN signal is output to the oscillator 200 to pump the negative substrate bias voltage.

Hereinafter, a detailed circuit of the Vbb level detector 100 of the current mirror type differential amplifier will be described.

Differential amplifier is basically composed by connecting two transistor emitters. Externally it has two input terminals, one output terminal for a single output and two output terminals for a differential output. The voltage commonly applied to the two input terminals is called a common-mode voltage, and the difference signal is called a differential-mode or differential signal. Differential amplifiers are insensitive to common-mode voltages and sensitive to differential signals.

5 is a circuit diagram of a substrate bias voltage level detector according to a preferred embodiment of the present invention. Referring to FIG. 5, the substrate bias voltage level detection unit 100 of the present invention includes a current mirror amplifier, and is configured in series between an internal power supply voltage Vintd and ground Vss at one input terminal of the current mirror amplifier. Resistor R3 and R4 are provided, and the other input terminal is provided with resistors R1 and R2 configured in series between the internal power supply voltage Vintd and the substrate bias voltage Vbb.

The current mirror amplifier includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a third NMOS transistor MN3 connected in series between an internal power supply voltage Vintd and ground vss. A second PMOS transistor MP2 and a second NMOS transistor MN2 configured in series between an internal power supply voltage Vintd and a connection node of the first NMOS transistor MN1 and the third NMOS transistor MN3; do.

The enable signal Vintd is received at the gate of the third NMOS transistor, and the voltage divided by the resistors R3 and R4 is applied to the gate of the first NMOS transistor MN1 so that MN1 is turned on. When the voltage divided by the resistors R1 and R2 is applied to the gate of the second NMOS transistor MN2, an output signal is generated at the connection node of the second PMOS transistor and the second NMOS transistor.

The operation of the substrate bias voltage level detector according to the present invention configured as described above is designed to operate under the following preconditions.

First, resistor R3 + R4 is equal to output resistor R1 + R2, and R3> R1.

Let's substitute the above conditions into Equation 1.

[Equation 1]

Substituting the equation of R3 + R4 = R1 + R2 into Equation 1 yields the same result as Equation 2.

[Equation 2]

Here, assume that the substrate bias voltage is sufficiently leaked to approach 0V.

That is, since R3 is larger than R1 in the state where Vbb = 0 and equal to the Vss value, Va is larger than Vb.

Therefore, the voltage Vintd-Vb for driving the second NMOS transistor MN2 is higher than the voltage Vintd-Va for driving the first NMOS transistor MN1.

Therefore, the following equation is established.

[Equation 3]

 When the driving voltage of the second NMOS transistor MN2 increases, the second NMOS transistor MN2 is turned on so that the node potential of the Vbb_EN output terminal becomes 'low'.

In the present invention, Vbb charge pumping is enabled when the signal of the Vbb-EN output terminal is 'low'.

That is, when Vbb leaks to a value similar to Vss, the Vbb-EN activation signal is applied to the oscillator 200.

The Vbb-EN output terminal signal may be configured to be stably transmitted through a predetermined inverter before being transmitted to the oscillator. In case of transmission through one inverter, Vbb charge pumping is enabled when the node potential of the Vbb-EN output terminal is 'high'.

In response to this signal, the charge pumping unit 300 starts the pumping operation to lower the potential to a negative value less than or equal to a predetermined value to provide a stable substrate bias voltage.

On the other hand, although the sum of the resistors R3 and R4 and the sum of the output resistors R1 and R2 are not the same, the above-described Vbb-EN output terminal signals may be output when Va and Vb become equal.

Although the present invention has been described above with reference to its preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be practiced with modification. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, according to the present invention, the substrate bias voltage detector, which is composed of a transistor of a conventional inverter type, employs a differential amplifier that is less affected by process, voltage, and temperature, so that the substrate bias voltage detection can be stably performed. do.

Claims (5)

A reference voltage generator for generating a reference voltage according to a ratio of resistance values of resistors provided between an internal power supply voltage and a ground; A substrate bias voltage input unit configured to generate an input voltage according to a ratio of resistance values of resistors provided between the internal power supply voltage and the substrate bias voltage; And And a single-ended differential amplifier for comparing the reference voltage with the input voltage to detect a change in the substrate bias voltage level with respect to the reference voltage. The method of claim 1, The output voltage level of the substrate bias voltage input unit increases when the substrate bias voltage level increases, and decreases when the substrate bias voltage level decreases, When the output voltage of the substrate bias voltage input unit is higher than the voltage of the reference voltage generator, the differential amplifier generates a 'low' level output signal. And when the output voltage of the substrate bias voltage input unit is lower than the voltage of the reference voltage generator, the differential amplifier generates a high level output signal. The method of claim 1, wherein the differential amplifier A first PMOS transistor and a first NMOS transistor connected in series between the internal power supply voltage and a ground; and a second PMOS transistor and a second NMOS transistor connected in series between the internal power supply voltage and a substrate bias voltage. And a third NMOS transistor for outputting a circuit activation signal to a common source of the first NMOS transistor and the second NMOS transistor. A common gate of the first PMOS transistor and the second PMOS transistor is connected to a drain of the first NMOS transistor, And an output signal is generated at a connection node of the second NMOS transistor and the second PMOS transistor. The method of claim 1, wherein the sum of the resistance provided between the internal power supply voltage and the ground and the sum of the resistance provided between the internal power supply voltage and the substrate bias voltage are set to the same value. Substrate bias, characterized in that the value of the resistance connected to the internal power supply voltage of the resistor provided between the internal power supply voltage and the ground is set larger than the value of the resistance connected to the internal power supply voltage of the resistor provided between the internal power supply voltage and the bias voltage Voltage detector. The Vbb activation signal is output when the voltage Vintd-Vb for driving the second NMOS transistor MN2 is higher than the voltage Vintd-Va for driving the first NMOS transistor. A substrate bias voltage detector.

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