KR100633598B1 - Half power voltage generator - Google Patents

Abstract

 A circuit for generating a half power supply voltage having a voltage level that is half that of the power supply voltage is disclosed. The half power supply voltage generation circuit of the present invention compares the half power supply voltage with the first and second reference voltages provided from the reference voltage generator, and pulls the half power supply voltage from the power supply voltage to the pull-up or ground voltage according to the comparison result. -Down to generate a half supply voltage that is half the supply voltage level. According to the present invention, the driving current of the pull-up current and the pull-down current for the generation of the half power supply voltage flows uniformly, and the pull-up transistor and the pull-down transistor are turned on at the same time by the short circuit prevention circuit so that the power supply voltage and the ground Since the voltage short circuit is prevented, the half power supply voltage is stably generated.

Half-Supply Voltage Generation Circuit, Short-Circuit Protection Circuit, Pull-Up Current, Pull-Down Current, Drive Current

Description

Half power voltage generator

1 is a diagram illustrating a conventional half power supply voltage generation circuit.

2 is a diagram illustrating a half power supply voltage generation circuit according to an embodiment of the present invention.

3 is a graph comparing driving currents of the half power voltage generator circuits of FIGS. 1 and 2.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to a circuit for generating a half power supply voltage corresponding to half of the power supply voltage.

There are internal power supply voltage generation circuits that receive an external power supply voltage VDD, generate an internal power supply voltage, and supply the internal power supply voltage to internal circuits of the semiconductor device. The internal power supply voltage includes a boosted voltage having a voltage level higher than the external power supply voltage VDD, a bit line precharge voltage having a voltage level lower than the external power supply voltage VDD, a cell plate voltage, and the like. The boosted voltage VPP is used to drive word lines without losing memory cell data, and the bit line precharge voltage and the cell plate voltage are used to increase the sensing efficiency of the memory cell data. The bit line precharge voltage and the cell plate voltage typically have a half power supply voltage VHDD level corresponding to half of the external power supply voltage VDD level, which is generated by the half power supply voltage generation circuit.

1 is a diagram illustrating a conventional half power supply voltage generation circuit. Referring to this, the half power supply voltage generation circuit 100 includes a voltage divider 110, a bias unit 120, a push-pull current mirror amplifier 130, and an output driver unit 140. In the voltage divider 110, the first and second resistors R1 and R2 having the same resistance value are connected in series between the power supply voltage VDD and the ground voltage VSS, so that the first and second resistors R0, The connection point of R1) has a VDD / 2 voltage level.

의 전압 레벨을 갖고 제1 피모스 트랜지스터(MP0)의 게이트는

전압 레벨을 갖는다.The bias unit 120 includes a third resistor R2, a first NMOS transistor MN0, a first PMOS transistor MP0, and a fourth connected between the power supply voltage VDD and the ground voltage VSS in series. Resistor R3. The third and fourth resistors R2 and R3 have the same resistance value, and the gate and the drain of the first NMOS and PMOS transistors MN0 and MP0 are connected to each other. The gate of the first NMOS transistor MN0 is

The gate of the first PMOS transistor MP0 has a voltage level of

Has a voltage level.

The push-pull current mirror amplifier 130 may include a second PMOS transistor MP1, a second NMOS transistor MN1, a third PMOS transistor MP2 between a power supply voltage VDD and a ground voltage VSS. The third NMOS transistor MN2 is connected to the fourth NMOS transistor MP3, the fourth NMOS transistor MN3, and the fifth PMOS transistor between the power supply voltage VDD and the ground voltage VSS. MP4) and a fifth NMOS transistor MN4 are connected. The source of the second NMOS transistor MN1 and the source of the third PMOS transistor MP2 are output at the half power supply voltage VHDD.

Push-pull current mirror amplifier 130 is composed of a plurality of current mirrors, the gate of the second PMOS transistor MP1 is connected to its drain and the gate of the fourth PMOS transistor MP3 is connected to the first The gate of the first NMOS transistor MN1 is connected to the gate of the first NMOS transistor MN0 of the bias unit 120 to form a second current mirror. The gate of the third PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP0 of the bias unit 120 to form a third current mirror. The gate of the third NMOS transistor MN2 is connected to the drain thereof and is connected to the gate of the fifth NMOS transistor MN4 to form a fourth current mirror. The gate of the fourth NMOS transistor MN3 is connected to its drain, and the gate of the fifth PMOS transistor MP4 is connected to its drain. The gate of the fifth PMOS transistor MP4 is connected to the gate of the sixth NMOS transistor MN5 to form a fifth current mirror. The gate of the fourth NMOS transistor MN3 is connected to the gate of the sixth PMOS transistor MP5 to form a sixth current mirror.

The output driver 140 includes a sixth NMOS transistor MN5 and a sixth PMOS transistor MP5 connected in series between the power supply voltage VDD and the ground voltage VSS, and includes a sixth NMOS transistor ( The source of MN5 and the source of sixth PMOS transistor MP5 are generated with half power supply voltage VHDD.

에 비례하고, 최대 풀-다운 전류는

에 비례한다.The half power supply voltage VHDD generated by the half power supply voltage generation circuit 100 is a pull-up current flowing through the sixth NMOS transistor MN5 of the output driver 140 and the sixth PMOS transistor MP5. It is determined by the pull-down current flowing through Maximum pull-up current is

Proportional to, the maximum pull-down current is

Proportional to

Meanwhile, as the capacity of the memory device increases, the length of the bit line BL becomes longer and the number of memory cells connected to the cell plate increases, so that the load capacitance of the bit line and the cell plate increases. In addition, the pull-up current and the pull-down current, which are driving currents of the output driver 140, are reduced due to the low power operation of the memory device. The reduced drive current takes considerable time to generate the half supply voltage connected to the cell lines and bit lines with large load capacitance. That is, the response characteristic of the half power supply voltage generation at power-on becomes worse.

Therefore, the presence of a half power supply voltage generator circuit for generating a half power supply voltage with a constant large drive current is required.

An object of the present invention is to provide a half power supply voltage generation circuit having a large driving current.

In order to achieve the above object, the half power supply voltage generation circuit of the present invention includes a reference voltage generator for generating first and second reference voltages from the power supply voltage; A first comparator comparing the first reference voltage and a half power supply voltage; A second comparator comparing the second reference voltage and the half power supply voltage; A first path portion generating a first driving signal in response to an inversion signal of the first comparator output signal and a second comparator output and a second driving signal in response to an inversion signal of the second comparator output signal and the first comparator output A short circuit prevention circuit portion having a second path portion for generating a; An output driver unit generating the half power supply voltage pulled up and down from the power supply voltage and the ground voltage in response to the first and second driving signals; And a voltage divider for dividing the power supply voltage to generate the half power supply voltage corresponding to half of the power supply voltage level.

Therefore, in the half power supply voltage generating circuit of the present invention, the driving current of the pull-up current and the pull-down current for the half power supply voltage flows constantly, and the pull-up transistor and the pull-down transistor are simultaneously driven by a short circuit prevention circuit. Since the power supply voltage is turned on to prevent the power supply voltage and the ground voltage from being shorted, the half power supply voltage is stably generated.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a diagram illustrating a half power supply voltage generation circuit according to an embodiment of the present invention. Referring to this, the half power supply voltage generation circuit 200 includes a reference voltage generation circuit 210, a first comparator 220, a second comparator 222, a short circuit prevention circuit 230, an output driver 260, and A voltage divider 270.

The reference voltage generator circuit 210 includes first to third resistors R1, R2, and R3 connected in series between the power supply voltage VDD and the ground voltage VSS. The connection point of the first resistor R1 and the second resistor R2 is generated as the first reference voltage VREFU, and the connection point of the second resistor R2 and the third resistor R3 is the second reference voltage VREFL. Is caused by. The first reference voltage VREFU and the second reference voltage VREFL are represented as follows.

That is, the first reference voltage VREFU has a higher voltage level than the second reference voltage VREFL.

The first comparator 220 compares the first reference voltage VREFU and the half power supply voltage VHDD, and the second comparator 222 compares the second reference voltage VREFL and the half power supply voltage VHDD. When the half power supply voltage VHDD level is higher than the first reference voltage VREFU level, the first and second comparators 220 and 222 generate an output of a logic “H” level. If the half power supply voltage VHDD level is lower than the second reference voltage VREFL level, the outputs of the first and second comparators 220 and 222 are generated at a logic “L” level. When the half power supply voltage VHDD level is between the first reference voltage VREFU level and the second reference voltage VREFL level, the first comparator 220 output is at a logic “L” level and the second comparator 222. ) Output is generated at logic "H" level.

The short circuit protection circuit 240 is divided into the first path part 240 and the second path part 250. The first path unit 240 generates the first driving signal DS1 in response to an inverted signal of the output of the first comparator 220 and the output of the second comparator 222. The second path unit 250 generates a second driving signal DS2 in response to an inverted signal of the output of the second comparator 222 and the output of the first comparator 220.

In detail, the first path unit 240 inputs a first inverter 241 for inputting the output of the first comparator 220 and a NAND gate for inputting the output of the second comparator 222 inverted from the output of the first inverter 241. 242, a second inverter 243 for inputting the NAND gate 242 output, and a third inverter 244 for inputting the output of the second inverter 243 to output the first driving signal DS1. . The second path unit 250 receives a first inverter 251 for inputting the output of the second comparator 222 and a NAND gate 252 for inputting the output of the first comparator 220 inverted from the output of the first inverter 251. , A second inverter 253 for inputting the output of the NOR gate 252, and a third inverter 254 for inputting the output of the second inverter 253 to output the second driving signal DS2.

The output driver 260 includes a PMOS transistor 261 and an NMOS transistor 262 connected in series between the power supply voltage VDD and the ground voltage VSS. The gate of the PMOS transistor 261 is connected to the first driving signal DS1, the gate of the NMOS transistor 262 is connected to the second driving signal DS2, and the drain and the MOS of the PMOS transistor 261 are connected. The drain of the transistor 262 becomes the half power supply voltage VHDD.

PMOS transistors 271 and 272 of the diode type having the same resistance value are connected to the voltage divider 270 between the power supply voltage VDD and the ground voltage VSS. In the first PMOS transistor 271, a power supply voltage VDD is connected to a source thereof, a gate thereof, and a drain thereof are connected to each other, and is connected to a half power supply voltage VHDD. The second PMOS transistor 272 has a drain and a gate thereof connected to a ground voltage VSS, and a source thereof connected to a half power supply voltage VHDD.

The operation of the half power voltage generator 200 is as follows.

에 비례한다.First, when the half power supply voltage VHDD level is higher than the first reference voltage VREFU level, the output C1 of the first comparator 220 is generated at a logic " H " level and the second comparator 222 Output C2 is generated at a logic " H " level. In response to the first comparator 220 output C1 having a logic “H” level, the first driving signal DS1, which is an output of the short circuit protection circuit 230, is generated at a logic “H” level. The PMOS transistor 261 of the output driver 260 is turned off in response to the first driving signal DS1 having a logic "H" level. By the second comparator 222 output C2 at the logic " H " level, the inverter 251 output is brought to the logic " L " level, and by the first comparator 220 output C1 at the logic " H " level. The output of inverter 241 is at a logic "L" level. In response to the output of the inverters 241 and 251 having the logic "L" level, the second driving signal DS2 which is the output of the short circuit protection circuit 230 is generated at the logic "H" level. The NMOS transistor 262 of the output driver 260 is turned on in response to the second driving signal DS2 having the logic "H" level. The turned-on NMOS transistor 262 causes the half power supply voltage VHDD to be pulled down to lower its voltage level. At this time, the pull-down current is

Proportional to

에 비례한다.Second, when the half power supply voltage VHDD level is lower than the second reference voltage VREFL level, the output C1 of the first comparator 220 is generated at a logic “L” level and the second comparator 222 Output C2 is generated at a logic "L" level. In response to the second comparator 222 output C2 at the logic “L” level, the second driving signal DS2, which is an output of the short circuit protection circuit 230, is generated at the logic “L” level. The NMOS transistor 262 of the output driver 260 is turned off in response to the second driving signal DS2 having a logic “L” level. The output of the inverter 241 is brought to the logic "H" level by the first comparator 220 output C1 at the logic "L" level, and the output C2 by the second comparator 222 at the logic "L" level. The output of the inverter 251 is at a logic "H" level. In response to the output of the inverters 241 and 251 having the logic "H" level, the first driving signal DS1, which is the output of the short circuit protection circuit 230, is generated at the logic "L" level. The PMOS transistor 261 of the output driver 260 is turned on in response to the first driving signal DS1 having a logic “L” level. The turned-on PMOS transistor 261 causes the half power supply voltage VHDD to be pulled up to raise its voltage level. The pull-up current at this time

Proportional to

Third, when the half power supply voltage VHDD level is lower than the first reference voltage VREFU level and higher than the second reference voltage VREFL level, the output C1 of the first comparator 220 is at a logic “L” level. And the output C2 of the second comparator 222 is generated at a logic " H " level. The output of the inverter 251 is brought to the logic "L" level by the second comparator 222 output C2 of the logic "H" level so that the first drive signal DS1, which is the output of the short circuit protection circuit 230, is the logic "H" level. H " level. The output of the inverter 241 becomes the logic "H" level by the first comparator 220 output C1 of the logic "L" level, so that the second drive signal DS2, which is the output of the short-circuit prevention circuit 230, is the logic "L" level. Occurs at the L "level. In response to the first driving signal DS1 having a logic "H" level, the PMOS transistor 261 of the output driver unit 260 is turned off and in response to the second driving signal DS2 having a logic "L" level. The NMOS transistor 262 of the output driver 260 is turned off. Accordingly, the half power supply voltage VHDD is generated at the voltage level corresponding to half of the power supply voltage VDD by the voltage divider 270.

On the other hand, when the half power supply voltage VHDD level is between the first reference voltage VREFU level and the second reference voltage VREFL level, the output C1 of the first comparator 220 is normally at a logic “L” level. Is generated and the output C2 of the second comparator 222 should be generated at a logic "H " level, but the output of the first comparator 220 is affected by the offset voltage of the comparators 220 and 222. Level, and the output of the second comparator 222 may be abnormally generated at a logic "L" level. Even in this case, the first driving signal DS1 of the short circuit protection circuit 230 is generated at a logic "H" level, and the second driving signal DS2 is generated at a logic "L" level, thereby operating the output driver 260. To block. That is, both the PMOS transistor 261 and the NMOS transistor 262 of the output driver 260 are turned on at the same time to prevent a short circuit between the power supply voltage VDD and the ground voltage VSS.

) 분포는 도 3에 도시되어 있다. 이를 참조하면, 전원 전압(VDD)이 1.5V 정도 저전압일 때 하프 전원 전압(VHDD)은 0.75V 정도로 잡힌다. 하프 전원 전압(VHDD)이 0.75V 이하인 구간에서는 150mA 정도의 풀-업 전류가 일정하게 흐르고, 하프 전원 전압(VHDD)이 0.75V 이상인 구간에서는 150mA 정도의 풀-다운 전류가 일정하게 흐른다.The pull-up current and the pull-down current according to the level of the half power voltage VHDD generated by the half power voltage generation circuit 200, that is, the driving current (

) Distribution is shown in FIG. 3. Referring to this, when the power supply voltage VDD is about 1.5V low, the half power supply voltage VHDD is about 0.75V. In the section where the half power supply voltage VHDD is 0.75V or less, a pull-up current of about 150mA flows constantly, and in the section where the half power supply voltage VHDD is 0.75V or more, a pull-down current of about 150mA flows constantly.

This is because the pull-up current and the pull-down current flowing to generate the half power voltage VHDD in the half power voltage generation circuit 100 of FIG. 1 are farther away from the 0.75V level of the half power voltage VHDD. Compared with a large flow rate and near 0.75V, the smaller the flow rate, the smaller the driving capability is. In other words, the driving current for generating the half power supply voltage of this embodiment flows stably and stably.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, diode-connected NMOS transistors may be substituted for diode-connected PMOS transistors 271 and 272 in the voltage divider 270 as well as passive elements or active elements having the same resistance value. It will be apparent to those skilled in the art. Although the power supply voltage VDD applied to the circuit has been described in the embodiment of the present invention, the operation principle of the circuit will be the same even if another DC voltage, for example, an internal power supply voltage is applied instead of the power supply voltage. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the half power supply voltage generation circuit of the present invention described above, the driving current of the pull-up current and the pull-down current for the half power supply voltage is constantly flowing, and the pull-up transistor and the pull-down transistor are simultaneously driven by a short circuit prevention circuit. Since the power supply voltage is turned on to prevent the power supply voltage and the ground voltage from being shorted, the half power supply voltage is stably generated.

Claims (9)

delete delete A reference voltage generator configured to generate first and second reference voltages from a power supply voltage; A first comparator comparing the first reference voltage and a half power supply voltage; A second comparator comparing the second reference voltage and the half power supply voltage; A first path portion generating a first driving signal in response to an inversion signal of the first comparator output signal and a second comparator output and a second driving signal in response to an inversion signal of the second comparator output signal and the first comparator output A short circuit prevention circuit portion having a second path portion for generating a; An output driver unit generating the half power supply voltage pulled up and down from the power supply voltage and the ground voltage in response to the first and second driving signals; And And a voltage divider for dividing the power supply voltage to generate the half power supply voltage corresponding to half of the power supply voltage level. The method of claim 3, wherein the first path portion A first inverter for inputting an output of the first comparator; A NAND gate configured to input an output of the first inverter and an inverted second comparator output; A second inverter configured to input an output of the NAND gate; And And a third inverter configured to input an output of the second inverter to output the first driving signal. The method of claim 3, wherein the second path portion A first inverter for inputting an output of the second comparator; A noah gate for inputting the output of the first inverter and the inverted first comparator output; A second inverter for inputting an output of the noah gate; And And a third inverter configured to input an output of the second inverter to output the second driving signal. delete delete The method of claim 3, wherein the voltage divider A first resistor element having a predetermined resistance value and connected between the power supply voltage and the half power supply voltage; And And a second resistor element having a resistance value equal to that of the first resistor element and connected between the half power voltage and the ground voltage. The method of claim 3, wherein the voltage divider A first PMOS transistor having a source connected to the power supply voltage and a gate and a drain thereof connected to the half power supply voltage; And And a second PMOS transistor whose source and gate are connected to the ground voltage and whose drain is connected to the half power voltage.

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