JP2001127609A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power-on reset circuit that can reduce a temperature characteristic of a reset release voltage caused by a temperature characteristic of a threshold voltage of a MOS transistor(TR) and enhance the accuracy of a power-on reset operation. SOLUTION: A first detection circuit 11 uses resistor R11, R12 or the like to divide a voltage of a power supply and gives the divided voltage to a gate of an NMOS TR N2. A first detection circuit 12 uses resistor R14, R15 or the like to divide the voltage of the power supply and gives the divided voltage to a gate of a PMOS TR P2. A ratio of the resistance of the resistors R11, R12 is selected so that a power supply voltage (reset release voltage) is a voltage resulting from adding a permissible voltage α to a threshold voltage when a gate voltage of the NMOS TR N2 reaches the threshold voltage, e.g. 1:8. This is applied also to the case with the resistors R14, R15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit for generating a reset signal for initializing each part of a system driven by a power supply when the power supply rises, and more particularly to a power-on reset circuit operating at a low voltage. It is related to the circuit.

[0002]

2. Description of the Related Art Conventionally, as an example of this type of power-on reset circuit, the one shown in FIG. 3 is known.

This power-on reset circuit, as shown in FIG. 3, uses a resistor R1 and a resistor R2 to generate a power supply voltage VD.
D1 is divided, and the divided voltage is supplied to the gate of the NMOS transistor N1. The source of the NMOS transistor (N-channel MOS transistor) N1 is grounded, and the drain thereof is a PMOS transistor (P
The channel MOS transistor P1 is connected to its drain, and an output is taken out from this common connection. The PMOS transistor P1 has a gate grounded, a source connected to a power supply, and supplied with a power supply voltage VDD1.

In the conventional power-on reset circuit having such a configuration, the power supply voltage V
When DD1 reaches the threshold voltage of the PMOS transistor P1, the PMOS transistor P1 conducts and the output goes to "H" level. Thereafter, when the divided voltage divided by the resistors R1 and R2 reaches the threshold voltage of the NMOS transistor N1, the NMOS transistor N1 conducts, and its output changes from "H" level to "L" level. I do. Therefore, the power supply voltage when the divided voltage reaches the threshold voltage becomes the reset release voltage for releasing the reset.

As described above, in the conventional low-voltage power-on reset circuit, the reset release voltage is determined by adjusting the threshold voltage of the NMOS transistor N1 by dividing the threshold voltage with the resistors R1 and R2.

[0006]

However, the temperature characteristic of the threshold voltage of the NMOS transistor N1 is -2 to 3
Since the threshold voltage is about [mV / ° C.], if the threshold voltage fluctuates with temperature, the fluctuation of the reset release voltage accompanying the fluctuation is (R1 + R2) / R1 times. Where R
1 is the resistance value of the resistor R1, and R2 is the resistance value of the resistor R2.

For example, when the reset release voltage is 0.85
[V] When the resistance values of the resistors R1 and R2 are set so that the threshold voltage of the NMOS transistor N1 becomes 0.35 [V], the temperature characteristic of the reset release voltage is as follows. (0.85
/0.35)=2.42 times, -5 to 7 [mV / °
C]. For this reason, -2 to normal temperature 25 ° C
In the range of 0 ° C. to 70 ° C., the reset release voltage is set to 0.
It becomes a large fluctuation of 25 to 0.35 [V], and it is desired to reduce this fluctuation.

Therefore, an object of the present invention is to reduce the temperature characteristic of the reset release voltage caused by the temperature characteristic of the threshold voltage of the MOS transistor, and to further improve the accuracy and stability of the power-on reset operation. An object of the present invention is to provide a power-on reset circuit as described above.

[0009]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, the respective inventions according to claims 1 to 4 are configured as follows.

According to a first aspect of the present invention, there is provided a power-on reset circuit for generating a reset signal when a power supply rises, the power-on reset circuit being connected between the power supply and a ground, and including a MOS transistor for generating the reset signal. Voltage dividing means for dividing the voltage of the power supply by a first resistor and a second resistor, and supplying the divided voltage to the gate of the MOS transistor. The voltage dividing ratio of the voltage dividing means is equal to the gate of the MOS transistor. Is set to be a voltage obtained by adding a permissible voltage to the threshold voltage when the reset release voltage becomes a threshold voltage.

According to the first aspect of the present invention, when the voltage dividing ratio of the voltage dividing means becomes equal to the threshold voltage of the gate of the MOS transistor, the reset release voltage corresponding to the threshold voltage becomes smaller. The threshold voltage is set to be a voltage obtained by adding the allowable voltage. Therefore, according to the present invention, the temperature characteristic of the reset release voltage caused by the temperature characteristic of the threshold voltage of the MOS transistor can be reduced.

According to a second aspect of the present invention, there is provided a power-on reset circuit for generating a reset signal when a power supply rises, the NMO being connected between the power supply and ground.
An S transistor; a first detecting unit having a first voltage dividing unit that divides a voltage of the power supply by a first resistor and a second resistor and supplies a divided voltage to a gate of the NMOS transistor; PMO connected between ground
A second detecting unit including an S transistor, a second voltage dividing unit that divides a voltage of the power supply by a third resistor and a fourth resistor, and supplies a divided voltage to a gate of the PMOS transistor; Output means for outputting a signal related to generation of the reset signal based on both outputs of the PMOS transistor.

According to a third aspect of the present invention, in the power-on reset circuit according to the second aspect, when both the NMOS transistor and the PMOS transistor are turned on, the output stage outputs a signal to that effect. Is what you do.

According to the second or third aspect of the present invention, since the reset release voltage is detected by both the NMOS transistor and the PMOS transistor, the accuracy and stability of the power-on reset are improved. I do.

According to a fourth aspect of the present invention, in the power-on reset circuit according to the third aspect, the voltage dividing ratio of the first voltage dividing means is determined when the gate of the NMOS transistor reaches a threshold voltage. , The corresponding reset release voltage is set to a voltage obtained by adding an allowable voltage to the threshold voltage, and the voltage dividing ratio of the second voltage dividing means is
When the gate of the MOS transistor reaches a threshold voltage, a reset release voltage corresponding to the threshold voltage is set to a voltage obtained by adding an allowable voltage to the threshold voltage. is there.

According to the fourth aspect of the present invention, since the voltage dividing ratio of the first voltage dividing means and the voltage dividing ratio of the second voltage dividing means are set as described above, the power-on reset is performed. And the temperature characteristics of the reset release voltage can be reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a power-on reset circuit according to an embodiment of the present invention.

As shown in FIG. 1, the power-on reset circuit according to this embodiment includes a first detection circuit 1 that detects that a reset release voltage has been reached by an NMOS transistor N2 and a first detection circuit 1 that has reached a reset release voltage. A second detection circuit 2 for detecting with a PMOS transistor P2; a logic circuit 3 for performing a logical AND operation of both outputs of the first and second detection circuits 1 and 2; and a reset signal based on the output of the logic circuit 3 And an output circuit 4 for generating and outputting.

In the first detection circuit 1, as shown in FIG. 1, a resistor R11, a resistor R12, and a hysteresis resistor Rh1 are connected in series between a power supply and ground, thereby dividing the power supply voltage VDD1. A voltage divider circuit is formed. The common connection between the resistors R11 and R12 is
It is connected to the gate of S transistor N2, and its source is grounded. The drain of the NMOS transistor N2 is connected to the power supply via the resistor R13 and to the input side of the inverter 10. The common connection between the resistor R12 and the resistor Rh1 is an NMOS transistor N
3 is connected to the drain. The gate of the NMOS transistor N3 is connected to the drain of the NMOS transistor N2, and the source is grounded.

Here, the ratio of the resistance values of the resistors R11 and R12 is determined by the value of the power supply voltage (reset release voltage) when the gate voltage of the NMOS transistor N2 reaches the threshold voltage. The threshold voltage is set to be a voltage obtained by adding an allowable voltage, and for example, is set to be 1: 8.

The reason for setting the ratio in this manner is that NM
This is to reduce the temperature characteristic of the reset release voltage caused by the temperature characteristic (temperature dependence) of the threshold voltage of the OS transistor N2 to an allowable range. Since the threshold voltage varies due to the manufacturing of the NMOS transistor, it is desirable to determine the ratio in consideration of these points.

As shown in FIG. 1, the second detection circuit 2 includes a hysteresis resistor Rh2 and a resistor R1 between a power supply and ground.
5, and the resistor R14 are connected in series, thereby forming a voltage dividing circuit for dividing the power supply voltage VDD1. A common connection between the resistors R14 and R15 is a PMO
The source of the S transistor P2 is connected to a power supply, and the source thereof is connected to a power supply so that the power supply voltage VDD1 is supplied. The drain of the PMOS transistor P2 is
It is grounded via a resistor R16 and is connected to the input terminal of the AND gate 11. Resistance Rh2 and resistance R
Fifteen common connection parts are connected to the drain of the PMOS transistor P3. The gate of the PMOS transistor P3 is connected to the drain of the PMOS transistor P2, and its source is connected to a power supply so that a power supply voltage is supplied.

Here, the ratio between the resistance values of the resistors R14 and R15 is such that when the gate voltage of the PMOS transistor P2 reaches the threshold voltage, the reset release voltage at that time is equal to the allowable voltage , And is set to, for example, 1: 8.

The reason for setting the ratio in this way is that PM
This is to reduce the temperature characteristic of the reset release voltage due to the temperature characteristic of the threshold voltage of the OS transistor P2 to an allowable range. The threshold voltage is PMOS
Since there is variation due to the manufacture of the transistor, it is desirable to determine the ratio in consideration of these points.

The logic circuit 3 has a two-input AND gate 11
And an inverter 12, which are connected in series. Specifically, the AND gate 11 has one input side connected to the output side of the inverter 10 and the other input side connected to the drain of the PMOS transistor P2. The output side of the AND gate 11 is connected to the input side of the inverter 12, and the output side of the inverter 12 is connected to each gate of the PMOS transistor P4 and the NMOS transistor N4.

The output circuit 4, as shown in FIG.
It comprises a CMOS inverter composed of an S transistor P4 and an NMOS transistor N4, a capacitor C1, a Schmitt trigger circuit 13, an amplifier (amplifier) 14, and the like.

More specifically, the gate of the PMOS transistor P4 and the gate of the NMOS transistor N4 are commonly connected, and this common connection is connected to the output side of the inverter 12. The source of the PMOS transistor P4 is connected to the power supply, and the drain thereof is connected to the resistor R17.
Is connected to the drain of the NMOS transistor N4. The source of the NMOS transistor N4 is grounded. The drain of the NMOS transistor N4 is
It is connected to the input side of the Schmitt trigger circuit 13 and is grounded via the capacitor C1. The output side of the Schmitt trigger circuit 13 is connected to the input side of the amplifier 14 so as to take out the output from the output side of the amplifier 14.

Next, the operation of the power-on reset circuit according to the embodiment having the above configuration will be described with reference to FIG.

Now, when the power supply voltage VDD1 starts to rise, in the first detection circuit 1, the NMOS transistor N2 operates until the gate voltage of the NMOS transistor N2 reaches the threshold voltage.
MOS transistor N2 is turned off (off). Therefore, until the gate voltage becomes the threshold voltage, the drain voltage V1 of the NMOS transistor N2 is used.
Increase in accordance with the rise of the power supply voltage VDD1. Since the voltage V1 is applied to the gate of the NMOS transistor N3, the NMOS transistor N3 becomes conductive when the voltage reaches the threshold voltage. As a result, both ends of the hysteresis resistor Rh1 are short-circuited, and the power supply voltage VDD1 is divided by the resistors R11 and R12.

On the other hand, when the power supply voltage VDD1 starts to rise, in the second detection circuit 2, the PMOS transistor P2 operates until the gate voltage of the PMOS transistor P2 reaches the threshold voltage.
MOS transistor P2 is turned off. Therefore, until the power supply voltage VDD1 reaches the threshold voltage, the drain voltage V
2 becomes the earth voltage and becomes 0 [V]. Its voltage V
2 is applied to the gate of the PMOS transistor P3.
Transistor P3 conducts. As a result, both ends of the hysteresis resistor Rh2 are short-circuited, and the power supply voltage VDD1 is divided by the resistors R14 and R15.

Thereafter, when the power supply voltage VDD1 rises and the gate voltage of the NMOS transistor N2 reaches the threshold voltage, the NMOS transistor N2 conducts, and the value of the power supply voltage VDD1 at this time becomes the reset release voltage. On the other hand, when the power supply voltage VDD1 rises and the gate voltage of the PMOS transistor P2 reaches the threshold voltage, the PMOS transistor P2 becomes conductive,
The value of the power supply voltage VDD1 at this time becomes the reset release voltage.

By the conduction of the NMOS transistor N2, N
The MOS transistor N3 is turned off, and the voltage is applied to the hysteresis resistor Rh1 after the short-circuit state is released, and the applied voltage increases the gate voltage of the NMOS transistor N2, thereby increasing the NMOS transistor N2.
Operation can be stabilized. On the other hand, the PMOS transistor P3 is turned off by the conduction of the PMOS transistor P2, and the voltage is applied to the hysteresis resistor Rh2 after the short-circuit state is released. Therefore, the applied voltage lowers the gate voltage of the PMOS transistor P2, and the PMO
The operation of the S transistor P2 can be stabilized.

Further, the drain of the NMOS transistor N2 becomes 0 [V] due to the conduction of the NMOS transistor N2 and becomes the "L" level. This is inverted by the inverter 10 to become the "H" level. 11 is input to one of the input terminals. On the other hand, due to the conduction of the PMOS transistor P2, the drain thereof becomes the power supply voltage VDD1 and becomes “H” level, and this “H” level is inputted to the other input terminal of the AND gate 11.

As described above, the output of the AND gate 11 becomes "H" level when both inputs become "H" level. This "H" level is inverted by the inverter 12 to become "L" level, whereby the gate voltages of both the PMOS transistor P4 and the NMOS transistor N4 become 0 [V]. As a result, the PMOS transistor P4 becomes conductive, and the NMOS transistor N4
Becomes non-conductive, the capacitor C1 is connected to the power supply voltage V
It is charged by DD1.

When the charging voltage exceeds a predetermined voltage (upper limit) of the Schmitt trigger circuit 13, the output of the Schmitt trigger circuit 13 changes from "L" level to "H" level. It is amplified and output as a reset signal.

As described above, in this embodiment,
The ratio between the resistance value of the resistor R11 and the resistance value of the resistor R12 was set as described above, and the ratio between the resistance value of the resistor R14 and the resistance value of the resistor R15 was set as described above. Therefore, in this embodiment, the temperature characteristics of the reset release voltage caused by the temperature characteristics of the threshold voltages of the NMOS transistor N2 and the PMOS transistor P2 can be reduced, and the reset release voltage can be set low.

For example, the threshold voltage of the NMOS transistor N2 at room temperature (25 ° C.) is 0.55
[V], the ratio of the resistance values of the resistors R11 and R12 is 1:
The temperature characteristic of the reset release voltage when it is set to 8 is represented by a solid line B shown in FIG. A solid line A shown in FIG. 2 indicates that the reset release voltage is 0.85 [V] and NM in the circuit of FIG.
The threshold voltage of the OS transistor N1 is 0.55 [V]
This is a temperature characteristic of the reset release voltage when the resistance values of the resistors R1 and R2 are set so as to be as follows. As can be seen from FIG. 2, the temperature characteristic of the reset release voltage can be significantly reduced in this embodiment as compared with the conventional example. Specifically, NMO
9/8 of temperature characteristic of threshold voltage of S transistor N2
Can be reduced by a factor of two.

In this embodiment, the reset release voltage is detected by both the NMOS transistor N2 and the PMOS transistor P2, and a reset signal is generated on condition that both of them are detected. The accuracy and stability of reset can be improved.

Further, in this embodiment, the reset release voltage itself depends on the variation in the threshold voltage of the MOS transistors N2 and P2.
Since the voltage obtained by adding the allowable voltage α to the threshold voltage of P2 is used as the reset release voltage, there is no problem in the power-on reset function.

In the above embodiment, the first detection circuit 1, the second detection circuit 2, the logic circuit 3, and the output circuit 4 are used. However, in order to improve the temperature characteristics of the reset release voltage, only one of the first detection circuit 1 and the second detection circuit 2 may be used. In this case, the logic circuit 3 can be omitted.

[0042]

As described above, according to the first aspect of the present invention, when the voltage dividing ratio of the voltage dividing means becomes the threshold voltage of the gate of the MOS transistor, the reset release corresponding to the threshold voltage is performed. The voltage is set to be a voltage obtained by adding an allowable voltage to the threshold voltage. Therefore, according to the present invention, the temperature characteristic of the reset release voltage caused by the temperature characteristic of the threshold voltage of the MOS transistor can be reduced.

According to the second or third aspect of the present invention, the reset release voltage is set between the NMOS transistor and the PMO.
Since the detection is performed by both the S transistors, the accuracy and stability of the power-on reset are improved.

According to the fourth aspect of the invention, since the voltage dividing ratio of the first voltage dividing means and the voltage dividing ratio of the second voltage dividing means are set as described above, the accuracy and stability of the power-on reset are improved. The temperature characteristic of the reset release voltage can be reduced while improving the performance.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power-on reset circuit according to an embodiment of the present invention.

FIG. 2 is a diagram comparing a conventional example and an example of temperature characteristics of a reset release voltage.

FIG. 3 is a circuit diagram of a conventional power-on reset circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st detection circuit 2 2nd detection circuit 3 logic circuit 4 output circuit 10 inverter 11 AND gate 12 inverter 13 Schmitt trigger circuit 14 amplifier

Claims (4)

[Claims] 1. A power-on reset circuit that generates a reset signal when a power supply rises, wherein the power-on reset circuit is connected between the power supply and a ground, and a MOS transistor for generating the reset signal; Voltage dividing means for dividing the voltage by the first resistor and the second resistor and supplying the divided voltage to the gate of the MOS transistor, wherein the voltage dividing ratio of the voltage dividing means is such that the gate of the MOS transistor has a threshold voltage. A reset release voltage corresponding to the threshold voltage is set to a voltage obtained by adding an allowable voltage to the threshold voltage. 2. A power-on reset circuit for generating a reset signal when a power supply rises, comprising: an NMOS transistor connected between the power supply and a ground; and a voltage of the power supply being controlled by a first resistor and a second resistor. First detecting means having first voltage dividing means for dividing the voltage and supplying the divided voltage to the gate of the NMOS transistor; a PMOS transistor connected between the power supply and the ground; A second detecting unit having a second voltage dividing unit that divides a voltage by a third resistor and a fourth resistor and supplies the divided voltage to a gate of the PMOS transistor; based on both outputs of the NMOS transistor and the PMOS transistor, A power-on reset circuit, comprising: output means for outputting a signal related to generation of the reset signal. 3. The power-on reset circuit according to claim 2, wherein the output stage outputs a signal to that effect when both the NMOS transistor and the PMOS transistor are turned on. . 4. A pressure-dividing ratio of said first pressure-dividing means is NM
When the gate of the OS transistor reaches a threshold voltage, a reset release voltage corresponding to the threshold voltage is set to be a voltage obtained by adding an allowable voltage to the threshold voltage. The voltage ratio is set so that when the gate of the PMOS transistor becomes a threshold voltage, a reset release voltage corresponding to the threshold voltage becomes a voltage obtained by adding an allowable voltage to the threshold voltage. The power-on reset circuit according to claim 2 or 3, wherein