JPH02254811A - Reset circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an externally mounted component such as an externally mounted terminal or capacitor and to attain miniaturization by connecting a resistor, a MOSFET and a resistor in series between a power supply and ground, using a connecting point between a drain of a MOSFET and a resistor as an input of inverters of 2-stage connection, connecting the gate of the MOSFET to a power supply, and connecting a back gate to ground. CONSTITUTION:At application of power supply, since a transistor(TR) (MOSFET) M1 is turned off and a voltage VB rises with a power supply voltage VDD as shown in a waveform D. Then a threshold level of an inverter reaches 1/2.VDD and an output Vout goes to a high level. When the power supply voltage VDD sufficiently rises and a TR M1 is turned on, the voltage VB reaches a value R2/R1+R2.VDD set by resistors R1 and R2. The voltage reaches ao inverter threshold level or below and the output Vout goes to a low level, reset is applied automatically at application of power supply. The voltage VB is outputted via a buffer and the output Vout is a reset signal subject to waveform shaping.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset circuit that resets a logic circuit to an initial state when power is turned on.

[Conventional technology]

Figure 3 is a conventional reset circuit, and Figure 4 is an operating waveform diagram of the conventional reset circuit.

In FIG. 3, R3 is a resistor, C1 is a capacitor, and both are externally connected in series between the power supply and the ground.
The connection point between the capacitor C1 and the capacitor C1 is connected to the input terminal of the IC. Further, as an input protection circuit, a diode D1 whose anode is connected to the input terminal and whose cathode is connected to the power supply is connected.

In this reset circuit, when the power is turned on, charging of the capacitor C1 is started as shown in FIG. 3, and the voltage VA at the input terminal becomes a waveform F that rises with a time constant. If this signal is input to the reset terminal of the logic circuit via the inverter, the power supply voltage will be the threshold voltage of the inverter v
After reaching th, until the input terminal V reaches vth, a reset signal of ``H'' is maintained, and the logic circuit is reset.

[Problem to be solved by the invention]

Conventional reset circuits were configured as described above. Therefore, in general, in analog/logic mixed ICs, a dedicated time constant is provided using external components as a logic circuit reset circuit. Afterwards, it was reset for a certain period of time.

Therefore, there is a problem in that a capacitor for providing a time constant and an external terminal are required.

This invention was made to solve the above-mentioned problems, and aims to provide a reset circuit that can give a reset signal without using external parts such as terminals and capacitors. purpose.

[Means to solve the problem]

The reset circuit according to the present invention has V! 1 resistor and MOSFET 1 resistor are connected in series between the 1 source and the ground, the connection point between the drain of the MOSFET and the resistor is used as the input of an inverter connected in 2 stages, the gate of the MOSFET is connected to the power supply, and the back gate is grounded. This is what I did.

[Operation] The reset circuit in this invention has a resistance value, a MOSFET
and the threshold of the inverter are appropriately selected, and 1
! The output of the second-stage inverter remains high until the power is sufficiently raised and the MOSFET is turned on, and then becomes low after the power is turned on, so that the output is automatically reset when the power is turned on.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a reset circuit showing one embodiment of the present invention, and FIG. 2 is an operational waveform diagram of the reset circuit shown in FIG. 1.

In Figure 1, R1 and R2 are resistors, and Ml is a MOSFE.
T, If, and I2 are inverter circuits. The vths of R1, R2 and Mt are set so as to satisfy the following relationships (Equations 1 and (2)).

...(1) and ...(2) With settings that satisfy these conditions, each voltage waveform when the power is turned on becomes as shown in FIG. 2. Figure 2 shows the voltage waveform of In vB, and E is Vou whose waveform has been shaped by the buffer.
t is a reset signal waveform.

When the power is turned on, the transistor (MO8FE'r) Ml
1. Since t is off, the voltage of V9 rises with the power supply voltage VDD as shown in the waveform, and the inverter threshold voltage - V
DD or higher, the output Vout becomes ``High'', and the power supply voltage VDD rises enough to turn on the transistor Ml. L.O.
! ', so it is automatically reset when the 11E power is turned on. By outputting the vB signal via a buffer, the output Vout becomes a waveform-shaped reset signal.

〔Effect of the invention〕

As described above, according to the present invention, external parts such as terminals and capacitors are not required, and elements that require area such as capacitors are not required in the circuit configuration, so the reset circuit can be made very small. Can be configured.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a reset circuit according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the reset circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional reset circuit, and FIG. The figure is an operational waveform diagram of the reset circuit of FIG. 3. In the figure, R1 and R2 are resistors, Ml is MOSFET, II
, I2 indicates an inverter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] a first resistor connected in series between the power supply and ground; a first MO;
an SFET, a second resistor, a first inverter whose input is connected to a connection point between the first resistor and the first MOSFET, and whose output is a reset signal having a phase opposite to that of the input; and the first inverter. a second inverter, the input of which is connected to the output of the second inverter, the output of which is a reset signal;
The gate of the OSFET is connected to a power supply, and the first MOSFET
A reset circuit in which the back gate of SFET is grounded.