JPH02165723A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent an overcurrent from flowing on an output buffer circuit by applying feedback from a flip-flop with set/reset on the base of an npn(pnp) transistor by comparing the output voltage of a CMOS transistor with a voltage decided by a current limit value. CONSTITUTION:When the output terminal 104 side of a load 105 is grounded accidentally and a current exceeding an output current limit value intends to flow, the output voltage Vo intends to go less than 3.3V. A voltage compara tor 107 compares it with a reference voltage VREF of 3.3V, and outputs 0V, therefore, inputs 5V to the set input S of the flip-flop 109, and -Q output goes to a low level, and the npn transistor Q 106 is turned off. In such a manner it is possible to prevent the damage of a P-channel transistor Qp in the CMOS transistor 101 due to the overcurrent from occurring.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an output buffer circuit.

(Prior Art) Conventionally, an output buffer circuit is composed of a CMO5, and has a mechanism that has no limit on the current supplied to or absorbed from the load when outputting a high or low level voltage.

[Problem to be solved by the invention]

The conventional output buffer circuit described above is composed of CMO5 transistors, and if an external load short-circuits to the ground side for some reason, the buffer's P-channel MOS
At the same time as the transistor turns on, a current determined only by the on-resistance of the P-channel MO5 transistor is output from its own power supply, resulting in an increase in current consumption, a heavy burden on the current system, and In the case of driving a load, there is a drawback that a limiting resistor is required at the output of the output buffer circuit in order to prevent the supply of more current than necessary and sufficient.

(Means for Solving the Problems) The output buffer circuit of the present invention includes a CMOS transistor, a high potential power supply terminal of the CMOS transistor, and a P-channel M
The output voltage of the bipolar transistor connected between the low potential power supply terminal of the OS ) transistor or CMOS transistor and the N-channel MOS t-transistor and the CMOS transistor is determined by the output current limit value of the CMOS transistor. A voltage comparator that compares the value, an inverter that inverts the output of the voltage comparator, the output of the voltage comparator and the inverted output are set and reset manually, and the output is connected to the base of a bipolar transistor (CMOS) transistor. When the output voltage does not exceed the limit value, the bipolar transistor is turned on,
It has a flip-flop that turns off the bipolar transistor when the limit value is exceeded.

[For production]

In the present invention, a bipolar transistor is connected in series to the high potential power supply terminal side or the low potential power supply terminal side of a MOS transistor, and the output voltage determined by the output current is compared with a set limit potential using a voltage comparator. If an overcurrent flows and exceeds a set limit potential, the voltage comparator detects it and operates the flip-flop in the next stage to turn off the bipolar transistor mentioned above and limit the current flowing.

Note that the bipolar transistor used in the present invention can be formed without adding any steps to the normal 0MO5 manufacturing process.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an output buffer circuit according to a first embodiment of the present invention.

This output buffer circuit consists of (:MOS) transistor 10
1 and the high potential power supply terminal +0 of the CMOS transistor 101
The collector is P-channel MOS transistor Qp at 2.
The output voltage v0 of the NPN) transistor 10B and the CMOS) transistor 101 whose emitter is connected to the source of
a voltage comparator 107 with a non-inverting input and a reference voltage V REF as an inverting input; An inverter 110 that inverts the , a set end S is connected to the input end 111 of the reset signal of the entire system and the inverter 108, a reset end R is connected to the output of the OR gate 108, and an inverting output end is connected to the input end 111 of the reset signal of the entire system and the inverter 108.
It is composed of flip-flops 109 with set/reset functions connected to the bases of transistors 106, and a load 105 is connected to an output terminal 104.

Next, the operation of the output buffer circuit of this embodiment will be explained.

Limit value iL of output current iL of this output buffer circuit
i, for example, 100 mA, and the on-resistance r of the P-channel MOS transistor Qp. Let N be 100Ω. 5■ as the power supply voltage VD to the collector of the npn transistor 106
Apply. When input terminal v1 is at low level,
A high-level output voltage v0 is output to the output terminal +04, and a load current iL is supplied to the external load 105. The reference voltage V REP is in this case the npn transistor 106
Base-emitter voltage = 5- (0,7+1) =
3. :1(V).

Normally, the buffer output current it flowing out when the P-channel MOS transistor Qp is turned on is applied to the load 105.
Assuming O+s^, the output voltage vo is 4.2■, and the voltage comparator 107 outputs 5V as the output voltage to the flip-flop 109 set R through the OR gate +08, and the flip-flop 109 outputs 5V is applied to the base of npn transistor 106. np
n) The transistor 106 thus continues to supply IC from the power supply terminal +02. Here, the output terminal lα4 side of the load 105 is accidentally grounded, causing a current exceeding the output current limit value iLL, for example l
When 01n+A tries to flow, the output voltage vo is 3
．． Trying to get below 3v. The voltage comparator 107 compares the reference voltage V□ with 3.3V and outputs Ov, and therefore outputs 5□ to the set S of the flip-flop 109, the output becomes low level, and the npn transistor 106 is turned off. do. This prevents the P-channel MOS transistor Qp of the CMOS transistor 101 described above from being destroyed by overcurrent.

FIG. 2 is a circuit diagram of an output buffer circuit according to a second embodiment of the present invention.

In this example, the npn transistor +
pnp instead of 06) The transistor 112 is a CMOS transistor + an N-channel MOS transistor Qn of 01.
A Nandt gate 113 is provided in place of the OR gate 108.

This embodiment also operates in the same way as the first embodiment to prevent overcurrent breakdown of the internal n-channel MOS transistor Qn.
) Protected by transistor 112.

This embodiment has the same effect as the first embodiment, but the first embodiment has a CMOS transistor 101 on an n-type semiconductor substrate.
In this embodiment, a CMOS transistor 101 is formed on a p-type semiconductor substrate.
and pnp) are suitable for forming the transistor 112.

(Effects of the Invention) As explained above, the present invention provides an npn (pnp) transistor between a p (n) channel MOS transistor of a CMOS transistor and a power supply,
Comparing the output voltage of the transistor and V REF determined from the current limit value, the above-mentioned npn (pnp)
Applying feedback from 5IIF/F to the base of the transistor has the effect of preventing overcurrent from flowing into the output buffer circuit.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of output buffer circuits according to first and second embodiments of the present invention, respectively. 101-101-C transistor, 102-... power supply terminal, 103.111-... input terminal, 104-... output terminal, 105... load, 106... npn transistor,... voltage comparator, ...OR gate, ...flip-flop with set/reset, ...inverter, ...pnp transistor, ...Nant gate.

Claims (1)

[Claims] 1. A CMOS transistor, a high potential power supply terminal of the CMOS transistor, and a p-channel M
The bipolar transistor connected between the low potential power supply terminal of the OS transistor or CMOS transistor and the N-channel MOS transistor and the output voltage of the CMOS transistor are compared with the output voltage limit value determined from the output current limit value of the CMOS transistor. A voltage comparator, an inverter that inverts the output of the voltage comparator, the output of the voltage comparator and the inverted output are set, the reset input is connected, the output is connected to the base of the bipolar transistor, and the CMO
An output buffer circuit comprising a flip-flop that turns on a bipolar transistor when the output voltage of the S transistor does not exceed a limit value, and turns off the bipolar transistor when the output voltage exceeds the limit value.