JPH03238365A - Low voltage detection circuit - Google Patents

Low voltage detection circuit

Info

Publication number
JPH03238365A
JPH03238365A JP3542990A JP3542990A JPH03238365A JP H03238365 A JPH03238365 A JP H03238365A JP 3542990 A JP3542990 A JP 3542990A JP 3542990 A JP3542990 A JP 3542990A JP H03238365 A JPH03238365 A JP H03238365A
Authority
JP
Japan
Prior art keywords
resistor
channel mos
low voltage
terminal
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3542990A
Other languages
Japanese (ja)
Inventor
Haruo Nishiura
晴男 西浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3542990A priority Critical patent/JPH03238365A/en
Publication of JPH03238365A publication Critical patent/JPH03238365A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/32Compensating for temperature change

Abstract

PURPOSE:To stabilize operation at a low voltage while reducing the number of elements by detecting a low voltage with one MOSFET and resistance each, only while compensation for temperature is made possible to perform a waveform shaping of outputs thereof with a buffer. CONSTITUTION:This circuit is made up of a resistor stage having a first P channel MOSFET 1 and a resistor 4, and a buffer stage having a second PMOSFET 2 and an N channel MOSFET 3. Since the FET 1 is ON when a power source terminal 5 is at a sufficiently high voltage, a low level is outputted at an output terminal 7 when a resistance value of the resistor 4 is large sufficiently. When the voltage at the terminal 5 lowers, the ON resistance of the FET 1 increases, and it exceeds the resistance value of the resistor 4 when a certain potential is reached. Thus, when the buffer stage is in operation, the signal at the terminal 7 is inverted to be a high level, and the current voltage value is detected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、定電圧検出回路に関し、特に温度補償型低電
圧検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage detection circuit, and particularly to a temperature compensated low voltage detection circuit.

〔従来の技術〕[Conventional technology]

第3図は、従来の低電圧検出回路の一例である。 FIG. 3 is an example of a conventional low voltage detection circuit.

第3図の電圧検出回路は16のCMOSオペアンプ、抵
抗R1,R2,R3、及び12のバイポーラトランジス
タのコレクタとベースをショートさせたダイオード6個
により構成されている。
The voltage detection circuit shown in FIG. 3 is composed of 16 CMOS operational amplifiers, resistors R1, R2, R3, and 6 diodes whose collectors and bases of 12 bipolar transistors are short-circuited.

この第3図の回路はバンドギャップリファレンス構造を
とっており、11,12.13の各抵抗R,,R2,R
3を適当に定めてやることにより、ダイオードのVBH
の温度係数による動作電圧の温度依存性を無くすことが
できる。したがって、この従来の回路の動作電圧の温度
補償特性は非常に良いものとなる。ところが、この回路
はCMOSオペアンプを使用しておりCMOSオペアン
プの特性を生かしたものとなっているが、CMOSオペ
アンプの動作可能な最低電源電圧はこの近来の技術にお
いても3.5〜4v程度であり、乾電池駆動の機器が広
く出回っている中、電源電圧が低い時には厳しい条件と
なる。
The circuit shown in Fig. 3 has a bandgap reference structure, and each of the resistors 11, 12, and 13 R, , R2, R
By appropriately setting 3, the VBH of the diode
The temperature dependence of the operating voltage due to the temperature coefficient of can be eliminated. Therefore, the operating voltage temperature compensation characteristics of this conventional circuit are very good. However, although this circuit uses a CMOS operational amplifier and takes advantage of the characteristics of a CMOS operational amplifier, the minimum power supply voltage at which a CMOS operational amplifier can operate is around 3.5 to 4 V even with this recent technology. Although dry battery-powered equipment is widely available, the conditions are severe when the power supply voltage is low.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上述べた様に、従来の低電圧検出回路は、CMOSオ
ペアンプを使用しているため電源電圧が低い時の動作に
問題があり、また素子数が多いという問題があった。
As described above, the conventional low voltage detection circuit uses a CMOS operational amplifier, so there is a problem in operation when the power supply voltage is low, and there is also a problem in that the number of elements is large.

〔課題を解決するための手段〕[Means to solve the problem]

このような課題を解決するために、本発明の低電圧検出
回路ではCMOSオペアンプを使用せずMOS)ランク
351個と抵抗1個のみにより低電圧を検出し、かつ、
温度補償ができるようにしており、その出力をバッファ
により波形を整形している。
In order to solve such problems, the low voltage detection circuit of the present invention detects low voltage using only 351 MOS (MOS) ranks and one resistor without using a CMOS operational amplifier, and
Temperature compensation is possible, and the output waveform is shaped by a buffer.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路図であり、この低電圧
検出回路は1の第1のPチャネルMOSトランジスタ及
び4の抵抗の部分と、2の第2のPチャネルMO3)ラ
ンジスタと3のNチャネルMOS)ランジスタからなる
バッファ部分とから構成されている。この回路において
低電圧を検出する部分は、1の第1のPチャネルMOS
トランジスタ及び4の抵抗の部分である。5の電源端子
に充分高い電位が印加されていれば、1の第1のPチャ
ネルMOSトランジスタはオンしているため、4の抵抗
値がこの時のlのPチャネルMOSトランジスタのオン
抵抗に比べて、充分大きければ7の出力端子にはローレ
ベルが出力される。しかし、5の電源端子に印加される
電位が低くなってくると、1の第1のPチャネルMOS
トランジスタのオン抵抗は増加していき、ある電位に達
すると4の抵抗の値よりも大きくなるため、バッファ部
が動作している領域であれば7の出力端子に出力される
信号は反転しハイレベルとなり、この時の電圧値が検出
される。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and this low voltage detection circuit includes a first P-channel MOS transistor (1), a resistor section (4), and a second P-channel MOS transistor (2). The buffer part consists of three N-channel MOS) transistors. In this circuit, the part that detects low voltage is the first P-channel MOS
This is the transistor and the resistor part 4. If a sufficiently high potential is applied to the power supply terminal 5, the first P-channel MOS transistor 1 is on, so the resistance value of 4 is compared to the on-resistance of the P-channel MOS transistor 1 at this time. If it is large enough, a low level is output to the output terminal 7. However, when the potential applied to the power supply terminal 5 becomes low, the first P-channel MOS
The on-resistance of the transistor increases, and when it reaches a certain potential, it becomes larger than the value of the resistance of 4, so if the buffer section is in operation, the signal output to the output terminal of 7 is inverted and goes high. level, and the voltage value at this time is detected.

次に第1図の低電圧検出回路のシミュレーション結果に
ついて説明する。
Next, simulation results of the low voltage detection circuit shown in FIG. 1 will be explained.

第4図は第1図の回路の5PICEによるDC特性のシ
ミュレーションの結果であり、温度をパラメータに取っ
ている。横軸は5の電源端子に印加される電圧値であり
、縦軸は7の出力端子に出力される電圧値である。この
結果から電源電圧が約3v以下になれば出力はハイレベ
ルになり、また約3v以上であれば出力はローレベルに
なることから、この回路で3vが検出できることになる
FIG. 4 shows the results of a simulation of the DC characteristics of the circuit shown in FIG. 1 using 5PICE, using temperature as a parameter. The horizontal axis is the voltage value applied to the power terminal 5, and the vertical axis is the voltage value output to the output terminal 7. From this result, if the power supply voltage is about 3V or less, the output will be at a high level, and if it is about 3V or more, the output will be at a low level, so this circuit can detect 3V.

また、温度を一40℃〜150℃まで変化させてシミュ
レーションをしているが、この時の動作電圧の変化は2
.8817V (MIN) 〜2.9960 V(MA
X)であり、その差!tO,1143V、!:小さく動
作電圧は温度について補償されている。今回のシミュレ
ーションにあたって温度特性を見るためにMOS)ラン
ジスタのモデルパラメータのレベルは2を用い、また抵
抗の1次温度係数を2000PPM/℃とした。
In addition, the simulation is performed by changing the temperature from -40℃ to 150℃, but the change in operating voltage at this time is 2
.. 8817V (MIN) ~2.9960V (MA
X) and the difference! tO,1143V,! : Small operating voltage is compensated for temperature. In this simulation, in order to observe the temperature characteristics, the model parameter level of the MOS transistor was set to 2, and the primary temperature coefficient of resistance was set to 2000 PPM/°C.

第2図は本発明の実施例2の回路図である。第2図の低
電圧検出回路は、本発明の実施例1の回路図である第1
図の回路の1と4からなる検出部分が異っており、4の
抵抗と8の第1NチャネルMOSトランジスタから構成
されている。第2図の回路の動作は5の電源電圧が充分
に高い時には8の第1NチャネルMOSトランジスタは
オンしており、11の出力端子にはハイレベルが出力さ
れ、低電圧時には実施例1と同様の考え方で出力は反転
しローレベルが出力されることになる。したがって第2
図の回路は第1図の回路に対して出力信号は論理的に逆
となるが、この低電圧検出回路の出力信号の他の回路へ
の使用法により、第1図の回路か、第2図の回路かを選
択することができる。
FIG. 2 is a circuit diagram of a second embodiment of the present invention. The low voltage detection circuit shown in FIG.
The detection portions 1 and 4 of the circuit shown in the figure are different, and are composed of 4 resistors and 8 first N-channel MOS transistors. The operation of the circuit shown in FIG. 2 is that when the power supply voltage 5 is sufficiently high, the first N-channel MOS transistor 8 is on, and a high level is output to the output terminal 11, and when the voltage is low, it is the same as in the first embodiment. Based on this idea, the output will be inverted and a low level will be output. Therefore, the second
The output signal of the circuit shown in the figure is logically opposite to that of the circuit shown in Fig. 1, but depending on how the output signal of this low voltage detection circuit is used in other circuits, the circuit shown in Fig. 1 or the circuit shown in Fig. 2 You can choose the circuit shown in the figure.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、温度補償がされた低電圧
の検出をCMOSオペアンプを使用せずに行うことがで
きるので、低電圧時においても充分動作し、また素子数
を減らすことができるという効果がある。
As explained above, the present invention can perform temperature-compensated low voltage detection without using a CMOS operational amplifier, so it can operate satisfactorily even at low voltages and can reduce the number of elements. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図、第2図は第2の実
施例の回路図、第3図は従来の技術を示す回路図、第4
図は第1図の回路のシミュレーション結果を示す特性図
である。 1・・・・・・第1PチヤネルMOSトランジスタ、2
・・・・・・第2PチヤネルMOSトランジスタ、3・
・・・・・NチャネルMOSトランジスタ、4・・・・
・・抵抗、5・・・・・・電源端子、6・・・・・・接
地端子、7・・・・・・出力端子、8・・・・・・第1
NチャネルMOSトランジスタ、9・・・・・・Pチャ
ネルMOSトランジスタ、10・・・・・・第2Nチャ
ネルMOSトランジスタ、11・・・・・・出力端子、
12・・・・・・バイポーラトランジスタ、13・・・
・・・抵抗R1,14・・・・・・抵抗R2,15・・
・・・・抵抗R8,16・・・・・・CMOSオペアン
プ、17・・・・・・出力端子。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a second embodiment, Fig. 3 is a circuit diagram showing a conventional technique, and Fig. 4 is a circuit diagram of an embodiment of the present invention.
The figure is a characteristic diagram showing simulation results of the circuit of FIG. 1. 1...First P channel MOS transistor, 2
...Second P channel MOS transistor, 3.
...N-channel MOS transistor, 4...
...Resistance, 5...Power terminal, 6...Ground terminal, 7...Output terminal, 8...1st
N-channel MOS transistor, 9... P-channel MOS transistor, 10... second N-channel MOS transistor, 11... output terminal,
12... Bipolar transistor, 13...
... Resistor R1, 14... Resistor R2, 15...
...Resistor R8, 16...CMOS operational amplifier, 17...Output terminal.

Claims (3)

【特許請求の範囲】[Claims] (1)第1のPチャネルMOSトランジスタのゲートを
接地端子に接続し、ソースを電源端子に接続し、ドレイ
ンを抵抗の一端に接続し、抵抗の他端を接地端子に接続
し、第1のPチャネルMOSトランジスタのドレインを
第2のPチャネルMOSトランジスタとNチャネルMO
Sトランジスタで構成されるCMOSインバータの入力
端子に接続することにより構成される温度補償型低電圧
検出回路。
(1) The gate of the first P-channel MOS transistor is connected to the ground terminal, the source is connected to the power supply terminal, the drain is connected to one end of the resistor, the other end of the resistor is connected to the ground terminal, and the first P-channel MOS transistor is connected to the ground terminal. The drain of the P-channel MOS transistor is connected to the second P-channel MOS transistor and the N-channel MO
A temperature compensated low voltage detection circuit configured by connecting to the input terminal of a CMOS inverter configured with S transistors.
(2)特許請求の範囲第一項記載のCMOSインバータ
の入力端子にNチャネルMOSトランジスタのドレイン
及び抵抗の一端を接続し、前記NチャンネルMOSトラ
ンジスタのゲートを電源端子に接続し、ソースを接地端
子に接続し、抵抗の他端を電源端子に接続することを特
徴とする温度補償型低電圧検出回路。
(2) The drain of an N-channel MOS transistor and one end of a resistor are connected to the input terminal of the CMOS inverter according to claim 1, the gate of the N-channel MOS transistor is connected to a power supply terminal, and the source is connected to a ground terminal. A temperature compensated low voltage detection circuit characterized in that the other end of the resistor is connected to a power supply terminal.
(3)特許請求の範囲第一項記載の抵抗が拡散抵抗で構
成され2000PPM/℃程度の正の温特を持つ事を特
徴とする温度補償型低電圧検出回路。
(3) A temperature compensated low voltage detection circuit characterized in that the resistor according to claim 1 is constituted by a diffused resistor and has a positive temperature characteristic of about 2000 PPM/°C.
JP3542990A 1990-02-15 1990-02-15 Low voltage detection circuit Pending JPH03238365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3542990A JPH03238365A (en) 1990-02-15 1990-02-15 Low voltage detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3542990A JPH03238365A (en) 1990-02-15 1990-02-15 Low voltage detection circuit

Publications (1)

Publication Number Publication Date
JPH03238365A true JPH03238365A (en) 1991-10-24

Family

ID=12441618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3542990A Pending JPH03238365A (en) 1990-02-15 1990-02-15 Low voltage detection circuit

Country Status (1)

Country Link
JP (1) JPH03238365A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644546A (en) * 1992-09-11 1997-07-01 Fujitsu Limited MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin
JP2007166685A (en) * 2005-12-09 2007-06-28 Ricoh Co Ltd Backflow prevention circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5719676A (en) * 1981-06-01 1982-02-01 Seiko Epson Corp Voltage detecting circuit
JPS6188549A (en) * 1984-10-05 1986-05-06 Citizen Watch Co Ltd Semiconductor integrated circuit with detecting circuit for life of battery
JPS61249126A (en) * 1985-04-27 1986-11-06 Toshiba Corp Circuit for detecting fall of supply voltage

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5719676A (en) * 1981-06-01 1982-02-01 Seiko Epson Corp Voltage detecting circuit
JPS6188549A (en) * 1984-10-05 1986-05-06 Citizen Watch Co Ltd Semiconductor integrated circuit with detecting circuit for life of battery
JPS61249126A (en) * 1985-04-27 1986-11-06 Toshiba Corp Circuit for detecting fall of supply voltage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644546A (en) * 1992-09-11 1997-07-01 Fujitsu Limited MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin
US5734622A (en) * 1992-09-11 1998-03-31 Fujitsu Limited MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin
JP2007166685A (en) * 2005-12-09 2007-06-28 Ricoh Co Ltd Backflow prevention circuit
JP4597044B2 (en) * 2005-12-09 2010-12-15 株式会社リコー Backflow prevention circuit

Similar Documents

Publication Publication Date Title
KR890004647B1 (en) Static current source circuit and differential amplifier with it
KR930007482B1 (en) Current detecting circuit
TWI451697B (en) Very low power analog compensation circuit
US4752703A (en) Current source polarity switching circuit
US5191235A (en) Semiconductor integrated circuit device having substrate potential detection circuit
US5608344A (en) Comparator circuit with hysteresis
US4461991A (en) Current source circuit having reduced error
JPH09321586A (en) Level comparator
KR950000432B1 (en) Simulated transistor/diode
Pessina Low-noise, low drift, high precision linear bipolar (±10 V) voltage supply/reference for cryogenic front-end apparatus
JPH03238365A (en) Low voltage detection circuit
US5065056A (en) Clamping circuit
KR930007127B1 (en) Semiconductor integrated circuit
JPH118534A (en) Semiconductor integrated circuit
US6590443B1 (en) Dynamic biasing for cascoded transistors to double operating supply voltage
US6842050B2 (en) Current-mode circuit for implementing the minimum function
CN114039560B (en) Operational amplifier and output stage circuit thereof
JPH08139531A (en) Differential amplifier
US5296754A (en) Push-pull circuit resistant to power supply and temperature induced distortion
KR100622350B1 (en) Stacked CMOS current mirror using the different threshold voltage MOSFETs in a low voltage digital technology
JPH0263205A (en) Amplifying circuit
US20150236683A1 (en) High voltage comparison circuit
JP2545374B2 (en) Differential amplifier circuit having constant current source circuit
KR930004708Y1 (en) Exponential amp using cmos
SU650066A1 (en) Dc voltage stabilizer