JPH118534A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [PROBLEMS] To improve the characteristics of a chopper-type comparator used in a semiconductor integrated circuit to selectively input and compare a reference voltage and an input voltage, and to improve the characteristics of a chopper-type comparator in order to shorten a comparison cycle, an input capacitance and an analog signal. When the on-resistance value of the transistor constituting the switch is reduced, the accuracy of comparison and determination is degraded by the feed-through charge of the analog switch, so that the on-resistance value and the input capacitance cannot be easily reduced. A threshold voltage of a MOS transistor constituting an analog switch is lower than that of a MOS transistor constituting a circuit other than a chopper type comparator in a semiconductor integrated circuit. According to the present invention, the ON resistance and the stray capacitance of the MOS transistor constituting the analog switch can be reduced, the charge / discharge characteristics can be improved, and the comparison cycle can be shortened. In addition, it is possible to suppress the deterioration of the comparison determination accuracy due to the feedthrough charge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the characteristics of a chopper type comparator which is used in a semiconductor integrated circuit, selects and inputs a reference voltage and an input voltage, and compares them.

[0002]

2. Description of the Related Art A comparator is used for making a comparison between an input voltage and a reference voltage, and is particularly known as a main circuit element of an A / D converter. The chopper type comparator is one of the circuit types of the comparator. An example of this type of chopper comparator is shown in FIG. 3A is a reference voltage input terminal, 2 is an analog input terminal, 3 is an input capacitor for sampling the reference voltage and the analog input voltage, and 4 is a control signal located between the terminal 1 and the input capacitor 3. An analog switch by an N-channel MOS transistor controlled by S2, 5 is located between the terminal 2 and the input capacitor 3, an analog switch by an N-channel MOS transistor controlled by a control signal S3, 6 is a P-channel MOS transistor 61
And an inverter 7 having an output connected to the drain of the N-channel MOS transistor 62 and an input connected to the gates of the transistors 61 and 62. The inverter 7 is controlled by the control signal S1, and the output of the inverter 6 is fed back to the input. Switch using an N-channel MOS transistor, that is, an analog switch for short-circuiting the output and input of the inverter.

The chopper comparator has two operation modes, a "self-biasing operation" and a "comparison / determination operation". FIG. 3B shows control waveform diagrams of S1, S2, and S3 in each operation mode.

First, when a high-level signal is applied to S1 and S2 and a low-level signal is applied to S3, "self-biasing operation" occurs. At this time, the input and output terminals of the inverter are short-circuited by turning on the analog switch 7, and the input gate voltage Vg and the output voltage Vo of the inverter become the logical inversion voltage Vb of the inverter. When the analog switch 4 between the terminal 1 and the input capacitor 3 is turned on, the voltage between the terminals of the input capacitor 3 becomes “Vr−Vb”, where Vr is the reference voltage of the reference voltage input terminal.

Next, when a low-level signal is applied to S1 and S2 and a high-level signal is applied to S3, a "comparison / determination operation" is performed. At this time, the input and output terminals of the inverter are not short-circuited by turning off the analog switch 7, and the inverter performs an inverting amplification operation. Further, the analog switch 4 between the terminal 1 and the input capacitor 3 is turned off, and the analog switch 5 between the terminal 2 and the input capacitor 3 is turned off.
Is turned on, an analog input voltage Vin is applied to one terminal of the input capacitor 3. At this time, since the voltage between the terminals of the input capacitor 3 does not change, the gate voltage Vg of the inverter is expressed by the following equation with respect to the analog input voltage Vin: Vg = Vin− (Vr−Vb) (1).

As a result, when the amplification factor of the inverter is G, Vin−Vr = Vg−Vb = ΔVi (2) and Vo−Vb = ΔVo (3) From equation (3), ΔVo = −G × ΔVi (4) It becomes an expression.

Thus, the analog input voltage Vin and the reference voltage Vr can be compared.

In the above-mentioned chopper type comparator, the VDD is applied to the inverter 6 during the "self-biasing operation".
Since a through current flows between -VSS, methods for reducing power consumption are disclosed in JP-A-1-064414, JP-A-2-101814, and JP-A-5-196659.
There is known a method described in public relations.

FIG. 4A shows a chopper type comparator described in the above-mentioned document as a second conventional example. In the second prior art, a P-channel MOS transistor 61 and an N-channel MOS constituting the inverter 6 described in the first prior art are used.
MOS transistors 8 and 9 of the same channel whose gate voltage is controlled by a control signal or a DC voltage are inserted on the source side of each of the transistors 62 to constitute a clocked inverter.

FIG. 4B shows a control waveform when the terminals 10 and 11 are used as control signals in this configuration. When a self-bias operation is started and a high-level signal is applied to the terminal 10 and a low-level signal is applied to the terminal 11 when the potential of the input / output terminal of the clocked inverter reaches the logic inversion voltage Va of the clocked inverter, the self-bias operation Give until the end. As a result, the through current path of the clocked inverter is cut off, and power consumption is reduced.

When a DC voltage is applied to the terminals 10 and 11, for example, VSS is applied to the terminal 10 and VDD is applied to the terminal 11, N
The channel MOS transistor 8 and the P-channel MOS transistor 9 function as a constant resistance element in the non-saturation region operation and a constant current element in the saturation region operation with respect to the path of the through current flowing during the “self-bias operation”. Since the potential difference between the sources of the N-channel transistor 62 is made lower than the power supply voltage by the voltage drop of the MOS transistors 8 and 9, the through current of the clocked inverter is reduced.

[0012]

However, in such a configuration of the conventional chopper type comparator, the threshold voltage of the MOS transistor forming the analog switch rises due to the base bias effect, and the on-resistance value Ron of the transistor is reduced. As a result, the charge / discharge characteristics of the input capacitor 3 during the “self-biasing operation” and the “comparison / judgment operation” deteriorate, and there is a problem that the comparison cycle for performing the normal comparison operation cannot be shortened.

This charge / discharge characteristic can be improved by reducing the product of the input capacitance value C of the input capacitance 3 and the on-resistance value Ron of the transistor. However, the analog switch, which is an important factor that determines the determination accuracy of the chopper type comparator, is used. These values cannot be easily reduced in consideration of the influence of the feed-through charge. The reason will be described below.

In the above description of the basic operation of the chopper type comparator, if ΔVi is the minimum resolution voltage of the chopper type comparator, that is, the minimum voltage difference that can be compared and determined in equation (2), the floating capacitance 12 in FIG. , Drain diffusion capacitance, wiring capacitance and the like. In the chopper-type comparator in consideration of the stray capacitance value Cs of the stray capacitance 12, the gate voltage Vg of the inverter 6 is given by ΔVf = ΔQf / (C + Cs) by the feedthrough charge ΔQf generated when the feedback analog switch 7 is turned off. ) An error voltage represented by the equation (5) is generated.

When the absolute value of the error voltage exceeds the minimum resolution voltage of the comparator, the polarity that should be output from the inverter is inverted, resulting in an erroneous determination operation. Therefore, increasing the denominator C and Cs in the equation (5) and reducing the numerator ΔQf can be taken as countermeasures.

Here, ΔQf is the carrier that forms a channel below the gate of the MOS transistor forming the analog switch when the analog switch 7 is turned on (hereinafter, referred to as a carrier).
It is called a channel forming carrier. ) Is known to be generated by being discharged to the source and drain of the transistor at the same time as the transistor is turned off. If the channel width of the transistor is W and the channel length is L, the relation of ΔQf∝W × L (6) is obtained. To establish.

On the other hand, the on-resistance value Ron of the transistor in the analog switch is expressed by the following equation: Ron = 1 / {β (Vgs−Vth)} (7)
Here, Vgs is the gate-source voltage of the transistor Vth is the threshold voltage of the transistor β is the current amplification factor of the MOS transistor, and β = μCoW / L (8)

Μ is the carrier mobility Co is the gate capacitance per unit area, so increasing C and Cs to reduce ΔVf causes an increase in the charge / discharge time, and decreasing W ( Since the on-resistance value Ron of the transistor increases when ΔQf in equation (6) is reduced, as is apparent from equations (7) and (8), the comparison is made without deteriorating the judgment accuracy of the comparator. There was a problem that only the cycle could not be shortened.

Here, the influence of the feedthrough charge of the feedback analog switch 7 at the end of the "self-biasing operation" has been described. However, the input analog switch 4 for selectively connecting the reference voltage and the analog input voltage, The same is true for No. 5.

[0020]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a sampling capacitor and first and second MOS transistors for selectively connecting a reference voltage and an analog input voltage to one end of the sampling capacitor. A second analog switch, an amplifying CMOS inverter connected in series to the other end of the sampling capacitor, and a third analog switch including a MOS transistor for enabling short-circuit or non-short-circuit selection of an output and an input of the inverter In a semiconductor integrated circuit incorporating a chopper type comparator comprising: a MOS constituting a first and second or third analog switch of the chopper type comparator
The threshold voltage of the transistor is an MO that constitutes a circuit other than the chopper type comparator in the semiconductor integrated circuit.
It is characterized by being lower than the threshold voltage of the S transistor.

According to a second aspect of the present invention, there is provided a chopper type comparator, comprising: a sampling capacitor; first and second analog switches each including a MOS transistor for selectively connecting a reference voltage and an analog input voltage to one end of the sampling capacitor; Amplifying CMOS clocked inverter connected in series to the other end of the sampling capacitor, and a third analog switch using a MOS transistor for enabling selection between short-circuit and non-short-circuit of an output and an input of the clocked inverter. In a semiconductor integrated circuit having a built-in chopper comparator, a P-channel MOS transistor and a N-channel transistor on the drain side of the clocked inverter are provided.
MOS in any of the channel MOS transistors
The threshold voltage of the transistor is an MO that constitutes a circuit other than the chopper type comparator in the semiconductor integrated circuit.
It is characterized by being lower than the threshold voltage of the S transistor.

A semiconductor integrated circuit according to a third aspect of the present invention is the chopper type comparator according to claim 1 or 2,
As a method of lowering the threshold voltage of the OS transistor,
In the semiconductor integrated circuit, a channel length of the transistor is shorter than a MOS transistor constituting a circuit other than the chopper type comparator in the semiconductor integrated circuit, and a threshold voltage is reduced by a short channel effect.

A semiconductor integrated circuit according to a fourth aspect of the present invention is the chopper type comparator according to claim 1, wherein a control signal for turning on and off the first and second analog switches, or a control signal for turning on and off the third analog switch. The amplitude voltage of the control signal to be turned off is smaller than the power supply voltage width applied to the semiconductor integrated circuit.

[0024]

According to the semiconductor integrated circuit of the first invention, the output and the input of the amplifying CMOS inverter in the chopper type comparator can be short-circuited or non-short-circuited. The threshold voltage of the MOS transistor forming the analog switch for selectively connecting the reference voltage and the analog input voltage is made higher than the threshold voltage of the MOS transistor forming a circuit other than the chopper type comparator in the semiconductor integrated circuit. By lowering the value, only the on-resistance value Ron can be reduced without increasing the gate area and the stray capacitance value Cs of the transistor. Therefore, the charge / discharge characteristics can be improved without deteriorating the comparison determination accuracy, and the comparison cycle can be shortened.

According to the semiconductor integrated circuit of the second invention, the threshold voltage of the P-channel MOS transistor or the N-channel MOS transistor on the drain side of the amplifying CMOS clocked inverter in the chopper type comparator is determined by Since the transconductance gm of the transistor can be increased without increasing the gate area by lowering the threshold voltage of the MOS transistor constituting a circuit other than the chopper type comparator, the comparison can be performed without increasing the stray capacitance Cs. The time required for the judgment operation and the self-bias operation can be reduced.

According to the semiconductor integrated circuit of the third aspect, the gate channel length is shorter than that of the MOS transistor constituting a circuit other than the chopper type comparator in the semiconductor integrated circuit, and the short channel effect of the MOS transistor is reduced. By lowering the threshold voltage, the gate area (W × L) of the MOS transistor constituting the input analog switch or the feedback analog switch according to the first invention can be reduced without increasing the number of manufacturing steps. In addition to the effect of the invention, the accuracy of comparison and determination is improved. Also,
Since the gate area of the P-channel MOS transistor or the N-channel MOS transistor on the drain side of the amplifying CMOS clocked inverter according to the second invention can be reduced, the stray capacitance value Cs can be reduced in addition to the effect of the second invention. The charge and discharge characteristics are improved.

According to the semiconductor integrated circuit of the fourth invention, the control signal for turning on / off the input analog switch or the control signal for turning on / off the feedback analog switch in the chopper type comparator according to the first invention. By making the amplitude voltage smaller than the power supply voltage width applied to the semiconductor integrated circuit, the number of carriers forming the channel when the MOS transistor is turned on can be reduced, so that the feedthrough charge when the analog switch is turned off can be reduced and the accuracy of comparison and determination can be improved.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the chopper type comparator according to the first, second and third aspects of the present invention. The embodiment of FIG. 1 employs clocks 8 and 9 shown in FIG. The threshold voltage of MOS transistors other than the P-channel and N-channel MOS transistors on the source side of the inverted inverter is lower than that of MOS transistors constituting circuits other than the chopper type comparator in the semiconductor integrated circuit. The operation is the same as that of the conventional example 2 described above.

The reason for lowering the threshold voltage of the MOS transistor forming the analog switch in the first invention will be described below. Normally, an analog switch has a potential difference Vbs between a transistor substrate and a source.
It is known that the threshold voltage increases due to (base bias voltage). The increase in threshold voltage Vth due to the base bias effect of the N-channel MOS transistor is expressed as follows: Vth = Vth (0) + K ｛(2ψbp + Vbs) 1 / 2- (2ψb
p) 1/2｝ is represented by the second term of equation (9).

Here, Δbp is the Fermi level determined by the P-type silicon base impurity concentration, and Vth (0) is Vbs = 0.
The threshold voltage at the time of (1) is obtained by Expression (10), and K is obtained by the substrate bias effect coefficient by Expression (11).

Vth (0) = 2ψbp + φms + (2qεsiNA) 1/2 / Co + Qint / Co (10) where φms is the work function difference between the gate material and silicon. Qint is the charge density at the interface state. Εsi is the dielectric constant of silicon. Channel impurity concentration (acceptor concentration) q is the amount of electron charge K = (2qεsiNA) 1/2 / Co (11) In order to suppress the rise of the threshold voltage, the second term in the expression (9) must be This can be easily achieved by doping the channel with phosphorus (P).

Assuming that the threshold voltage of the transistor after doping with phosphorus (P) is Vth ′, Vth ′ = Vth (0) + K ｛(2ψbp + Vbs) 1 / 2− (2
{bp) 1/2} −ΔVth (12)

ΔVth is a change in threshold voltage due to channel doping.

ΔVth = K ｛(2ψbp + Vbs) 1 / 2−
(2ψbp) 1/2｝ (13) can be made relatively easily in the current semiconductor manufacturing technology, whereby the off-resistance value R of the N-channel MOS transistor is obtained.
The off can reduce only the on-resistance Ron without deteriorating. In this case, it is not necessary to increase the gate channel width W of the N-channel MOS transistor in order to reduce the on-resistance value Ron of the transistor. Through charge can be reduced.

Next, reduction of the threshold voltage Vth of the P-channel and N-channel MOS transistors on the drain side of the clocked inverter according to the second invention will be described. It is a well-known fact that the operating speed of a MOS analog circuit is proportional to gm (mutual transmission conductance). In general, gm = β | Vgs−Vth | = μCoW / L (Vgs−Vth)
It is expressed by equation (14).

Since gm can be set higher by lowering Vth in equation (14), the on-resistance value Ron of the transistor is reduced without increasing the gate area and stray capacitance value Cs as shown in equation (7). be able to. Therefore, if the threshold voltage of at least one of the MOS transistors on the drain side of the clocked inverter is lowered, only the comparison operation can be sped up without deteriorating the comparison determination accuracy.

Further, the chopper type comparator according to the third invention has a gate channel for either the P-channel MOS transistor 61 or the N-channel MOS transistor 62 on the drain side of the analog switch 4 or 5 or 7 in FIG. The length L is shorter than that of a MOS transistor constituting a circuit other than a chopper type comparator in a semiconductor integrated circuit. It is known that when the channel length L of a MOS transistor is reduced, a subthreshold current increases due to a decrease in a barrier caused by a drain voltage and a threshold voltage Vth decreases. This phenomenon is called a “short channel effect”. I have. Therefore, if this short channel effect is actively used, the manufacturing process such as the channel doping described above becomes unnecessary, and MOS
The gate area can be reduced in addition to the reduction in the on-resistance value Ron of the transistor.

Finally, FIG. 2 is a control waveform diagram of the chopper type comparator of the fourth invention. In the chopper type comparator shown in FIG. 1, the amplitudes of the control signals S1, S2 and S3 for turning on and off the analog switch are shown. The voltage is smaller than the power supply voltage width applied to the semiconductor integrated circuit.

In FIG. 1, since the threshold voltage Vtn of the N-channel MOS transistor forming the analog switch is lowered by the above-described method, Vgs in the above equation (7) does not impair the desired on-resistance Ron. Can be as small as possible. That is, in any of the control signals S1, S2, and S3, the amplitude voltage of the control signal can be made smaller than the power supply voltage width applied to the semiconductor integrated circuit. Since the feedthrough charge due to the channel forming carrier is proportional to the signal amplitude applied to the transistor gate,
By reducing the amplitude voltage, the feedthrough charge when the analog switch is turned off is reduced, and the accuracy of comparison and determination can be improved.

[0040]

As described above, according to the semiconductor integrated circuit according to the first aspect of the present invention, the threshold voltage of the MOS transistor forming the feedback or input analog switch forming the chopper type comparator is controlled by the semiconductor. MO that constitutes a circuit other than a chopper type comparator in an integrated circuit
By making the threshold voltage lower than the threshold voltage of the S transistor, only the on-resistance value Ron can be reduced without increasing the gate area and the stray capacitance value Cs of the transistor. And the comparison cycle can be shortened.

According to the semiconductor integrated circuit of the second aspect of the present invention, the threshold voltage of the MOS transistor on the drain side of the clocked inverter constituting the chopper type comparator is set to a value other than the chopper type comparator in the semiconductor integrated circuit. Since the transconductance gm of the transistor can be increased without increasing the gate area by making the threshold voltage lower than the threshold voltage of the MOS transistor constituting the circuit, the comparison judgment operation and the self-bias operation can be performed without increasing the stray capacitance Cs. The time required for the operation can be reduced.

According to the semiconductor integrated circuit of the third aspect of the present invention, the gate channel length is shortened as compared with the MOS transistor constituting a circuit other than the chopper type comparator in the semiconductor integrated circuit, and the short channel of the MOS transistor is shortened. The MO that constitutes the analog switch for input or the analog switch for feedback according to the first aspect of the present invention can be manufactured without increasing the number of manufacturing steps by lowering the threshold voltage by the effect.
Since the gate area (W × L) of the S transistor can be reduced, the accuracy of comparison and determination is improved in addition to the effect of the first invention. Further, since the gate area of the P-channel MOS transistor or the N-channel MOS transistor on the drain side of the amplifying CMOS clocked inverter according to the second invention can be reduced, the floating capacitance value Cs can be reduced in addition to the effect of the second invention. The charge and discharge characteristics are improved by the reduction.

According to the semiconductor integrated circuit of the fourth aspect of the present invention, the control signal for turning on / off the input analog switch in the chopper type comparator according to the first aspect of the present invention, or the analog signal for feedback is turned on / off. By making the amplitude voltage of the control signal to be smaller than the power supply voltage width applied to the semiconductor integrated circuit, it is possible to reduce the carriers forming the channel when the MOS transistor is turned on.
The feed-through charge when the analog switch is off can be reduced, and the accuracy of comparison and determination is improved.

Further, if the chopper comparator of the present invention is applied to an A / D converter, the characteristics of the A / D converter itself can be improved. In this embodiment, the configuration using an N-channel MOS transistor for the analog switch has been described. However, the same effect can be obtained by replacing the analog switch with a P-channel MOS or CMOS transistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing first to third embodiments of the present invention.

FIG. 2 is a control waveform diagram of a chopper type comparator according to a fourth embodiment of the present invention.

FIG. 3A is a circuit diagram showing a first conventional example of a chopper type comparator. (B) A control waveform diagram of the chopper comparator of Conventional Example 1.

FIG. 4A is a circuit diagram showing a second conventional example of a chopper type comparator. (B) A control waveform diagram of a chopper type comparator when V1 and V2 of Conventional Example 2 are used as control signals.

FIG. 5 is an equivalent model diagram in a comparison determination operation of a chopper type comparator in consideration of stray capacitance.

[Explanation of symbols]

1. Reference voltage input terminal 2. Analog input terminal 3. Input capacitance 4. Analog switch using N-channel MOS transistor 41. Analog switch using low threshold voltage N-channel MOS transistor 5. N-channel MOS transistor Analog switch 51 .. Analog switch with low threshold voltage N-channel MOS transistor 6. Inverter 61. P-channel MOS transistor 62. N-channel MOS transistor 63. Low threshold voltage P-channel MOS transistor 64. · Low threshold voltage N channel MOS transistor 7 · · · Analog switch using N channel MOS transistor 71 · · · Analog switch using low threshold voltage N channel MOS transistor 8 · · · P channel MOS transistor Register 9 · N-channel MOS transistor 10 ... control signal and a fixed bias voltage input terminal 11 ... control signal and a fixed bias voltage input terminal 12 ... stray capacitance

Claims (4)

[Claims] 1. A sampling capacitor, first and second analog switches each including a MOS transistor for selectively connecting a reference voltage and an analog input voltage to one end of the sampling capacitor, and serially connected to the other end of the sampling capacitor. A semiconductor integrated circuit including a CMOS inverter for amplification connected to the inverter and a chopper-type comparator including a third analog switch including a MOS transistor for enabling selection between short-circuit and non-short-circuit of an output and an input of the inverter. Forming first and second or third analog switches of the type comparator
The threshold voltage of the transistor is an MO that constitutes a circuit other than the chopper type comparator in the semiconductor integrated circuit.
A semiconductor integrated circuit having a lower threshold voltage than an S transistor. 2. A sampling capacitor, first and second analog switches each including a MOS transistor for selectively connecting a reference voltage and an analog input voltage to one end of the sampling capacitor, and serially connected to the other end of the sampling capacitor. Amplifying CMOS clocked inverter connected to the power supply and an output and an input of the clocked inverter are short-circuited;
In a semiconductor integrated circuit incorporating a chopper type comparator comprising a third analog switch using a MOS transistor for enabling non-short-circuit selection, one of a P-channel MOS transistor and an N-channel MOS transistor on a drain side of the clocked inverter is provided. A semiconductor integrated circuit, wherein a threshold voltage of a MOS transistor is lower than a threshold voltage of a MOS transistor constituting a circuit other than the chopper type comparator in the semiconductor integrated circuit. 3. A chopper type comparator according to claim 1, wherein the threshold voltage of the MOS transistor is reduced by using a MOS transistor constituting a circuit other than the chopper type comparator in the semiconductor integrated circuit. A semiconductor integrated circuit characterized in that a channel length of a transistor is shortened and a threshold voltage is reduced by a short channel effect. 4. The chopper-type comparator according to claim 1, wherein the first and second analog switches are turned on,
A semiconductor integrated circuit, wherein an amplitude voltage of a control signal for turning off or a control signal for turning on and off a third analog switch is smaller than a power supply voltage width applied to the semiconductor integrated circuit.