JP3846267B2 - Differential amplifier and level detector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential amplifier circuit, particularly a technique that operates with a low voltage power source such as a battery and is effective when used for a level detector of a low level signal of about plus several mV.
[0002]
[Prior art]
In recent years, most of various signals in automobiles are processed using electronic circuits using ICs, and these electronic circuits are operated with a single power source from a battery and various devices are designed to operate with low power consumption. Is given. For example, in an analog circuit for ETCS (automatic toll collection system) using an IC card, the signal received by the roadside antenna is monitored, and the system is operated in the normal power consumption state only while the signal is received, When not receiving, the power consumption is reduced by maintaining the sleep state, which is a low power consumption state.
[0003]
The presence / absence of an antenna signal necessary for the ETCS is determined at a very low voltage level of several mV. FIG. 3 shows a comparator using a conventional differential amplifier circuit. Here, in order to clarify the problems that occur when this differential amplifier circuit is used for low voltage level detection as described above, and the problem to be solved by the present invention, the configuration and operation of this circuit will be described. To do. (In the following description, all elements in FIG. 3 are formed on the same IC chip, and transistors P1 and P2 and N1 and N2 have the same characteristics.)
[0004]
The sources of two PMOS transistors (P-type Metal Oxide Semiconductors) P1 and P2 forming a differential pair in FIG. 3 are connected to the drain of the PMOS transistor P3 in common, and the source of the PMOS transistor P3 is the power supply voltage Vdd. The gate of the power supply line to be supplied is connected to the gate of the PMOS transistor P4. The transistor P4 has a source connected to a power supply line for supplying the power supply voltage Vdd, a drain and a gate connected in common, and a grounded potential Vgnd via a resistor R. As a result, the voltage VgsP4 between the gate and source of the transistor P4 becomes a constant voltage substantially equal to the threshold voltage VthP of the PMOS transistor P4, assuming that its current driving capability is sufficiently high. Therefore, a constant voltage substantially equal to the threshold voltage Vthp of the PMOS transistor is always applied between the gate and source of the transistor P3. In this state, if a slight voltage is applied between the drain and the source of the transistor P3 (a voltage at which the drain is negative with respect to the source), the transistor P3 operates as a constant current source, and is connected to the source common connection point of the transistors P1 and P2. A constant current is supplied.
[0005]
On the other hand, the drains of the transistors P1 and P2 are respectively connected to the drains of NMOS transistors (N-type Metal Oxide Semiconductor) N1 and N2 constituting a current mirror circuit as an active load. Since the gates of the transistors N1 and N2 are connected in common and connected to the drain of the transistor N1, the gate-source voltages VgsN1 and VgsN2 are not less than a predetermined voltage (for example, not less than the threshold voltage VthN of the NMOS transistor). For example, drain currents Id1 and Id2 having almost equal magnitudes flow in the transistors N1 and N2.
[0006]
The differential input voltage is applied to the gates of the transistors P1 and P2 forming a differential pair, and the output voltage Vout is extracted from the drain of the transistor P2. In order to operate with a single power source of low voltage, all transistors are formed of enhancement type MOS.
[0007]
Here, consider a case where the level comparison between the minute voltage Vin and the reference voltage 0 V is performed using this circuit. Since the reference voltage Vref is 0 V, it is assumed that the gate of the transistor P2 is connected to the reference potential Vgnd and the minute input voltage Vin is applied to the gate of the transistor P1. The small signal differential voltage gain Adm of the circuit in this case is expressed by the following equation when the transistor P3 operates as a constant current source.
Adm = (− 1/2) gm · Rd (1) where gm is the mutual conductance of the transistors P1 and P2, and Rd is the common source output resistance of the transistors N1 and N2.
[0008]
In order for the circuit of FIG. 3 to exhibit performance as a differential amplifier, it is desirable that the differential voltage gain Adm represented by the equation (1) be as large as possible. For this purpose, each transistor is in an operating state in which the mutual conductance gm and the output resistance Rd are large, that is, the drain current Id is plotted on the vertical axis and the drain-source voltage Vds is plotted on the vertical axis using the gate-source voltage Vgs as a parameter. It is necessary to operate in the saturation region of the drain current in the grounded source output characteristic diagram (hereinafter abbreviated as Id-Vd characteristic diagram) of the MOS transistor drawn for the axis.
[0009]
FIG. 2 shows a general Id-Vd characteristic diagram of a MOS transistor. In the saturation region shown in the figure, the drain current Id is saturated at a substantially constant value regardless of the change in the drain-source voltage Vds. For this reason, the mutual conductance gm and the output resistance Rd are very large values compared to the case of operating in the non-saturated region in the figure.
[0010]
According to the theoretical analysis of the MOS transistor, it is known that the MOS transistor operates in the saturation region in the Id-Vd characteristic diagram when the following conditional expression is satisfied.
| Vds | ≧ | Vgs | − | Vth | (2) where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage.
From this equation (2), the conditions for the transistor P1 of FIG. 3 to operate in a state where the mutual conductance is high, that is, in the saturation region, are as follows.
| VdsP1 | ≧ (| VgsP1 | − | VthP |) (3) where VthP is the threshold voltage of the PMOS transistor P1.
When the drain-source voltage of the NMOS transistor N1 is VdsN1, the following equation is derived from the equation (3).
| VthP | + Vin ≧ VdsN1 (4) Formula
On the other hand, considering the condition in which the transistor N1 operates with a high output resistance, that is, in the saturation region, the transistor N1 always satisfies the expression (2) because the gate voltage and the drain voltage are equal. That is, when the drain current is flowing, it always operates in the saturation region. From this, the condition for the transistor N1 to operate in a saturated state can be expressed by the following equation.
VdsN1 ≧ VthN (5) Equations (4) and (5) can be summarized as follows.
| VthP | + Vin ≧ VdsN1 ≧ | VthN | (6) From this, when the input voltage Vin is equal to the reference voltage of 0 V, the following occurs.
| VthP | ≧ VdsN1 ≧ | VthN | (7) Although the transistors P1 and N1 have been studied above, the transistors N1 and N2 and P1 and P2 have the same characteristics, and therefore the input voltage Vin and the reference voltage Vref are both 0V. (6) is also a condition for the transistors P2 and N2 to operate in the saturation region.
[0012]
When the condition of the expression (7) is not satisfied, the fact that there is a transistor that cannot operate in the saturation region will be described with an example using specific numbers. Assume that the circuit of FIG. 3 is operated under the following conditions.
PMOS threshold voltage: | VthP | = 0.9V
NMOS threshold voltage: | VthN | = 1.0V
Power supply voltage: Vdd = 2.5V
Input voltage, reference voltage: ViN = Vref = 0V
Power supply reference potential: Vgnd = 0V
It is assumed that the current driving capability of the transistor P3 that supplies a constant current is sufficiently high.
[0013]
If the constant current source transistor P3 and the active loads N1 and N2 are all operating in the saturation region under this condition, the drain potential of the transistor P3 is about 2.4V, which is about 0.1V lower than the power supply voltage. The drain potential is about 1.1 V, which is slightly higher than the threshold voltage of the NMOS transistor than the reference potential. As a result, the absolute value of the drain-source voltage of the transistor P1 is 1.3V, and the absolute value of the gate-source voltage is 2.4V. In order for the transistor P1 to operate in the saturation region, it must be 1.5 V or more obtained by subtracting the threshold voltage 0.9 V of the PMOS transistor from the gate-source voltage 2.4 V. However, the drain-source voltage of the transistor P1 is 1.3 V, which is smaller than this. Therefore, the transistor P1 cannot operate in the saturation region, and operates in the non-saturation region.
[0014]
From what has been described so far, the following can be said. That is, when the differential amplifier circuit of FIG. 3 is operated with the input voltage Vin and the reference voltage Vref being at a low level close to the power supply reference potential Vgnd, the absolute value of the threshold voltage VthP of the PMOS transistor is the NMOS transistor. If it is smaller than the absolute value of the threshold voltage VthN, one or more of the operating points of the transistors P1, P2, N1, and N2 move out of the saturation region and move to the non-saturation region. Therefore, the differential voltage gain Adm represented by the equation (1) cannot be sufficiently obtained, and there arises a problem that the performance as an amplifier is deteriorated.
[0015]
[Problems to be solved by the invention]
The present invention is intended to solve the above-described problem, and an object of the present invention is to provide a circuit in the case where a conventional differential amplifier circuit as shown in FIG. 3 is operated with an input voltage near the power supply reference potential Vgnd. Even if the absolute value of the threshold voltage of the PMOS transistor constituting the transistor is smaller than the absolute value of the threshold voltage of the NMOS transistor, all the transistors constituting the circuit are operated in the drain current saturation region. An object of the present invention is to provide a differential amplifier circuit that prevents a decrease in the differential voltage gain Amd, has a high voltage gain, and operates stably.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a differential amplifier circuit according to the present invention includes a pair of PMOS transistors forming a differential pair, a current mirror circuit composed of an NMOS transistor serving as a load of the transistors, and the pair of PMOS transistors. A level consisting of a source follower circuit composed of a PMOS transistor with a constant current source as a load at the inverting input terminal and non-inverting input terminal of a differential circuit consisting of a constant current circuit that supplies a constant current to sources connected in common to the transistors A differential amplifier circuit configured by connecting shift circuits to each other, wherein the PMOS transistors constituting the differential pair and the source follower circuit have the same threshold voltage, and the values thereof are NMOS transistors constituting the current mirror circuit Characterized by being formed to be 1/2 or more of the threshold voltage of A.
In the differential amplifier circuit having such a configuration, when the threshold voltage of the PMOS transistor is V thP and the threshold voltage of the NMOS transistor is V thN , the input voltage of the differential amplifier circuit is a negative value, for example. Also,( ｜ V thN ｜ − If the value is 2 | V thP |) or more, there is an advantage that a high differential voltage gain can be obtained when the difference between the two input voltages of inversion and non-inversion is small.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of an embodiment of the present invention will be described with reference to FIG. In the figure, 1 is a first level shift circuit, and 2 is a second level shift circuit. The circuit portion excluding the first and second level shift circuits 1 and 2 is the same as that of the differential amplifier circuit shown in FIG. 3, and the configuration and operation thereof are as described in detail in the section “Prior Art”. It is. (In FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals.)
[0018]
The first level shift circuit is a source follower circuit configuration in which two PMOS transistors P5 and P6 are connected in cascade. The source of one transistor P6 is connected to a power supply line for supplying a power supply voltage Vdd, and the other transistor The drain of P5 is connected to the power supply reference potential Vgnd.
A connection point 3 between the source of the commonly connected transistor P5 and the drain of the transistor P6 is where the output voltage of the first level shift circuit appears, and is connected to the gate of the transistor P1, which is the inverting input terminal of the differential pair. The The input voltage Vin is applied to the gate of the transistor P5 connected to the power supply reference potential Vgnd side, while the gate of the transistor P6 connected to the power supply Vdd side is connected to the gate of the transistor P4.
[0019]
Here, the voltage between the gate and the source of the transistor P4 is constant and almost equal to the threshold voltage of the PMOS transistor if the current driving capability of the transistor P4 is formed high because the gate and the drain are connected in common. Value. Accordingly, since the gate-source voltage of the transistor P6 is also maintained at a constant value almost equal to the threshold voltage of the PMOS transistor, the transistor P6 operates as a current source, and the transistor P5 connected to the power supply reference potential Vgnd side. A constant current Id6 is supplied to the drain. As a result, the potential Vin1 at the connection point 3 corresponding to the output of the first level shift circuit becomes a potential obtained by adding the absolute value | VgsP5 | of the gate-source voltage of the transistor P5 to the gate potential of the transistor P5. This voltage | VgsP5 | depends on the drain current Id6 supplied to the transistor P5. However, if the transistor P5 has the ability to sufficiently drive the drain current Id6, the absolute value of the threshold voltage of the PMOS transistor A value almost equal to | VthP |. Therefore, the following equation holds.
Vin1 ≒ Vin + | VthP | Equation (8)
The configuration and operation of the second level shift circuit 2 are also the same as those of the first level shift circuit 1. The difference is that the other input voltage Vref of the differential input is applied to the gate of the transistor P7 connected to the power supply reference potential Vgnd side, and the source of the transistor P7 which is the level-shifted output is not in the differential pair. This is a point connected to the gate of the transistor P2, which is an inverting input terminal.
[0021]
The same conditions as those discussed in the section “Prior Art” of this circuit, that is, the terminal for supplying the reference voltage Vref is connected to the power supply reference potential Vgnd to be 0 V, and the minute voltage near the power supply reference potential Vgnd is set as the input voltage Vin. In addition, it is assumed that it is operated. In this case, the conditions under which all transistors in the circuit operate in the saturation region are as follows by substituting Vin1 in equation (8) for Vin in equation (6).
2 | VthP | + Vin ≧ VdsN1 ≧ | VthN | (9) Therefore, when VdsN1 is almost equal to | VthN |, the following equation is obtained even if the input voltage Vin is 0V:
2 | VthP | ≧ | VthN |
If the threshold voltages of the transistors are designed so as to hold, all the transistors operate in the saturation region, and a high differential voltage gain can be obtained.
[0022]
The following relationship is obtained from the equation (9).
Vin ≧ | VthN | −2 | VthP | Equation (10) Therefore, as long as the input voltage Vin is negative as long as this equation (10) is satisfied, all the transistors operate in the saturation region and are high. A differential voltage gain is obtained.
[0023]
The transistors P6 and P8 in the first and second level shift circuits serve to supply a constant current to the input transistors P5 and P7, respectively. Any constant current circuit that can always supply a constant current to the input transistors P5 and P7 may be used. Similarly, the transistor P3 in the figure plays a role of supplying a constant current to the source common connection point of the transistors P1 and P2 forming the differential pair, and is not limited to the circuit shown in the figure. It is also possible to use a circuit of another type that can flow.
[Brief description of the drawings]
FIG. 1 is an electrical configuration diagram of a differential amplifier circuit according to an embodiment of the present invention. FIG. 2 is a general output characteristic diagram of a source grounding of a MOS transistor. FIG. Explanation of symbols]
In the drawing, 1 and 2 are level shift circuits, Vdd is a power supply voltage, Vgnd is a reference potential of the power supply, Vin and Vref are differential input voltages, Vout is an output voltage, N1 and N2 are NMOS transistors, and P1 to P8 are PMOS transistors. Indicates.

Claims (2)

A current mirror circuit composed of a pair of PMOS transistors forming a differential pair, an NMOS transistor serving as a load of the transistors, and a constant current circuit for supplying a constant current to the commonly connected sources of the pair of PMOS transistors A differential amplifier circuit configured by connecting a level shift circuit composed of a source follower circuit composed of a PMOS transistor having a constant current source as a load to the inverting input terminal and the non-inverting input terminal of the differential circuit,
The PMOS transistors constituting the differential pair and the source follower circuit have the same threshold voltage, and the value is set to be 1/2 or more of the threshold voltage of the NMOS transistor constituting the current mirror circuit. There is a differential amplifier circuit.   2. The differential amplifier circuit according to claim 1, wherein the constant current source of the source follower circuit comprises a PMOS transistor having a source connected to a power source and a constant voltage applied to a gate.

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