JPS649737B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a complementary MIS circuit (CMOS circuit)
Regarding devices, by adding a constant voltage circuit device to a CMOS integrated circuit, latch-up, which is the biggest weakness of CMOS circuits, can be prevented.

A basic circuit diagram of a monolithic CMOS integrated circuit is shown in FIG. CMOS inverter is
P channel MOS transistor Tp and N channel
Consisting of a MOS transistor T _N , the source of Tp is connected to a high potential source V _DD , the source of T _N is connected to a low potential source V _SS ,
The drains of both transistors are the common output terminal
OUT, both gates are commonly connected to the input terminal IN.

When the input is at 0 level, Tp is conductive and T _N is non-conductive, so the output OUT is at 1 level. When the input becomes 1 level, Tp becomes non-conductive and _TN becomes conductive, so the output OUT becomes 0 level. In either case, one MOS transistor becomes non-conductive, so no current flows between V _DD and V _SS , and current flows only in the transition region between the 1 level and 0 level of the input potential, resulting in low power consumption. There are fewer advantages.

FIG. 2 is an example of a cross-sectional view of the element shown in FIG. 1.
N ^- bulk is an n-type semiconductor substrate, 3, 4, and 5 are the source, channel, and drain of n-channel MOS transistor T _N , and 8, 9, and 10 are p-channel MOS transistors.
Drain, channel, source of transistor Tp,
2, 6, 7, 11 are guard rings, P well is p
This is the well layer of the mold.

In general, the V _DD − of a monolithic CMOS integrated circuit is
Between V _SS , PNPN along the dashed line A in Figure 2.
It is well known that a diode structure, that is, a thyristor structure is equivalently constructed.

_{The voltage} current (V
-I) The characteristics are as shown in FIG. 3, and in the normal operation mode, the device operates with a small portion of the current on the curve between OA and A. However, when a voltage that causes the latch-up limit voltage V _LU is applied between V _DD and V _SS (even if it is spike-like), the operation mode of this element shifts between B and C, where a large current flows. This B-
The area between C and C is the latch-up area of the CMOS circuit.

Once latch-up occurs, as shown in Figure 3, the state will be maintained unless the voltage between V _DD and V _SS is lowered below V _H (minimum holding voltage) or the current is lowered below I _H (minimum holding current). .

Conventionally, as a method to prevent latch-up, for example, as shown in Fig. 4, the high potential source side of V _DD and C MOS,
There is also a method of inserting a resistor into either or both of V _SS and the low potential source side of the CMOS to limit the current that causes latch-up and the abnormal current caused by latch-up, thereby preventing element deterioration or burnout.

However, this method is not suitable for ON-
These resistors have the disadvantage of causing a voltage drop when switching OFF quickly and a large amount of transient current flows, or when you want to extract current from the CMOS circuit to the output. Therefore, in such a structure, there is a problem that high speed operation and sufficient amplitude of H and L levels cannot be obtained.

The object of the present invention is to provide a CMOS integrated circuit with
The purpose is to prevent latch-up due to noise from the power supply or rise in power supply voltage, and to ensure that there is no hindrance to normal operation.

The present invention relates to a semiconductor substrate of one conductivity type, a well layer of an opposite conductivity type formed in the semiconductor substrate,
A channel MIS transistor of opposite conductivity type formed in the semiconductor substrate and a channel MIS transistor of one conductivity type provided in the well layer, between a high potential source V _DD and a low potential source V _SS In a complementary MIS integrated circuit device, the high potential source V _DD and the low potential source V a constant voltage circuit device inserted between _{the SS} and the predetermined circuit in parallel with the semiconductor substrate or the well layer;
The voltage at which the constant voltage circuit device operates is set to the high potential source.
V _DD voltage higher than the latch-up limit voltage
It is characterized by being set lower than V _LU .

FIG. 5 is a basic configuration diagram of the present invention. If the operating voltage of the constant voltage circuit device is set to be lower than the latch-up limit voltage V _LU shown in Figure 3, the CMOS circuit will remain stable even if spyer noise from the power supply is added or the power supply voltage attempts to rise. high potential source
Since the voltage between V _DD and the low potential source V _SS is suppressed by the operating voltage of the constant voltage circuit device, it does not enter the latch-up region.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 6 shows an embodiment of the present invention. In this embodiment, an inverter circuit consisting of a p-channel MIS transistor Tp and an n-channel MIS transistor T _N is provided between a high potential source V _DD and a low potential source V _SS , and a Zener diode Z _D is used as a constant voltage circuit device.
is installed in parallel with the inverter circuit between V _DD and V _SS to utilize its constant voltage characteristics.

In other words, even if spyer noise that causes a latch-up is added between V _DD and V _SS or an excessive voltage is applied, the voltage between V _DD and V _SS will not exceed the voltage that causes reverse breakdown of the Zener diode Z _D. Latch-up does not occur because it is held down by FIG. 7 is a cross-sectional view of the device of the embodiment of FIG. 6. 1,2
is a Zener diode, 3, 4, and 5 are N channels.
MOS transistor source, channel, drain, 8, 9, 10 are p channel MOS transistor drain, channel, source, 2, 6, 7,
11 is a guard ring. According to this method, latch-up does not occur even if noise enters the power supply or the power supply voltage increases significantly. In addition, since only the Zener diode Z _D is added, the degree of integration is hardly reduced.

Figures 8a and b show an embodiment of the present invention in a CMOS NAND gate circuit and its truth table, and Figure 9 shows an embodiment of the present invention in a CMOS NOR gate circuit and its truth table. Tp ₁ and Tp ₂ are P-channel transistors, T _N1 and T _N2 are N-channel transistors, Z _D is a Zener diode of a constant voltage circuit device, A and B are input terminals, and S is an output terminal.

According to the present invention, it is possible to prevent latch-up due to noise from the power supply or rise in power supply voltage by simply adding a small constant voltage circuit within the CMOS integrated circuit.

Furthermore, by using a Zener diode provided in the substrate as a constant voltage circuit, a CMOS integrated circuit can be formed without impairing the degree of integration.

Furthermore, under normal operating conditions, the Zener diode Z _D does not do anything that limits its operation.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit diagram of a CMOS inverter, Fig. 2 is an element structure diagram of a monolithic CMOS integrated circuit, and Fig. 3 is a diagram showing the voltage and current of the PNPN structure along the dashed line A in Fig. 2. The characteristics, Figure 4, are
An example of a latch-up prevention method according to the prior art, FIG. 5 is a basic configuration diagram of the present invention, FIG. 6 is a circuit diagram showing an embodiment of the present invention, and FIG. 7 is an element structure of the circuit of FIG. 6. 8a and 8b are a circuit diagram of a NAND circuit according to another embodiment of the present invention and its truth table,
FIGS. 9a and 9b are a circuit diagram of another NOR circuit according to the present invention and its truth table. In the figure, Tp is a P channel MIS transistor, T _N
is an N-channel MIS transistor, the dashed-dotted line A is the trace of a latch-up, and Z _D is a Zener diode.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a well layer of an opposite conductivity type formed in the semiconductor substrate, a channel MIS transistor of an opposite conductivity type formed in the semiconductor substrate, and the well layer. A channel MIS transistor of one conductivity type is provided between the high potential source _VDD and a low potential source _VSS , and the MIS transistor of the one conductivity type channel and the MIS transistor of the opposite conductivity type channel are provided In a complementary MIS integrated circuit device comprising a predetermined circuit, a constant voltage circuit device is inserted between the high potential source V _DD and the low potential source V _SS and is in parallel with the predetermined circuit. is provided in the semiconductor substrate or the well layer, and the voltage at which the constant voltage circuit device operates is set higher than the voltage of the high potential source _VDD and lower than the latch-up limit voltage _VLU . Type MIS integrated circuit device.