KR960000050Y1 - Output buffer circuit - Google Patents

Abstract

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Description

Output buffer circuit

1 is a circuit diagram showing an example of the output buffer circuit of the present invention

2 is an enlarged perspective view showing a part of a general MOS transistor broken.

3 is a circuit diagram showing an example of a conventional output buffer circuit.

4 is a characteristic diagram showing breakdown characteristics

* Explanation of symbols for main parts of the drawings

1: dummy PMOS transistor 2: dummy NMOS transistor

3: PMOS transistor 4: NMOS transistor

5: Output terminal 6: Input terminal

The present invention relates to an output buffer circuit in a semiconductor device such as a memory device, and in particular, to realize the improvement of the electrostatic strength.

The present invention provides an improvement in electrostatic strength by providing a MOS transistor connected to an output terminal in parallel with an output buffer MOS transistor in an output buffer circuit in a semiconductor device such as a memory device.

An example of an output buffer circuit in a semiconductor device such as a memory device will be described with reference to FIG. 3. First, a sense amplifier that is connected to a memory cell that stores an information signal and senses a signal read in accordance with an address signal The so-called driver 32 is connected to the output terminal of 31, and this driver 32 is connected to the input terminal 33 of the output buffer circuit. The output buffer circuit consists of a PMOS transistor 34 and an NMOS transistor 35, and the input terminal 33 is connected to the gates of the PMOS transistor 34 and the NMOS transistor 35, respectively. Sources of the PMOS transistor 34 and the NMOS transistor 35 are connected to a power supply voltage or earth, respectively, and the drains of the PMOS transistor 34 and the NMOS transistor 35 are commonly connected to the output terminal 36. It is.

In the output buffer circuit having the above-described configuration, in the conventional design rule, since the MOS transistors 34 and 35 themselves constituting the output buffer circuit functioned as an electrostatic protection circuit, a special protection circuit Did not need. That is, as shown in FIG. 2, in the MOS transistor, the MOS transistor is formed by a depletion layer 23 from the PN junction 22 formed in the impurity region 21 on the drain D side at the time of reverse bias. It functions as a protective diode itself, so that breakdown at the portion a (near the surface side of the channel side of the PN junction 22) occurs at a lower voltage than the electrostatic breakdown voltage, and thus it is possible to prevent the electrostatic breakdown in advance.

However, as the size of the memory device progresses, the channel width W of the MOS transistor of the output buffer circuit is also reduced, and when the channel width W is shortened as described above, the breakdown voltage increases as indicated by the broken line in FIG. Occurs, and therefore, the output buffer circuit cannot be effectively protected from electrostatic breakdown.

That is, when the channel width W is shortened, the volume of the substrate 24, the well region 25, etc., which surround the PN junction 22, becomes relatively large, and the voltage applied to the depletion layer 23 by the resistance thereof. This degrades. Therefore, at the voltage at which breakdown occurs, breakdown has not yet occurred due to the resistance, and breakdown occurs. In addition, shortening the channel width W increases the current per unit area, and electrostatic breakdown is likely to occur.

In contrast, unless the channel width W is shortened, the breakdown voltage does not have to increase.

However, if the channel width W is not shortened, the drive capacity of the output buffer circuit becomes larger than necessary, and parasitic depending on the transient current when driving the load capacitance 37 as shown in FIG. This may adversely affect the power supply voltage, ground voltage, etc. due to inductance, etc., and may cause malfunction.

On the other hand, even if the channel length L of the MOS transistor of the output buffer circuit is longer than that of the MOS transistor such as a memory cell, the channel width can be reversed without shortening the channel width and increasing the driving capability more than necessary.

In this case, however, the gate capacitance (depending on the area of the gate electrode G in FIG. 2) of the MOS transistors 34 and 35 of the output buffer circuit as shown in FIG. This causes disadvantages such as delays, disadvantageous power consumption and pattern area contact, and the need to increase the driving capability of the driver 32, the sense amplifier 31 and the like.

In view of the above-described problems, the present invention aims to provide an output buffer circuit that effectively prevents electrostatic breakdown even when the channel width W is shortened.

The present invention provides a first conductive type FET 3 (P channel FET) having a source connected to a power supply (V _DD ), a drain connected to an output terminal, a gate connected to an input terminal, and a gate connected to the input terminal. A second conductive FET 4 (N-channel FET) of a second conductivity type connected to the source, the source is grounded, and the drain is connected to the output terminal, and the first FET 3 and the second A third output of the first conductivity type in which a complementary output buffer circuit having a short channel width W of the FET 4 is connected, a source and a gate are connected to the power supply, and a drain is connected to the output terminal. The above-mentioned problem is solved by the output buffer circuit which consists of the FET 1, the 4th FET 2 of the 2nd conductivity type whose source and gate are grounded, and the drain is connected to the said output terminal.

The present invention has a MOS transistor connected to the output terminal in parallel with the MOS transistor for the output buffer.

The MOS transistor connected to this output terminal functions as an diode equivalently from the output side, and substantially the same effect as having made the channel width W substantially short while keeping the channel width W of the output buffer MOS transistor short is obtained. have.

That is, for example, there is an inflow of electric charge from the output terminal due to static electricity or the like, and this becomes a voltage and is applied to the output terminal, but not only the impurity region of the output buffer MOS transistor but also the output terminal of the MOS transistor functioning as a protection diode. The voltage is equally applied to each PN junction of the impurity regions to be connected, and thus the area to which the voltage is applied increases, so that the resistance of the substrate or the like is relatively small. When the resistance is small, breakdown occurs at a low voltage without contribution of the resistance as shown by the solid line during the fourth period, and thus breakdown of the insulation can be prevented in advance. In this way, a substantial current density can be reduced, and electrostatic breakdown can be effectively suppressed.

A preferred embodiment of the present invention will be described with reference to the drawings.

This embodiment is an output buffer circuit of a memory device that stores information signals, and has a circuit configuration of CMOS.

First, as shown in FIG. 1, in the output buffer circuit of this embodiment, a gate is connected to the input terminal 6, respectively, and a first FET of the first conductivity type that is used as an output buffer MOS transistor ( PMOS transistor 3, which is a P-channel FET, and an NMOS transistor 4, which is a second FET (N-channel FET) of a second conductivity type, and the source of the PMOS transistor 3 is a power supply level (V _DD ). On the other hand, the source of the NMOS transistor 4 is at ground level. A dummy PMOS transistor 1, which is a third FET of the first conductivity type for functioning as a protection diode in parallel with the PMOS transistor 3, is disposed, and functions as a protection diode in parallel with the NMOS transistor 4. A dummy NMOS transistor 2, which is a fourth FET of a second conductivity type, is disposed. Each drain side of the dummy PMOS transistor 1 and the dummy NMOS transistor 2 is connected to an output terminal 5, and similarly, each drain side of the PMOS transistor 3 and the NMOS transistor 4 is also an output terminal ( 5). Each gate of the dummy PMOS transistor 1 and the dummy NMOS transistor 2 is connected to a respective source, and each gate of the dummy PMOS transistor 1 and the dummy NMOS transistor 2 is respectively It is connected to a source, and the gate of the dummy PMOS transistor 1 is at the power supply level, and the gate of the dummy NMOS transistor 2 is at the ground level.

In the input terminal 6 of the output buffer circuit having such a configuration, for example, a sense amplifier 8 for detecting a weak information signal from a capacitor of a memory cell of a memory device and outputting a predetermined read level is described above. And a signal from the driver 7 is input to the output buffer circuit, and the CMOS output stages of the PMOS transistor 3 and the NMOS transistor 4 are in use. The output is made by the output.

The output buffer circuit of this embodiment having the above-described configuration is used for the dummy PMOS transistor 1 and the dummy for use as a protection diode in addition to the PMOS transistor 3 and the NMOS transistor 4 used for driving the load according to the input signal. The NMOS transistor 2 is connected to the output terminal 5. Therefore, even when the channel width W of the PMOS transistor 3 and the NMOS transistor 4 is shortened, good breakdown characteristics can be obtained, thereby improving the electrostatic protection function.

For example, even when static electricity or the like flows in from the output terminal 5, not only the impurity region connected to the output terminal 5 of the PMOS transistor 3 or the NMOS transistor 4, but also the above-mentioned impurity region. The voltage is similarly applied to each PN junction of the impurity region connected to the output terminal 5 of the cosmetic PNMS transistor 1 or the dummy NMOS transistor 2. This means that the area functioning as a diode from the output shaft is enlarged. Therefore, as described above, since the resistance of the substrate, the well area, etc. is relatively reduced, a good breakdown can be achieved without increasing the channel width W of the MOS transistor for the output buffer at all. Characteristics can be obtained. Since the output buffer circuit of this embodiment has a CMOS configuration, breakdown may occur in the MOS transistor on the side having the PN junction biased by a predetermined voltage or more in the reverse direction in each of positive and negative charges.

The output buffer circuit of the present embodiment having the above configuration is used when the dummy PMOS transistor 1 and the dummy NMOS transistor 2 are supplied with a constant potential to their gates, respectively, so that the output buffer circuit is used. I never do that. In designing the circuit, in particular, the circuit is designed without considering the electrostatic strength, the arbitrary channel width, the channel length is set, and finally, the dummy PMOS transistor 1 and the dummy NMOS transistor 2 are replaced. It shows that what should be added. Therefore, the use of the output buffer circuit of this embodiment has advantages not only in improving the electrostatic strength but also in circuit design.

In the above-described embodiment, the output buffer circuit of the CMOS has been described. However, the present invention is not limited thereto and may be used for other output buffer circuits.

By applying the output buffer circuit of the present invention, good breakdown characteristics can be obtained without sacrificing the channel width W or the channel length L, and therefore, the electrostatic strength can be improved. In addition, the MOS transistor disposed at the output terminal is not used in the normal driving operation, and therefore, the electrostatic strength can be improved by adding the MOS transistor after setting arbitrarily in circuit design.

In addition, since the channel width W and the channel length L are not sacrificed, noise characteristics, operating speed, power consumption, and pattern area can be made good.

Claims (1)

(Correction) A first conductive FET 3 (P channel FET) of a first conductivity type in which a source is a power supply (V _DD ), a drain is an output terminal, and a gate is connected to an input terminal, respectively, and a gate is connected to the input terminal. A second conductive FET 4 (N-channel FET) of a second conductivity type connected to the output terminal, the source is grounded, and the drain is connected to the first FET 3 and the second A complementary output buffer circuit in which the channel width W of the FET 4 is shortened; A third FET (1) of the first conductivity type having a source and a gate connected to the power supply, and a drain connected to the output terminal. An output buffer circuit comprising: a fourth FET (2) of the second conductivity type, wherein a source and a gate are grounded, and a drain is connected to the output terminal.