JP2798510B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which the state of an output signal must be fixed at a power-on state.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit of this type, for example, when a wired OR circuit or the like is formed by using a plurality of such integrated circuits, the initial state of the output signal level after turning on the power must be always high. Used when you have to.

FIG. 2A is a circuit diagram showing an example of a conventional semiconductor integrated circuit of this type. FIG. 2B shows an operation waveform diagram when the power is turned on.

In this semiconductor integrated circuit, a potential fixing circuit 2 provided on an IC chip 1 for fixing an output signal OUT at power-on to a high level, and an external signal IN
And a two-input OR circuit 4 that receives a signal A from the potential fixing circuit 2 and an internal signal B from the internal circuit 3 as inputs. The output of the OR circuit 4 is the output signal OUT.

As shown in FIG. 2A, the potential fixing circuit 2 includes P-channel MOS transistors P ₁ and P ₂ and a N-channel MOS transistor connected in a totem pole type between a high power supply terminal 5 and a ground terminal 6. MOS transistor N
And an inverter 7 connected to its output terminal, and the signal A is output from the output terminal of the inverter 7. In the potential fixing circuit 2, P-channel MOS transistor P ₁ has a gate diode-connected,
P-channel MOS transistor P ₂ is the ground potential is applied to the gate, N-channel MOS transistor N is the supply voltage is applied to the gate.

In this semiconductor integrated circuit, when power is turned on, a signal A from the potential fixing circuit 2
As shown in (b), the power supply voltage follows the power supply level (high level) from V _TN to 2 | V _TP |. Thereafter, the potential becomes the ground potential (low level). Here, V _TN is the threshold voltage of the N-channel MOS transistor N, and V _TP is the threshold voltage of the P-channel MOS transistors P ₁ and P ₂ .

In this semiconductor integrated circuit, as shown in FIG. 2A, the signal A from the above-described potential fixing circuit 2 is input to the two-input OR circuit 4, so that the OR circuit 4
(Output signal OUT) is fixed at a high level immediately after the power is turned on regardless of the level of the internal signal B from the internal circuit 3.

Thereafter, when the power supply voltage exceeds 2 | V _TP |, the signal A from the potential fixing circuit 2 goes low, so that the output signal OUT becomes a signal synchronized with the internal signal B from the internal circuit 3. .

[0009]

As described above, in the conventional semiconductor integrated circuit, the output signal OUT is fixed to a high level immediately after the power is turned on by the signal from the potential fixing circuit 2, and thereafter, this fixed signal is fixed. The level is released and becomes a signal synchronized with the signal from the internal circuit.

However, in the potential fixing circuit 2, the level of the output signal A at power-on is determined only by the threshold voltage of the MOS transistor, so that the level of the signal A depends on the threshold voltage of the MOS transistor. It changes greatly.

For example, when the threshold voltage V _TN of the N-channel MOS transistor N is two P-channel M
If the voltage value is close to 2 | V _TP | determined by the OS transistor, the operation becomes unstable, and the level of the output signal OUT from the OR circuit 4 immediately after power-on can be fixed at a high level. May disappear.

[0012]

A semiconductor integrated circuit according to the present invention performs a predetermined logical operation in response to an externally input signal.
An internal circuit and an output signal of the internal circuit are input, and
Two-input logic circuit that uses a synchronized signal as an output signal to the outside
Circuit and the potential state of the output when power is turned on.
Configuration, and depending on the output potential state,
The output logic of the logic circuit when power is turned on
In addition to fixing the signal from the internal circuit,
The potential state determined when the power is turned on is output from the internal circuit.
And a latch circuit released by the signal of

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a circuit configuration of one embodiment of the present invention.

The present embodiment differs from the conventional semiconductor integrated circuit shown in FIG. 2A in the portion of the potential fixing circuit 8. In this embodiment, the potential fixing circuit 8 includes a latch circuit 9 and two inverters 10 and 11 cascaded to the output terminal of the latch circuit 9.

The latch circuit 9 has a configuration in which a two-input NOR circuit 12 and an inverter 13 are connected in a flip-flop format.

In the latch circuit having such a circuit configuration, N
By appropriately setting the ratio of the magnitude of the current drive capability of the P-channel MOS transistor and the N-channel MOS transistor constituting the OR circuit 12 and the inverter 13, the level of the output (signal C) after power-on is always high. Level.

In addition, the potential state of the latch circuit 9 determined at the time of power-on is not reset unless the internal signal B input to one input terminal of the NOR circuit 12 becomes high level, and the signal C becomes high level. Keep keeping. In order to reset the potential state of the latch circuit 9 to make the signal C low, the internal signal B input to the latch circuit 9
To a high level.

In FIG. 1, when the power is turned on, the signal A from the potential fixing circuit 8 always goes high. Therefore, in this case, the output signal OUT of this semiconductor integrated circuit
Always goes to a high level, similarly to a conventional semiconductor integrated circuit.

Next, an input signal I from outside the IC chip
When the internal signal B from the internal circuit 3 goes high due to the change of N, the latch circuit 9 is reset and the signal A from the potential fixing circuit 8 goes low.

The output signal OUT is synchronized with the internal signal B from the internal circuit 3 unless the power is turned off thereafter.

When the internal signal B for resetting the latch circuit 9 is at the high level when the power is turned on, the output signal O
The level of the UT cannot be set to the high level by the signal A from the potential fixing circuit 8, but in this case, the O
In the R circuit 4, since the internal signal B input to one input terminal is at a high level, the output signal OUT is also at a high level.

[0022]

As described above, the semiconductor device of the present invention
The integrated circuit performs a predetermined logical operation according to an external input signal.
And an output signal of the internal circuit,
A signal synchronized with this is an output signal to the outside.
Logic circuit and output potential state when power is turned on
Is set to one of two potential states.
The logic of the output of the logic circuit when power is turned on
Is fixed regardless of the signal from the internal circuit.
In addition, the potential state determined at the time of turning on the power is
A latch circuit released by a signal from the circuit.
Have .

With this circuit configuration, according to the present invention,
The potential state of the output signal of the semiconductor integrated circuit after the power is turned on,
The signal can be fixed in a fixed direction without depending on the threshold voltage of the MOS transistor and regardless of the level of the internal signal .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional semiconductor integrated circuit and an operation waveform diagram when power is turned on.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IC chip 2, 8 Potential fixing circuit 3 Internal circuit 4 OR circuit 5 Higher power supply terminal 6 Ground terminal 7, 10, 11, 13 Inverter 9 Latch circuit 12 NOR circuit

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 17/22

Claims (1)

(57) [Claims] A predetermined logic operation according to an external input signal.
An internal circuit for performing the calculation, and a signal synchronized with the input signal of the output signal of the internal circuit.
A two-input logic circuit that outputs a signal to the outside and one potential state when the power is turned on.
Power supply depending on the output potential state.
The logic of the output of the logic circuit when turned on
In addition to fixing the signal from the circuit,
The potential state determined at the time of input is a signal from the internal circuit.
And a latch circuit released by the semiconductor integrated circuit.