JP2933466B2 - Input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly to an input circuit.
The present invention relates to an input circuit including an OS transistor.

[0002]

2. Description of the Related Art As shown in FIG. 9, a conventional input circuit of this type includes a MOS inverter formed by a P-channel MOS transistor 17 and an N-channel MOS transistor 18, and a P-channel MOS transistor. A MOS inverter formed by a transistor 19 and an N-channel MOS transistor 20 is connected in two stages in series, and a P-channel MOS transistor and an N-channel MOS in each MOS inverter are provided.
A transistor is generally configured to have a ratio configuration.

As another conventional example, as shown in FIG. 10, an external input signal (IN) is applied to a P-channel type M.
The gate is input to the MOS inverter formed by the OS transistor 23 and the N-channel type MOS transistor 24, and between the power supply voltage V _DD and the input terminal,
A pull-up circuit including a P-channel type MOS transistor 22 and a MOS inverter 21 is provided to form the input circuit (see Japanese Patent Application Laid-Open No. 3-230612,
JP-A-2-26816).

[0004]

In the above-mentioned conventional input circuit, the external input signals other than the power supply voltage and the ground potential level, for example, TTL levels (V _IH / V _IL)
= 2.4V / 0.8V), there is a drawback that a steady state current always flows in the first or next stage logic element.

In order to reduce the steady-state current, in the example shown in FIG. 9, a first-stage or a next-stage logic element has a ratio configuration. Further, in order to further reduce the steady-state current, a configuration using a pull-up circuit or the like is adopted as shown in the example of FIG. 10, but the steady-state current in the first-stage or next-stage logic element is suppressed. However, a steady current may flow in the pull-up circuit itself, and a reverse current may flow from the pull-up circuit to an external input signal. There is a disadvantage that there is.

[0006]

According to a first aspect of the present invention, there is provided an input circuit, wherein a source is connected to a high-potential power supply, and a gate and a drain are connected to the high-potential power supply via a predetermined capacitor. A low-voltage generating circuit comprising: a MOS transistor; and a second P-channel MOS transistor having a source connected to the drain of the first P-channel MOS transistor and having a gate and a drain set to a low-voltage output terminal. A third P-channel MOS having a source connected to the low-voltage output terminal, an external input signal input to the gate, and an output signal output from the drain
The transistor and the drain are the third P-channel type M
A first N-channel MOS transistor connected to the drain of the OS transistor, the gate connected to the gate of the third P-channel MOS transistor, and the source connected to the ground potential; A fourth P-channel MOS transistor having a source connected to the high-potential power supply, a drain connected to the drain of the third P-channel MOS transistor to which an output signal is output, and an input terminal connected to the fourth P-channel MOS transistor. The output terminal is connected to the drain of a P-channel type MOS transistor,
M connected to the gate of the channel type MOS transistor
And a pull-up circuit including an OS inverter.

The input circuit according to the second invention has a first N-channel MOS transistor having a drain and a gate connected to a high potential power supply, and a drain and a gate connected to the high potential power supply via a predetermined capacitance. A low-voltage generating circuit including a second N-channel MOS transistor connected to a source of the first N-channel MOS transistor and having a source set to a low-voltage output terminal; A first P-channel MOS transistor connected to an output terminal, an external input signal input to the gate, and an output signal output from the drain; and a drain connected to the drain of the first P-channel MOS transistor , The gate of which is connected to the gate of the first P-channel MOS transistor, and the source of which is connected to the ground potential. An input first-stage circuit including a third N-channel MOS transistor; a drain connected to a high-potential power supply; and a source connected to a drain of the first P-channel MOS transistor to which an output signal is output. A fourth N-channel MOS transistor having a gate connected to a high potential power supply and one of a drain and a source connected to the gate of the fourth N-channel MOS transistor; ,
An input terminal is connected to the source of the fifth N-channel MOS transistor, and an output terminal is connected to the fifth N-channel MOS transistor.
And a pull-up circuit including a MOS buffer connected to one of the source and the drain of the OS transistor.

In the input circuit according to a third aspect of the present invention, the source is connected to a high-potential power supply, and the gate and drain are connected to the high-potential power supply via a predetermined capacitor.
A low-voltage generating circuit including: an OS transistor; and a second P-channel MOS transistor having a source connected to the drain of the first P-channel MOS transistor and having a gate and a drain set to a low-voltage output terminal. A third P-channel MOS transistor having a source connected to the low-voltage output terminal, an external input signal input to the gate, and an output signal output from the drain, and a drain connected to the third P-channel MOS transistor A first N-channel MOS transistor having a gate connected to the gate of the third P-channel MOS transistor, a source connected to the low-voltage output terminal, and a gate having a predetermined control. A signal is input and the drain is connected to the drain of the third P-channel MOS transistor. Fourth P-channel type MOS is
A transistor and a drain are the first N-channel type M
An input first stage circuit including: a second N-channel MOS transistor connected to the source of the OS transistor; a gate connected to the gate of the fourth P-channel MOS transistor; and a source connected to the ground potential. A fifth P-channel MOS transistor having a source connected to the high-potential power supply, a drain connected to the drain of the fourth P-channel MOS transistor outputting an output signal, and an input terminal connected to the fifth P-channel MOS transistor. An MO connected to the drain of the P-channel MOS transistor and having an output terminal connected to the gate of the fifth P-channel MOS transistor
A pull-up circuit including an S inverter; and a control circuit that generates and outputs the control signal and controls the operation of the input first-stage circuit.

In the input circuit according to a fourth aspect of the invention, the source is connected to a high potential power supply, and the gate and the drain are connected to the high potential power supply via a predetermined capacitor.
A low-voltage generating circuit including: an OS transistor; and a second P-channel MOS transistor having a source connected to the drain of the first P-channel MOS transistor and having a gate and a drain set to a low-voltage output terminal. A third P-channel MOS having a source connected to the low-voltage output terminal and a gate supplied with a predetermined control signal
The transistor and the source are the third P-channel type MO.
A fourth P-channel MOS transistor which is connected to the drain of the S transistor, receives an external input signal at the gate, and outputs an output signal from the drain; and a drain connected to the drain of the fourth P-channel MOS transistor. And the gate is the fourth P-channel MOS
A first N-channel MOS transistor connected to a gate of the transistor and having a source connected to the ground potential; a drain connected to a drain of the first N-channel MOS transistor; An input first-stage circuit including a second N-channel MOS transistor having a source connected to the ground potential;
A fifth P-channel MOS transistor having a source connected to the high potential power supply, a drain connected to the drain of the fourth P-channel MOS transistor outputting an output signal, and an input terminal connected to the fifth P-channel MOS transistor; A pull-up circuit including a MOS inverter connected to the drain of the channel type MOS transistor and having an output terminal connected to the gate of the fifth P-channel type MOS transistor; and generating and outputting the control signal; And a control circuit for controlling the operation of the input first-stage circuit.

In the input circuit according to a fifth aspect of the present invention, a first N-channel MOS transistor having a drain and a gate connected to a high potential power supply, and a drain and a gate connected to the high potential power supply via a predetermined capacitance. A low-voltage generating circuit including a second N-channel MOS transistor connected to a source of the first N-channel MOS transistor and having a source set to a low-voltage output terminal; A first P-channel MOS transistor connected to an output terminal, an external input signal input to the gate, and an output signal output from the drain; and a drain connected to the drain of the first P-channel MOS transistor , A third N-channel MOS transistor having a gate connected to the gate of the first P-channel MOS transistor. And registers a source connected to the low voltage output terminal, a predetermined control signal to the gate is the input, a second P-channel type MOS having a drain connected to a drain of said first P-channel type MOS transistor
The transistor and the drain are the third N-channel type M
An input first stage circuit including: a fourth N-channel MOS transistor connected to the source of the OS transistor; a gate connected to the gate of the second P-channel MOS transistor; and a source connected to the ground potential. A fifth N-channel MOS transistor having a drain connected to the high-potential power supply and a source connected to the drain of the first P-channel MOS transistor to which an output signal is output; and a gate connected to the high-potential power supply. And a drain or a source connected to the gate of the fifth N-channel MOS transistor.
A transistor and an input terminal connected to the fifth N-channel type MO.
The output terminal is connected to the source of the S transistor
A pull-up circuit including a MOS buffer connected to one of a source and a drain of the N-channel MOS transistor; a control circuit that generates and outputs the control signal and controls the operation of the input first-stage circuit; It is comprised including.

According to a sixth aspect of the present invention, the input circuit includes a first N-channel MOS transistor having a drain and a gate connected to a high-potential power supply, and a drain and a gate connected to the high-potential power supply via a predetermined capacitor. A low-voltage generation circuit including a second N-channel MOS transistor connected to a source of the first N-channel MOS transistor and having a source set to a low-voltage output terminal; Connected to the low voltage output terminal,
A first P-channel MOS transistor having a gate to which a predetermined control signal is input, a source connected to the drain of the first P-channel MOS transistor, an external input signal input to the gate, and an output from the drain A second P-channel MOS transistor to which a signal is output;
A third N-channel MOS transistor having a drain connected to the drain of the second P-channel MOS transistor, a gate connected to the gate of the second P-channel MOS transistor, and a source connected to the ground potential; A transistor, a fourth N-channel transistor having a drain connected to the drain of the third N-channel MOS transistor, a gate connected to the gate of the first P-channel MOS transistor, and a source connected to the ground potential; An input first stage circuit including a channel type MOS transistor; a fifth N-channel having a drain connected to the high potential power supply and a source connected to a drain of the second P-channel type MOS transistor outputting an output signal; Type MOS transistor and a gate are connected to a high potential power source, and one of a drain and a source is 5 and a sixth N-channel type MOS transistor connected to the gate of N-channel type MOS transistor, the input end the fifth N-channel type MOS
A pull-up circuit including a MOS buffer connected to a source of the transistor and having an output terminal connected to one of a source and a drain of the sixth N-channel MOS transistor; and generating and outputting the control signal; And a control circuit for controlling the operation of the input first-stage circuit.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment includes a low-voltage generating circuit 3 including P-channel MOS transistors 31 and 32 and a capacitor 33, a pull-up circuit 4 including a P-channel MOS transistor 41 and a MOS inverter 42. , A power supply is supplied through a low-voltage generating circuit 3, and a P-channel type MOS to which an external input signal IN is gate-input.
An inverter formed by the transistor 11 and the N-channel MOS transistor 13 is provided. In this embodiment, the power supply voltage VDD is 5 V, and the low voltage generating circuit 3 is configured such that the high level of the external input signal IN is 3 V.

Referring to FIG. 1, a P-channel MOS transistor 11 and an N-channel MOS transistor 13
The power supply voltage is supplied from the low voltage generation circuit 3 to the inverter composed of the P-channel MOS transistor 11 when the external input signal IN is input at a low level (0.8 V). The N-channel MOS transistor 13 is turned off when the level difference between the gate level and the source level is equal to or lower than the threshold voltage _VTN . Correspondingly, in the pull-up circuit 4, the output of the inverter becomes high level, whereby the MOS inverter 42
, The P-channel MOS transistor 41 is turned on, and the output signal OUT is output at the power supply voltage V _DD level (5.0 V).

In this state, the external input signal IN is changed from the low level (0.8 V) to the high level (2.4 V).
, The N-channel MOS transistor 13 changes from the off state to the on state, so that the potential of the output signal OUT tries to decrease to the ground potential level (0 V) and at the same time, Since the MOS transistor 11 is on, the pull-up circuit 4
, The P-channel MOS transistor 41
The source-side potential level of the P-channel MOS transistor 11 is reduced to the level of (V _DD -2 {V _TP }) (V _TP is the threshold voltage of the P-channel MOS transistor 11). At this time, the level difference between the gate level and the source level of the P-channel MOS transistor 11 becomes equal to or lower than the potential level of the absolute value of the threshold voltage _VTP.
Is turned off, the output signal OUT falls to 0V, and at the same time, the output level of the MOS inverter 42 in the pull-up circuit 4 changes from low level (0V) to high level.
Level (V _DD ).
The transistor 41 is turned off. On this occasion,
There is no conduction state between the power supply voltage V _DD and the ground potential. Further, when the external input signal IN is at a high level (2.4
V) to a low level (0.8 V), the N-channel MOS transistor 13 changes from the on state to the off state, and the P-channel MOS transistor 11 changes from the off state to the on state. At the same time, the potential level of the output signal OUT rises from the low level (0 V) to the level (V _DD -2 {V _TP }), and at the same time, the output level of the MOS inverter 42 in the pull-up circuit 4 becomes high. Low level (0 V) from level (V _DD )
, Whereby the P-channel MOS transistor 41 changes from the off state to the on state, and the output signal OUT rises from the level of (V _DD -2 {V _TP }) to the V _DD level. At this time, no conduction state exists between the power supply voltage V _DD level and the ground potential level.

FIG. 2 is a diagram showing operation waveforms including the external input signal IN and the output signal OUT obtained as a result of simulating the operation of the first embodiment using existing data. In FIG. 2, the optimum design for the response speed and the like is not performed.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. As shown in the drawing, in the present embodiment, the internal configurations of the low voltage generating circuit 3 and the pull-up circuit 4 are different from those of the first embodiment. That is, in the present embodiment, the low-voltage generation circuit 3 and the pull-up circuit 4
In both cases, an N-channel MOS transistor is used in place of the P-channel MOS transistor. The low-voltage generating circuit 3 includes a capacitor 33 and N-channel MOS transistors 34 and 35, and a pull-up circuit 4 , N channel type MOS transistors 43 and 44 and a MOS buffer 45. The operation of this embodiment is similar to that of the first embodiment.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention. As shown in FIG. 4, in the present embodiment, an input first-stage circuit 1 including P-channel MOS transistors 11 and 12 and N-channel MOS transistors 13 and 14 is provided.
A control circuit 2 for generating and outputting a control signal for controlling an operation state and a non-operation state of the input first-stage circuit 1, a low-voltage generation circuit 3 including P-channel MOS transistors 31, 32 and a capacitor 33; A pull-up circuit 4 including a channel type MOS transistor 41 and a MOS inverter 42 is provided, and power is supplied to the input first stage circuit 1 via the low voltage generation circuit 3. As is clear from comparison with FIG. 1, in this embodiment, the internal configurations of the low-voltage generating circuit 3 and the pull-up circuit 4 are exactly the same as those of the first embodiment, and the first embodiment , An input first-stage circuit 1 is provided instead of the inverter. In this embodiment, the power supply voltage VDD is 5 V, and the low voltage generating circuit 3 is configured such that the high level of the external input signal IN is 3 V.

If the control signal output from the control circuit 2 is at a high level (power supply voltage VDD) and the external input signal IN is at a low level (0.8 V), the input first-stage circuit 1 P-channel MOS transistor 1
1 and the N-channel MOS transistor 14 are turned on, the P-channel MOS transistor 12 is turned off, and the N-channel MOS transistor 1 is turned off.
3 turns off when the level difference between the gate level and the source level is equal to or lower than the threshold voltage VTN. As a result, the output of the MOS inverter 42 in the pull-up circuit 4 goes low (ground potential), the P-channel MOS transistor 41 is turned on, and the output signal OUT goes to the VDD level (5.0 V). .

In this state, when the external input signal IN changes from low level (0.8) to high level (2.4 V), the N-channel MOS transistor 1
3 changes from the off state to the on state, the potential of the output signal OUT is about to decrease to the ground level (0 V), and at the same time, the P-channel MOS transistor 11 is in the on state. The P-channel type MOS transistor 41 allows the P-channel type M
The source side level of the OS transistor 11 (VDD−2VT)
P). At this time, the level difference between the gate level and the source level of the P-channel MOS transistor 11 becomes equal to or less than the absolute value of the threshold voltage VTP, and the P-channel MOS transistor 11 is turned off.
At the same time as the output signal OUT becomes 0 V, the output of the MOS inverter 42 in the pull-up circuit 4 also goes from low level (0 V) to high level (VDD), whereby the P-channel MOS transistor 41 is turned off. Become. At this time, no conduction state exists between VDD and ground.

Further, when the external input signal IN changes from the high level (2.4 V) to the low level (0.8 V), the N-channel MOS transistor 13 changes from the on state to the off state. Then, the P-channel MOS transistor 11 changes from the off state to the on state,
The output signal OUT changes from low level (0 V) to (VDD−2).
{VTP}) level, the output of the MOS inverter 42 in the pull-up circuit 4 changes from the high level (VDD) to the low level (0 V), and the P-channel MOS transistor 41 is turned on from the off state. As a result, the output signal OUT becomes (VDD−2)
{VTP}) level to the VDD level. On this occasion,
There is no conduction between the power supply voltage VDD and ground.

FIG. 5 is a diagram showing operation waveforms including the external input signal IN and the output signal OUT obtained as a result of simulating the operation of the third embodiment using existing data. In FIG. 2, the optimum design for the response speed and the like is not performed.

When the control signal output from the control circuit 2 is at a low level (0 V), the external input signal IN
The level of the output signal OUT is high regardless of the level of the
Level (VDD) and there is no conduction state between the power supply voltage VDD and the ground.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. As shown in FIG.
An input first-stage circuit 1 including P-channel MOS transistors 11 and 12 and N-channel MOS transistors 13 and 14, and a control circuit 2 for generating and outputting a control signal for controlling an operation state and a non-operation state of the input first stage circuit When,
The input first-stage circuit 1 includes a low-voltage generation circuit 3 including P-channel MOS transistors 31 and 32 and a capacitor 33, and a pull-up circuit 4 including a P-channel MOS transistor 41 and a MOS inverter 42. Power is supplied through the low voltage generation circuit 3.
As is clear from comparison with FIG. 4, in the present embodiment, the internal configurations of the low-voltage generating circuit 3 and the pull-up circuit 4 are exactly the same as those of the third embodiment.
There is a difference in the interconnection relationship between the channel MOS transistors 11 and 12 and the N channel MOS transistors 13 and 14. In the fourth embodiment, when the control signal output from the control circuit 2 is at a low level, the P-channel MOS transistor 12 is turned on, and the N-channel MOS transistor 14 is turned off. The input first-stage circuit 1 is in the operating state, and the operation as the input circuit in this case is the same as that in the case where the control signal of the third embodiment is at the high level. When the control signal is at a high level, the input first-stage circuit 1 is in a non-operating state, and the output signal OUT is at a low level (0 V) regardless of the level of the external input signal IN.

FIGS. 7 and 8 are circuit diagrams showing fifth and sixth embodiments of the present invention, respectively.
In the case of the third embodiment, the internal configuration of the input first stage circuit 1 is the same as that of the third embodiment, and the internal configurations of the low voltage generating circuit 3 and the pull-up circuit 4 are the same as those of the second embodiment. It is. In the case of the sixth embodiment, the internal configuration of the input first-stage circuit 1 is the same as that of the fourth embodiment, and the internal configurations of the low-voltage generation circuit 3 and the pull-up circuit 4 are the second.
This is the same as the embodiment. These fifth and sixth
The operation of this embodiment is the same as that of the third and fourth embodiments, respectively.

[0026]

As described above, the present invention provides an input first-stage circuit that receives an external input signal, a low-voltage generating circuit that supplies a power supply voltage to the input first-stage circuit, and an operation state of the input first-stage circuit. / A control circuit for controlling the non-operating state and a pull-up circuit connected to the output signal of the input first stage circuit, so that an external input signal corresponding to an input such as a TTL level other than the power supply voltage and the ground potential can be handled. Even in the state, there is no conduction state between the power supply voltage and the ground, and there is an effect that a steady current at the time of signal input, a steady current and a reverse current in the pull-up circuit, and the like can be eliminated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is an operation waveform diagram in the third embodiment.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a conventional example.

FIG. 10 is a circuit diagram showing another conventional example.

[Explanation of symbols]

Reference Signs List 1 input initial stage circuit 2 control circuit 3 low voltage generation circuit 4 pull-up circuit 11, 12, 17, 19, 22, 23, 31, 32, 4
1. P-channel MOS transistors 13, 14, 18, 20, 24, 34, 35, 43, 4
4. N-channel type MOS transistor 21, 42 MOS inverter 45 MOS buffer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 19/0185

Claims (6)

(57) [Claims] 1. A first P-channel MOS transistor having a source connected to a high-potential power supply, a gate and a drain connected to the high-potential power supply via a predetermined capacitor, and a source connected to the first P-channel MOS transistor. A low-voltage generation circuit including a second P-channel MOS transistor connected to the drain of the MOS transistor and having a gate and a drain set to a low-voltage output terminal; a source connected to the low-voltage output terminal; A third P-channel MOS transistor, which receives an external input signal and outputs an output signal from the drain, a drain connected to the drain of the third P-channel MOS transistor, and a gate connected to the third P-channel MOS transistor. P-channel type MO
An input first-stage circuit including a first N-channel MOS transistor connected to the gate of the S transistor and having a source connected to the ground potential; a source connected to the high-potential power supply; A fourth P-channel MOS transistor connected to the drain of the third P-channel MOS transistor; an input terminal connected to the drain of the fourth P-channel MOS transistor; and an output terminal connected to the fourth P-channel MOS transistor. And a MOS inverter connected to the gate of the P-channel type MOS transistor. 2. A first N-channel MOS transistor having a drain and a gate connected to a high potential power supply,
The drain and the gate are connected to a high potential power supply via a predetermined capacitor, and the first N-channel MOS
A low-voltage generating circuit including a second N-channel MOS transistor connected to the source of the transistor and having the source set to a low-voltage output terminal; a source connected to the low-voltage output terminal; A first P-channel MOS transistor which receives an input signal and outputs an output signal from a drain; a drain connected to the drain of the first P-channel MOS transistor; and a gate connected to the first P-channel MOS transistor Type MO
An input first-stage circuit including a third N-channel MOS transistor connected to the gate of the S transistor and having a source connected to the ground potential; a drain connected to the high-potential power supply; A fourth N-channel MOS transistor connected to the drain of the first P-channel MOS transistor; a gate connected to a high potential power supply; and one of a drain and a source connected to the fourth N-channel MOS transistor. Fifth N-channel type M connected to the gate of MOS transistor
An OS transistor; and a MOS buffer having an input terminal connected to the source of the fifth N-channel MOS transistor and an output terminal connected to one of the source or the drain of the fifth N-channel MOS transistor. An input circuit, comprising: a pull-up circuit; 3. A first P-channel MOS transistor having a source connected to a high-potential power supply, a gate and a drain connected to the high-potential power supply via a predetermined capacitor, and a source connected to the first P-channel MOS transistor. A low-voltage generation circuit including a second P-channel MOS transistor connected to the drain of the MOS transistor and having a gate and a drain set to a low-voltage output terminal; a source connected to the low-voltage output terminal; A third P-channel MOS transistor, which receives an external input signal and outputs an output signal from the drain, a drain connected to the drain of the third P-channel MOS transistor, and a gate connected to the third P-channel MOS transistor. P-channel type MO
A first N-channel MOS transistor connected to the gate of the S transistor, a source connected to the low-voltage output terminal, a predetermined control signal input to the gate, and a drain connected to the third P-channel MOS transistor A fourth P-channel MOS transistor connected to the drain of the transistor; a drain connected to the source of the first N-channel MOS transistor; and a gate connected to the fourth P-channel MOS transistor.
Connected to the gate of the channel type MOS transistor,
A second N-channel type MO whose source is connected to the ground potential
An input first-stage circuit including an S transistor; a fifth P-channel MOS transistor having a source connected to the high-potential power supply and a drain connected to the drain of the fourth P-channel MOS transistor outputting an output signal; A pull-up circuit including: a transistor; an MOS inverter having an input terminal connected to the drain of the fifth P-channel MOS transistor and an output terminal connected to the gate of the fifth P-channel MOS transistor; A control circuit that generates and outputs the control signal and controls the operation of the input first-stage circuit. 4. A first P-channel MOS transistor having a source connected to a high-potential power supply and a gate and a drain connected to the high-potential power supply via a predetermined capacitor;
A low-voltage generation circuit including a second P-channel MOS transistor having a source connected to the drain of the first P-channel MOS transistor, and a gate and a drain set to a low-voltage output terminal; A third P-channel MOS transistor connected to the low-voltage output terminal and having a gate supplied with a predetermined control signal; a source connected to the drain of the third P-channel MOS transistor; Is input and an output signal is output from the drain, a drain is connected to the drain of the fourth P-channel MOS transistor, and the gate is connected to the fourth P-channel MOS transistor. A first n-channel MOS connected to the gate of the transistor and having the source connected to ground potential A second N-channel MOS transistor having a drain connected to a drain of the first N-channel MOS transistor, a gate receiving the control signal, and a source connected to the ground potential; An input first-stage circuit, a fifth P-channel MOS transistor having a source connected to the high-potential power supply and a drain connected to the drain of the fourth P-channel MOS transistor from which an output signal is output, A pull-up circuit including a MOS inverter connected to the drain of the fifth P-channel MOS transistor and having an output terminal connected to the gate of the fifth P-channel MOS transistor; And a control circuit for controlling the operation of the input first-stage circuit. 5. A first N-channel MOS transistor having a drain and a gate connected to a high potential power supply,
The drain and the gate are connected to a high potential power supply via a predetermined capacitor, and the first N-channel MOS
A low-voltage generating circuit including a second N-channel MOS transistor connected to the source of the transistor and having the source set to a low-voltage output terminal; a source connected to the low-voltage output terminal; A first P-channel MOS transistor which receives an input signal and outputs an output signal from a drain; a drain connected to the drain of the first P-channel MOS transistor; and a gate connected to the first P-channel MOS transistor Type MO
A third N-channel MOS transistor connected to the gate of the S transistor, a source connected to the low-voltage output terminal, a predetermined control signal input to the gate, and a drain connected to the first P-channel MOS transistor A second P-channel MOS transistor connected to the drain of the transistor; a drain connected to the source of the third N-channel MOS transistor; and a gate connected to the second P-channel MOS transistor.
Connected to the gate of the channel type MOS transistor,
Fourth N-channel type MO whose source is connected to ground potential
An input first stage circuit including an S transistor; a fifth N-channel MOS transistor having a drain connected to a high potential power supply and a source connected to a drain of the first P-channel MOS transistor from which an output signal is output. A sixth N-channel type M transistor in which a transistor and a gate are connected to a high potential power supply and one of a drain and a source is connected to a gate of the fifth N-channel type MOS transistor;
An OS transistor; and a MOS buffer having an input terminal connected to the source of the fifth N-channel MOS transistor and an output terminal connected to one of the source or the drain of the sixth N-channel MOS transistor. An input circuit, comprising: a pull-up circuit; and a control circuit that generates and outputs the control signal and controls an operation of the input first-stage circuit. 6. A first N-channel MOS transistor having a drain and a gate connected to a high potential power supply,
The drain and the gate are connected to a high potential power supply via a predetermined capacitor, and the first N-channel MOS
A low-voltage generating circuit including a second N-channel MOS transistor connected to a source of the transistor and having a source set to a low-voltage output terminal; a source connected to the low-voltage output terminal; And a source connected to the drain of the first P-channel MOS transistor, an external input signal input to the gate, and an output signal output from the drain. A second P-channel MOS transistor to be connected, a drain connected to the drain of the second P-channel MOS transistor, a gate connected to the gate of the second P-channel MOS transistor, and a source grounded A third N-channel MOS transistor connected to the potential, and a drain connected to the third N-channel MOS transistor. An input first-stage circuit including: a fourth N-channel MOS transistor connected to the drain of the S transistor; a gate connected to the gate of the first P-channel MOS transistor; and a source connected to the ground potential. A fifth N-channel MOS transistor having a drain connected to the high-potential power supply, a source connected to the drain of the second P-channel MOS transistor to which an output signal is output, and a gate connected to the high-potential power supply , And one of the drain and the source is connected to the gate of the fifth N-channel MOS transistor.
An OS transistor; and a MOS buffer having an input terminal connected to the source of the fifth N-channel MOS transistor and an output terminal connected to one of the source or the drain of the sixth N-channel MOS transistor. An input circuit, comprising: a pull-up circuit; and a control circuit that generates and outputs the control signal and controls an operation of the input first-stage circuit.