JP2919401B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit for interfacing semiconductor integrated circuit devices of different power supply voltages, and more particularly, to an output terminal connected to a bus line, which is supplied to an output circuit at a preceding stage. Output voltage of the output circuit when the voltage is pulled up to a second high-level power supply (hereinafter, referred to as high power supply HV) having a higher potential than the first high-level power supply (hereinafter, referred to as low power supply LV). The present invention relates to an output circuit improved so as to be able to output at a high potential level pulled up.

[0002]

2. Description of the Related Art In recent years, the voltage of a semiconductor integrated circuit device has been reduced, and the power supply voltage has become 3.0 V or 3.3 V (hereinafter, 3 V).
V system). However, there are still many semiconductor integrated circuit devices with a power supply voltage of 5 V, and even with a semiconductor integrated circuit device with a power supply voltage of 3 V, the interface of the signal with the outside is the signal of the semiconductor integrated circuit device with a power supply voltage of 5 V. Need to be able to handle

An output circuit used in a semiconductor integrated circuit device generally includes a pull-up circuit and a pull-down circuit connected to an output terminal, and a circuit for generating a control signal for controlling these circuits. The pull-up circuit and the pull-down circuit operate according to the signal output from the output circuit, and the switching operation is performed to change the potential of the output terminal.

The above-mentioned conventional output circuit includes a circuit called LVTTL. Referring to FIG. 3, which shows an output section when a bus line to which this output circuit is connected is pulled up to a high power supply HV (5 V) by a pull-up element, this output circuit has only a 3 V system as a supply power supply. It is composed of a circuit using a single power supply. The combination of signals supplied to the two signal input terminals A and B of this circuit is defined as "A", "B", and when the logic level of the signal is high. When it is expressed as “1” and “0” at the low level, the potentials (“0”, “1”), (“1”, “0”),
(“0”, “1”) Three types of combinations of signals are supplied. Here, since the signal of the combination of the potentials (“1”, “1”) is not supplied, the output terminal O
As the potential of the UT, two levels of “1” and “0”;
The output circuit has three values in a “Hiz (hereinafter, referred to as high impedance)” state, and such an output circuit is called a three-state logic circuit.

The source electrode of the P-channel type (hereinafter referred to as P-type) MOS transistor MP2 of the three-state logic circuit is connected to the low power supply LV, and the drain electrode is connected to the output terminal OU.
In T, the gate electrode is the emitter electrode of the bipolar transistor BP1 and the N-channel type (hereinafter referred to as N-type) M
Each is connected to the drain electrode of the OS transistor MN2. The collector electrode of bipolar transistor BP1 is connected to low power supply LV, and the base electrode is connected to the drain electrodes of P-type MOS transistor MP1 and N-type MOS transistor MN1. The source electrode of the P-type MOS transistor MP1 is connected to the low power supply LV,
Source electrodes of S transistors MN1 and MN2 are connected to ground potential GND. P-type MOS transistor MP
1 and the gate electrodes of the N-type MOS transistors MN1 and MN2 are commonly connected to a signal input terminal A from the preceding stage. The drain electrode of the N-type MOS transistor MN3 is the output terminal OUT, the source electrode is the drain electrode of the N-type MOS transistor MN4, and the gate electrode is the low power supply LV.
, The source electrode of the N-type MOS transistor MN4 is connected to GND, and the gate electrode is connected to the signal input terminal B from the previous stage.

The operation of the three-state logic circuit having the above configuration will be described. When the potential of the signal supplied to the signal input terminals (A, B) of this circuit is ("0", "1"), the potential of the signal input terminal A is "0".
The MOS transistors MN1 and MN2 are in a non-conductive “off” state (hereinafter referred to as “OFF”), respectively.
The MOS transistor MP1 is turned on (hereinafter referred to as O
N), a potential difference is generated between the emitter electrode and the base electrode of the bipolar transistor BP1, and this transistor is turned on, so that the signal input terminal D becomes "1" and the P-type MOS Transistor M
P2 is in the “OFF” state.

Further, since the potential of the signal input terminal B is "1", the N-type MOS transistor MN4 is in the "ON" state, and the N-type MOS transistor MN3 is always "O".
Since it is in the “N” state, the output terminal OUT is set to “0”.

On the other hand, when the potentials of the signal input terminals (A, B) of this circuit are ("1", "0"), respectively, the potential of the signal input terminal B is "0". The transistor MN4 is turned off. Further, since the potential of the signal input terminal A is "1", the P-type MOS transistor MP1 is in the "OFF" state, and the N-type MOS transistors MN1 and MN2 are each in the "ON" state. No potential difference occurs between the emitter electrode and the base electrode, and the bipolar transistor BP1 is turned off.

Therefore, the potential of the signal input terminal D is N-type M
Since the OS transistor MN2 is in the “ON” state, it becomes “0”, and the P-type MOS transistor MP2 becomes “O”.
N "state and the output terminal OUT is set to" 1 ", but the output terminal OUT is connected to the high power supply H having a higher potential than the low power supply LV.
Since it is pulled up to V, the current i1 flowing from the high power supply HV to the low power supply LV when the P-type MOS transistor MP2 is in the “ON” state, and the drain electrode and the N-well of the P-type MOS transistor MP2 are formed. Current leak 2 due to the parasitic diode.

On the other hand, when the potentials of the signal input terminals (A, B) of this circuit are ("0", "0"), the potential of the signal input terminal A is "0". The transistors MN1 and MN2 are each in the "OFF" state, and the P-type MOS transistor MP1 is in the "ON" state. Therefore, a potential difference is generated between the emitter electrode and the base electrode of the bipolar transistor BP1, and this is turned "ON".
State, the potential of the signal input terminal D becomes “1”,
The P-type MOS transistor MP2 is turned off.

Since the potential of the signal input terminal B is "0", the N-type MOS transistor MN4 is turned "OFF".
In this state, the output terminal OUT becomes “Hiz”. At this time, since the output terminal OUT is pulled up to the high power supply HV by the Pull Up element as in the case where the potential of the output terminal OUT is outputting “1”, the P-type M
The OS transistor MP2 has a drain electrode level of a high power supply HV (5 V), a gate electrode level of a low power supply LV (3.0 or 3.3 V), and a source electrode (contact D) level of a low power supply LV. , The drain electrode and the source electrode are switched, and the state becomes “ON”. Therefore, when the P-type MOS transistor MP2 is turned “ON”, a current i1 flowing to the low power supply LV and a current leak i2 due to a parasitic diode formed by the drain electrode and the N well occur.

Another conventional example improved from the above-mentioned conventional example is described in Japanese Patent Application Laid-Open No. 7-297701. FIG. 4 shows an output section when an output terminal is connected to a bus line in a state where an output terminal is pulled up to a high power supply HV (5 V) by a pull-up element in the output interface circuit described in the publication. Referring to FIG. 4, this output circuit is a circuit for interfacing between semiconductor integrated circuits to which different power supply voltages are supplied, and is also called a floating N-well circuit. This output circuit is constituted by a circuit using a single power supply of only a 3 V system as a power supply, and signal potentials ("0", "1") are respectively applied to signal input terminals (A, B) of this circuit. , (“1”,
(0)) and (0), the signal of three combinations of (0) and (0) is supplied, and the signal of the combination of (1) and 1 is not supplied. OUT
As two potentials, “1” and “0”;
This is a three-state logic circuit having three values in a “Hiz” state.

In this three-state logic circuit, the source electrode of the P-type MOS transistor MP2 is connected to the low power supply LV, the drain electrode is connected to the output terminal OUT, and the gate electrode is connected to the emitter electrode of the bipolar transistor BP1 and the N-type MOS transistor.
The drain potential of the transistor MN2 is connected to the source electrodes of the P-type MOS transistors MP3 and MP5, and the well potential is set to the P-type MOS transistor MP3.
The well potentials of MP4 and MP5 are connected to the drain electrodes of P-type MOS transistors MP4 and MP5, respectively. The drain electrode of the P-type MOS transistor MP3 is connected to the output terminal OUT and the P-type MOS transistor M
The gate electrode of P4 is connected to the low power supply LV, respectively. The source electrode of the P-type MOS transistor MP4 is connected to the low power supply LV. The collector electrode of bipolar transistor BP1 is connected to low power supply LV, and the base electrode is connected to the drain electrodes of P-type MOS transistor MP1 and N-type MOS transistor MN1.
The source electrode of the P-type MOS transistor MP1 has a low power supply L
V, N-type MOS transistors MN1 and MN1
The source electrode of N2 is connected to GND. The P-type MOS transistors MP1 and MP5 and the gate electrodes of the N-type MOS transistors MN1 and MN2 are commonly connected to a signal input terminal A from the preceding stage. N-type MOS transistor M
The drain electrode of N3 is connected to the output terminal OUT, the source electrode is connected to the drain electrode of the N-type MOS transistor MN4, and the gate electrode is connected to the low power supply LV. N-type MOS
The source electrode of the transistor MN4 is connected to GND,
The gate electrode is connected to the signal input terminal B from the previous stage.

Next, the operation will be described with reference to FIG. 4 and FIG. 5 showing timing waveforms for explaining the operation.
In the timing waveforms shown in this figure, the signal propagation time is set to 0 for easy explanation.

When the signals supplied to the signal input terminals (A, B) of this circuit are at the potentials ("0", "1") during the period from time t0 to t1, respectively, the potential at the signal input terminal A becomes "0". ", The N-type MOS transistor MN1
And MN2 are each in the “OFF” state, and the P-type M
Since the OS transistor MP1 is in the “ON” state, a potential difference occurs between the emitter and base electrodes of the bipolar transistor BP1, and this transistor is in the “ON” state.

Therefore, the potential of the contact D becomes "1", and the P-type MOS transistor MP2 is turned "OFF". Further, since the potential of the signal input terminal B is “1”, the N-type MOS transistor MN4 is in the “ON” state, and the N-type MOS transistor MN3 is always in the “ON” state. The potential becomes “0”.

At this time, in the P-type MOS transistor MP5 in the floating N well indicated by the one-dot chain line, the potential of the contact D is "1" and the signal input terminal A is "0" as described above.
Therefore, the state becomes “ON”. Also, P-type MOS
The potential of the output terminal OUT of the transistor MP4 also becomes "0" because the potential of the output terminal OUT becomes "0". Therefore, the above-mentioned floating N well is connected to the low power supply LV (3.0 V or 3.0 V).
3V), the P-type MOS transistor MP
2, MP3, MP4 and MP5 are other P-type MOSs in the circuit
The operation is similar to that of a transistor.

Next, a transition is made from time t1 to t2 and time t2
In this case, when the signals supplied to the signal input terminals (A, B) of this circuit are the potentials ("1", "0"), respectively, the potential of the signal input terminal A is "1". The MOS transistor MP1 is in the “OFF” state, and the N-type MOS
Since the transistors MN1 and MN2 are each in the “ON” state, no potential difference occurs between the emitter and base electrodes of the bipolar transistor BP1, and the bipolar transistor BP1 is in the “OFF” state.

Therefore, the potential of the contact D becomes "0" because the N-type MOS transistor MN2 is in the "ON" state. The potential "0" turns the P-type MOS transistor MP2 into the "ON" state, thereby causing the signal input. Since the potential at the terminal B is “0”, the N-type MOS transistor M
Since N4 is in the “OFF” state, the potential of the output terminal OUT becomes the potential “1” of the low power supply LV at time t3.

However, since the output terminal OUT is pulled up to the high power supply HV (5 V) by the pull-up element, the potential of the output terminal OUT exceeds the supply low power supply LV of this output circuit at time t3, and at time t4 At high potential HV
Operate to transition to.

At this time, the P-type MOS transistor MP5 in the floating N-well indicated by the one-dot chain line enters the “OFF” state because the potential of the contact D is “0” and the signal input terminal A is “1”. Become. Also, the potential of the output terminal OUT of the P-type MOS transistor MP4 becomes "1", so that it is also in the "OFF" state.

Next, at time t5, when the potential of the signal input terminal A changes to "0", the N-type MOS transistors MN1 and MN2 are each in the "OFF" state, and the P-type MOS transistor MP1 is "ON", as described above. State, a potential difference is generated between the emitter and base electrodes of the bipolar transistor BP1.
N "state.

Therefore, the potential of the node D changes from the potential “0” to the potential “1” of the low power supply LV from time t5 to time t6.
And the P-type MOS transistor MP2 is in the “OFF” state. Further, since the potential of the signal input terminal B is “0”, the N-type MOS transistor MN4 is in the “OFF” state. Therefore, the potential of the output terminal OUT becomes “Hi”.
z "state.

At this time, as described above, at time t4, the output terminal OUT is connected to the high power supply H by the pull-up element.
Since the operation is performed so as to increase the voltage to V (5 V), the potential relationship between the source and drain electrodes of the P-type MOS transistor MP3 is reversed to be in the “ON” state, and the time t6
, The potential of the contact D, which was at the potential “1” of the power supply LV, is raised to the low potential LV or more at time t4, and the output terminal OUT
And the same potential.

When the potential at the contact D becomes "1" at time t6, the P-type MOS transistor MP2 is turned "OFF".
However, the P-type MOS transistor MP3 is turned on and the potential of the contact D is raised to the high power supply HV (5 V), so that the P-type MOS transistor MP5 is turned on and the floating N-well is set. Also has the same potential as the output terminal OUT and the contact D.

[0026]

The above-mentioned conventional output circuit has the following problems. That is, in the conventional output circuit of FIG. 4 which has taken measures against the problem of the conventional output circuit described with reference to FIG. 3, a bus line connecting between semiconductor integrated circuit devices to which two different power supply voltages are supplied, When pulled up to the same high-potential high power supply HV, even if the potential “1” is output from the output circuit at the preceding stage to the output terminal, the high power supply is obtained despite the bus line potential being pulled up. There is a problem that the potential does not rise to the HV potential.

The reason is as follows. That is,
3 and 4 operate with a low power supply LV,
When the potential “1” is being output, the potential “1” of the output terminal OUT is determined by the resistance ratio between the pull-up element and the “ON resistance” of the driver transistor MP2 of the pull-up circuit in the output circuit. Decided. But,
In order to reduce the operating current when the output potential is "0", several kilohms are usually used as the "ON resistance". Now, since the "ON resistance" of the driver transistor MP2 is set to an extremely small value with respect to the resistance value of the pull_up element, the level of the output terminal is set to the low power supply L level.
From V to the high power supply HV.

Therefore, the floating N shown in FIG.
The well circuit does not operate and the output terminal OUT of the output circuit
The driver transistor MP2 that raises the potential of the bus line to “1” always remains in the “ON” state, so that the current flows from the high power supply HV pulling up the bus line to the low power supply LV that is the power supply voltage of the output circuit. A path occurs. Therefore, the potential “1” of the bus line cannot rise to the high power supply HV due to the resistance ratio determined by the pull-up element and the “ON resistance” of the driver transistor MP2.

[0029]

An output circuit according to the present invention comprises a first semiconductor integrated circuit device to which a first high-potential power is supplied and a second semiconductor device to which a second high-potential power higher than the voltage is supplied. An output circuit in which two semiconductor integrated circuit devices are interfaced with each other via a bus line, wherein the bus line is an output circuit connected to a second high-potential power supply by a pull-up connection. When the potential of the output terminal is set to three states of a high level, a low level, and a high impedance in response to a combination of the first and second input control signals, the first control signal is changed to a delayed signal delayed for a predetermined period. A control circuit for responsively controlling conduction and non-conduction of a first switch provided between the gate electrode of the output transistor and the output terminal, wherein the control circuit is configured to control the delayed predetermined period. The first switch means is turned off, the output transistor is turned on, the potential of the output terminal is set to a first high power supply potential, and after the predetermined period has elapsed, the first switch means is turned on. Making the gate electrode of the output transistor and the output terminal conductive so as to raise the potential of the output terminal to the high power supply potential of A2, and cutting off the current flowing from the second high power supply to the first high power supply via the output transistor; It is characterized by.

In any of the three states, the current flowing from the second high-level power supply to the first high-level power supply via the output transistor is cut off to lower the potential of the output terminal to the second high-level power supply. It can be maintained at the power supply potential.

Further, the gate electrode of the output transistor is supplied with the first input signal via an input section and a second switch means, and when the second input signal is at a low level and the first input signal is at a low level. In response to the transition of the input signal from the low level to the high level, the first switch means is non-conductive, and as soon as the second switch means is conductive and goes to the low level, the potential is immediately raised to the first high power supply potential. Further, after the predetermined period has elapsed, the second switch is turned off and the first switch is turned on in response to the delay signal, and the output is output via the switch. It is also possible to make a transition to the second high power supply potential whose terminal is pulled up and to maintain the potential until the next time when the first input signal becomes high level.

Further, when the first and second input signals each transition to a low level and the potential of the output terminal enters the high impedance state, the potential of the gate electrode of the output transistor becomes the first level. The second switch means, which conducts in response to the transition of the input signal from the high level to the low level, is in a state in which the first high power supply potential supplied from the input section is secured, and And the output terminal potential is maintained at the second high potential power supply potential of the output terminal via the first switch means which is already in a conductive state in response to the high level of the state immediately before the input signal. Even if the delay signal later transitions to a low level, the second potential of the output terminal potential
The potential relationship between both ends is reversed by the high potential power supply potential, and the second potential is maintained via the first switch means for maintaining the conduction state.
, And this potential can be maintained until the next high-level transition time of the first input signal.

Further, the first high-potential power supply and the low-potential power supply are supplied, and the input section inverts and outputs the first and second input signals, and the first high-potential power supply and the low-potential power supply. A first P-channel MOS transistor serving as an output transistor, a first N-channel MOS transistor having a gate electrode connected to a first high potential power supply, and a second N-channel MOS transistor having a gate electrode connected to the second input signal input terminal. N
Channel type MOS transistor is connected in series, and the first P-channel type MOS transistor and the first
Is connected to the output terminal, and the gate electrode of the first P-channel MOS transistor is connected to the output terminal of the input section and the source electrode of the second P-channel MOS transistor. The drain electrode of the second P-channel MOS transistor is connected to the output terminal, and the gate electrode of the first P-channel MOS transistor is connected to the source electrode of the third P-channel MOS transistor. The gate electrode of the third P-channel MOS transistor is connected to the first input signal input terminal. The drain electrode and the well of the third P-channel MOS transistor are connected to the first high-potential power supply, and the gate electrode is connected to the source terminal. The fourth P to connect
The drain electrode and the well of the channel type MOS transistor, the well of the second P-channel type MOS transistor and the well of the first P-channel type MOS transistor are commonly connected, and the output terminal is connected to the second high potential. The control circuit is inserted in place of a direct connection between the output terminal of the input unit of the output circuit pulled up to the power supply and the gate electrode of the first P-channel MOS transistor, and the control circuit is A source electrode of a third N-channel MOS transistor is connected to an output terminal of the input unit, and a drain electrode is connected to a gate electrode of the first P-channel MOS transistor; The output terminal of the first AND circuit is connected to the gate electrode of the MOS transistor. The input terminal is connected to the output terminal of the input unit via a polarity inversion element, the other input terminal is connected to the first signal input terminal via a delay element, and the output terminal of the delay element. Is further connected to one input terminal of a second AND circuit, the other input terminal is connected to the output terminal, and the output terminal of the second AND circuit is connected to the second P-channel type. It is connected to the gate electrode of a MOS transistor.

[0034]

Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an output section of an output circuit according to a first embodiment of the present invention. An output terminal is connected to a bus line, and this bus line is connected to a high power supply HV (5 V) by a pull-up element. Shows a state where the pull-up is performed. Referring to FIG. 1, this output circuit is an output circuit for interfacing between semiconductor integrated circuit devices to which different power supply voltages are supplied, and uses a single power supply of only a 3 V system as a power supply. As described above, this circuit is called a floating N-well circuit, and signal potentials ("0", "1"), ("1", "0") are applied to signal input terminals (A, B) of this circuit, respectively. )), (“0”,
“0” ”) are supplied.
Since the signal of the combination (“1”, “1”) is not supplied, the output terminal OUT has two levels of “1” / “0” and the level of the “Hiz” (high impedance) state. It is a three-state logic circuit composed of three values.

This output circuit is a P-type MOS for driver.
The source electrode of the transistor MP2 is the low power supply LV, the drain electrode is the output terminal OUT, and the gate electrode is the drain electrode of the switching N-type MOS transistor MN5, the source electrode of the switching P-type MOS transistor MP3 and the floating N well. P-type M that determines potential
The well potential is connected to the source electrode of the OS transistor MP5, respectively, and the well potential is set to the P-type MOS transistors MP3 and MP3.
4 and MP5 and the drain electrodes of P-type MOS transistors MP4 and MP5, respectively. The drain electrode of the P-type MOS transistor MP3 is connected to the output terminal OUT, the gate electrode of the P-type MOS transistor MP4 and one input terminal of NAND2, and the gate electrode is connected to the output terminal of NAND2. P-type MOS
The source electrode of the transistor MP4 is connected to the low power supply LV. The other input terminal of NAND2 is a delay block D
The output terminal of LY1 is connected to one input terminal of NAND1. The gate electrode of the N-type MOS transistor MN5 is connected to the output terminal of NAND1, and the source electrode is connected to INV.
1 is connected to the input terminal of the first transistor, the emitter electrode of the bipolar transistor BP1, and the drain electrode of the N-type MOS transistor MN2. The output terminal of INV1 is NAND1
Is connected to the other input terminal. The collector of the bipolar transistor BP1 is connected to the power supply LV, and the base electrode is connected to the P-type MO.
S transistor MP1 and N-type MOS transistor M
Commonly connected to each drain electrode of N1. The source electrode of the P-type MOS transistor MP1 is connected to the low power supply LV, and the N-type MOS transistors MN1 and MN2
Are connected to GND, respectively. The gate electrodes of the MOS transistors MP1, MP5, MN1, MN2 and the input terminal of the delay block DLY1 are commonly connected to a signal input terminal A from the previous stage. The drain electrode of the N-type MOS transistor MN3 is connected to the output terminal OUT, the source electrode is connected to the drain electrode of the N-type MOS transistor MN4, the gate electrode is connected to the low power supply LV, and the source electrode of the N-type MOS transistor MN4 is connected to GND. , The gate electrode is connected to the signal input terminal B from the previous stage.

Next, the operation will be described with reference to the timing waveform shown in FIG. Note that this timing waveform
For ease of explanation, the signal propagation time except for the delay block DLY1 is set to 0.

First, in the period between times t0 and t1, when the potentials of the signals supplied to the signal input terminals (A, B) of this output circuit are ("0", "1"), respectively, the signal input terminal A Is "0", the N-type MOS transistors MN1 and MN2 are each in the "OFF" state, and the P-type MOS transistor MP1 is in the "ON" state. Therefore, between the emitter and base electrodes of the bipolar transistor BP1. Since a potential difference is generated and this transistor is turned on, the contact C becomes the potential "1" of the low power supply LV.

At this time, the potential “1” of the contact C is INV1
And the potential of the contact E becomes “0”, and the output of the NAND 1 unambiguously outputs the potential “1”.
The transistor MN5 is turned “ON”, and the contact D becomes the same potential “1” as the contact C. Further, "0" of the signal A is delayed by DLY1 to about the rise time, and
Until the potential "0" is maintained, the contact F
, And the output of NAND2 uniquely outputs the potential "1", so that the P-type MOS transistor MP3 to which this output signal is supplied is in the "OFF" state.

Therefore, the potential of the contact D is a P-type MOS
Since the potential remains at “1” without being affected by the transistor MP3, the P-type MOS transistor MP2 is turned “OFF”.
State. Further, since the potential of the signal input terminal B is “1”, the N-type MOS transistor MN4 is in the “ON” state, and the N-type MOS transistor MN3 is always “O”.
Since the state is “N”, the potential of the output terminal OUT becomes “0”.

At this time, the portion surrounded by the dashed line indicates the floating N-well region, but the P-type MOS transistors MP5 and MP4 in this region are shown.
Are turned on by the signal A and the potential “0” of the output terminal OUT, respectively, and the potential of the N well is changed to the low power supply L.
V (3.0V-3.3V), P-type MOS
The transistors MP2, MP3, MP4, and MP5 operate similarly to other MOS transistors of the same type in the circuit.

Therefore, P-type MOS transistor MP2
No current flows through.

Next, during a period from time t2 to t7,
When the potential of the signal supplied to the signal input terminals (A, B) of this output circuit is ("1", "0"), the potential of the signal input terminal B is "0", so that the N-type MOS transistor MN4 is turned off. Since the signal input terminal A is "1", the P-type MOS transistor MP1 is in the "OFF" state, and the N-type MOS transistors MN1 and MN2 are in the "ON" state.
No potential difference occurs between the emitter and base electrodes of the bipolar transistor BP1, and the bipolar transistor BP1 is turned off. Therefore, the potential of the contact C is N
Since the type MOS transistor MN2 is in the “ON” state, the potential becomes “0” at time t2.

Here, the signal at the contact F is output at time t3 since the signal at the signal input terminal A outputs a potential "1" which is delayed by the delay block DLY1 to about the rise time of this circuit as described above. The contact F remains at "0" until t2, and even if the potential of the signal input terminal A changes from "0" to "1" at time t2, the contact F remains at "0" for about the rise time of this circuit. Will remain. Since the potential "0" causes the NAND1 to uniquely output "1", the N-type MOS transistor MN5 is turned "ON", and the contact D becomes the same potential "0" as the contact C.

Further, the output contact H of the NAND 2 also outputs "1" uniquely in response to the potential "0" of the contact F described above, so that the P-type MOS transistor MP3 is turned "OFF".
State. By these operations, the potential of the contact D is determined, and the MOS transistor MP2 is turned “ON”, so that the potential of the output terminal OUT becomes the low power supply LV at time t2.
To the high power supply HV (5
V).

However, if the delay time about the rise time has passed, the contact F also becomes "1" at time t2, so that the potential "1" of the contact F and the signal potential "1" of the output terminal OUT are supplied. The NAND 2 outputs the potential “0” to the node H in response to the respective input potentials “1”, and sets the MOS transistor MP3 to the “ON” state.

At this time, since the potential of the signal B is "0", the MOS transistor MN4 is in the "OFF" state, and the potential of the contact E, which is the output of INV1, and the potential of the contact F after the delay. Since the potentials are “1”, the NAND 1 outputs the potential “0” and the N-type MOS
Since the transistor MN5 is in the “OFF” state,
The potential of the contact D is equal to "O" of the P-type MOS transistor MP3.
The potential becomes "1" in response to the "N" state, and as a result, the P-type MOS transistor MP2 is turned "OFF".

At this time, since the output terminal OUT is pulled up to the high power supply HV (5 V) by the pull-up element, the potential of the floating N well region indicated by the dashed line portion HV (5
V), the P-type MOS transistor MP3 becomes “O”
N "state, N-type MOS transistor MN
5 is in the “OFF” state, and the P-type MOS transistor M
P4 also has "OF" because the output terminal OUT is "1".
The state becomes F ", and the potential of the contact D further rises from the low power supply LV and becomes the same as the potential of the output terminal OUT and the high power supply HV (5 V) at time t6.

When the potential of the contact D is raised to the high power supply HV (5 V), the MOS transistor MP5 is turned on, and the N-well in the floating region also has the same potential as the output terminal OUT and the contact D.

Therefore, current leakage caused by the parasitic diode formed by the drain electrode of the MOS transistor MP2 and the N well is eliminated, and when the P-type MOS transistor MP2 is in the "ON" state, the power supply LV
Does not flow because the P-type MOS transistor MP2 is in the "OFF" state.

Further, the MOS transistor MN5 is set to "O"
Since the state is FF ", no current i2 flows from the contact D to the MOS transistor MN2.

Therefore, the potential of the bus line connected to the output terminal OUT rises to the high power supply HV pulling up this bus line.

Next, when the potentials of the signals supplied to the signal input terminals (A, B) of this circuit change ("0", "0") from time t7 to t8, respectively, the potential of the signal input terminal A changes. Is "0", the N-type MOS transistors MN1 and MN2 are each in the "OFF" state,
Since the P-type MOS transistor MP1 is in the "ON" state, a potential difference occurs between the emitter and base electrodes of the bipolar transistor BP1, the transistor is in the "ON" state, and the contact C is "1".

The potential "1" at the contact C is inverted at INV1 to become the potential "0" at the contact E.
Since D1 uniquely outputs "1" to the contact H, the N-type M
The OS transistor MN5 is turned “ON”, and the contact C
Becomes the same potential “1” as the contact D.

At this time, even if the potential of the signal input terminal A changes from "1" to "0" as described above, the contact F still maintains "1" for about the rise time of this circuit, and the NAN
The output contact G of D2 is "0" and the P-type MOS transistor M
Since P3 maintains the “ON” state, the contact D also maintains the same potential “1” as the high power supply HV (5 V) of the output terminal OUT.

After the delay time about the rise time has passed, the potential of the contact F becomes "0" at time t9, and the signal of the contact F which has reached the potential "0" unambiguously connects the output contact H of the NAND 1 to the potential. Since the level is set to “1”, the MOS transistor MN5 continuously maintains the “ON” state.

Similarly, the output contact G of the NAND 2 also has the potential "1". However, since the potential of the output terminal OUT is the high power supply HV, the inverted potential relationship of the source / drain electrodes of the transistor MP3 is maintained as it is, so that the potential of the gate electrode, which is the contact G, becomes the potential "1" of the low power supply LV. Continuity is maintained even if
The potential of the contact D maintains the high power supply HV.

By the above operation, the potential of the signal input terminal D is determined, and the MOS transistor MP2 is turned off. Further, since the signal input terminal B is “0”, the N-type MOS transistor MN4 is in the “OFF” state, and the output terminal OUT is “Hiz”.

At this time, the MOS transistor MP5 in the floating N-well indicated by the one-dot chain line is in the "ON" state because the contact D is "1" and the contact A is "0" as described above. The N-well in the floating well region is charged to the low power supply LV (3.0 V to 3.3 V), and the P-type MOS transistors MP2, MP3, MP4
And MP5 operate similarly to the other P-type MOS transistors in the circuit.

By this operation, the "OFF" state of the P-type MOS transistor MP2 is maintained, and the P-type
Since the OS transistor MP5 is in the “ON” state, the N-well in the floating region has the same potential as the output terminal OUT and the contact D.

Therefore, P-type MOS transistor MP
The current leak i2 caused by the parasitic diode formed by the drain electrode of N2 and the N well is eliminated, and the current i1 flowing to the low power supply LV when the P-type MOS transistor MP2 is in the "ON" state is also reduced by the P-type MOS transistor MP2. Does not flow because is set to the "OFF" state.

Therefore, the P-type MOS transistor MP
2 so that current leakage due to a parasitic diode formed by the drain electrode and the N well does not flow.
Since the P-type MOS transistor MN5 is in the “OFF” state, no current i2 flows from the high power supply HV to the MOS transistor MN2.

Further, even if the potential of the bus line to which the output terminal OUT is connected becomes "1" (high power supply HV),
This bus line maintains the potential “1” level by the high power supply HV pulled up.

[0064]

As described above, the output circuit of the present invention is an output circuit in which the bus line is pulled up to the high power supply HV, and the first and second input control circuits supplied to this output circuit. When the potential of the output terminal is set to three states of a high level, a low level, and a high impedance in response to a combination of signals, the gate electrode of the output transistor responds to a delay signal obtained by delaying the first control signal for a predetermined period. And a control circuit for controlling conduction and non-conduction of the first switch means provided between the first and second output terminals.
During the delayed predetermined period, the first switch means is turned off, the output transistor is turned on, the potential of the output terminal is set to the first high power supply potential, and after the predetermined time period, the first switch means is turned off. Since the gate electrode and the output terminal of the output transistor are brought into the conductive state to raise the potential of the output terminal to the high power supply potential and cut off the current flowing from the high power supply to the low power supply via the output transistor, the first effect is that two different power supplies are used. When connecting a semiconductor integrated circuit of a high voltage to a bus line pulled up to a high power supply, if the output circuit operating at a low power supply outputs a "1" level, the level of the bus line is raised to a high power supply voltage. That you can do it. The second effect is that the power consumption of the output circuit can be reduced. The reason is that the resistance value of the pull-up element can be increased because the resistance value of the pull-up element does not influence the level at the time of output of “1”. This is because the current can be small.

For example, "ON" of an N-type MOS transistor
Assuming that the “resistance” is 200Ω and the “ON resistance” of the P-type MOS transistor is 400Ω, in the conventional output circuit, in order to increase the output level to “5V-5%”, the pull-up resistance must be 35Ω. "0"
At the time of output, "ON resistance" of two-stage N-type MOS transistor
Although a steady current of 11 A flows from the resistance value of the pull-up resistor, in the present invention, since the pull-up resistance can be increased, this can be greatly reduced. For example, if the pull-up resistance is 50 KΩ, the steady-state current at the time of “0” output is 0.1 mA. When "1" is output, the input signal is delayed by about the rise time, and the pull-up transistor provided at the gate electrode of the driver MOS transistor of this output circuit is turned "OFF" to thereby provide a bus line. The current i flowing to the low power supply when the driver MOS transistor is in the “ON” state is also the current path flowing from the high power supply pulling up to the power supply of the output circuit.
2 does not flow because it is in the "OFF" state.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional output circuit.

FIG. 4 is a circuit diagram of another example of a conventional output circuit.

FIG. 5 is a timing chart of a conventional output circuit 2.

[Explanation of symbols]

 A to H contacts HV high power supply LV low power supply MP1 to MP5 P-type MOS transistor MN1 to MN5 N-type MOS transistor BP1 bipolar transistor DLY1 delay block NAND1, NAND2 AND circuit INV1 inverter (polarity inversion element) Pull Up pull up element

Claims (5)

(57) [Claims] 1. A bus line is provided between a first semiconductor integrated circuit device to which a first high potential power supply is supplied and a second semiconductor integrated circuit device to which a second high potential power supply higher than the voltage is supplied. An output circuit interfaced through the output circuit, wherein the bus line is an output circuit connected to a second high-potential power supply by a pull-up connection, and a combination of the first and second input control signals supplied to the output circuit. When the potential of the output terminal is set to three states of a high level, a low level, and a high impedance in response, the gate electrode of the output transistor and the output terminal respond to the delay signal obtained by delaying the first control signal for a predetermined period. A control circuit for controlling conduction and non-conduction of the first switch provided between the terminals, wherein the control circuit disconnects the first switch during the delayed predetermined period; State, the output transistor is turned on, the potential of the output terminal is set to the first high power supply potential, and after the predetermined period has elapsed, the first switch means is turned on, and the gate electrode of the output transistor is turned on. An output circuit for raising a potential of the output terminal to a second higher power supply potential and interrupting a current flowing from the second higher power supply to the first higher power supply via the output transistor. 2. In any one of the three states,
2. The output circuit according to claim 1, wherein a potential of said output terminal is maintained at a second high power supply potential by interrupting a current flowing from said second high power supply to said first high power supply via said output transistor. 3. A gate electrode of the output transistor,
The first input signal is supplied through an input section and a second switch means, and is responsive to the second input signal being at a low level and the first input signal transitioning from a low level to a high level. As soon as the first switch means is non-conductive and the second switch means is conductive and goes to a low level, the potential is immediately raised to the first higher power supply potential. The second switch means is turned off in response to a signal and the first switch means is turned off.
Is turned on, the output terminal is transited to the second high power supply potential which is pulled up via this switch means, and the potential is changed until the next time when the first input signal becomes high level. 2. The output circuit according to claim 1, wherein the output circuit is maintained. 4. When the first and second input signals each transition to a low level and the potential of the output terminal enters the high impedance state, the potential of the gate electrode of the output transistor becomes the first input signal. A state in which the first high power supply potential supplied from the input section is secured by the second switch means that is turned on in response to a signal transitioning from a high level to a low level; and In response to the high level of the state immediately before the input signal, the output terminal potential is maintained at the second high potential power supply potential of the output terminal potential through the first switch means already in the conductive state, and further after the predetermined period has elapsed. Even if the delay signal transitions to a low level, the first switch that maintains the conductive state by reversing the potential relationship between both ends by the second high potential power supply potential of the output terminal potential. 2. An output circuit according to claim 1, wherein the output circuit is maintained at a second high potential power supply potential via a switch means, and this potential is maintained until the next high-level transition time of the first input signal. 5. The power supply according to claim 1, wherein the first high-potential power supply and the low-potential power supply are supplied, and the input unit inverts and outputs the first and second input signals, and the first high-potential power supply and the low-potential power supply. First P-channel type MO serving as output transistor
An S transistor and a first N-channel MOS transistor having a gate electrode connected to a first high-potential power supply;
Is connected in series with a second N-channel MOS transistor having a gate electrode connected to the input signal input terminal of
P-channel MOS transistor and the first N
A serial connection point of the channel type MOS transistor is connected to the output terminal, and a gate electrode of the first P channel type MOS transistor is connected to an output terminal of the input unit and a source electrode of the second P channel type MOS transistor. The drain electrode of the second P-channel MOS transistor is connected to the output terminal, and the gate electrode of the first P-channel MOS transistor is also connected to the source electrode of a third P-channel MOS transistor. A gate electrode of the third P-channel MOS transistor is connected to the first input signal input terminal, a drain electrode and a well of the third P-channel MOS transistor are connected to a source electrode for a first high potential power supply, and a gate electrode is connected to the output terminal. And a drain electrode of a fourth P-channel MOS transistor for connecting And the well of the second P-channel MOS transistor and the well of the first P-channel MOS transistor are commonly connected, and the output terminal is pulled up to a second high potential power supply. The control circuit is inserted in place of a direct connection between the output terminal of the input unit and the gate electrode of the first P-channel MOS transistor, and the control circuit unit includes a third terminal connected to the output terminal of the input unit. The source electrode of the N-channel MOS transistor is connected, the drain electrode is connected to the gate electrode of the first P-channel MOS transistor, and the gate electrode of the third N-channel MOS transistor is connected to the first N-channel MOS transistor. The output of the AND circuit is connected,
One input terminal of the first AND circuit is connected to an output terminal of the input unit via a polarity inversion element, and the other input terminal is connected to the first signal input terminal via a delay element. And the output terminal of the delay element is further connected to one input terminal of a second AND circuit, and the other input terminal is connected to the output terminal. 2. The output circuit according to claim 1, wherein an output terminal is connected to a gate electrode of said second P-channel MOS transistor.