JP2846338B2 - Schmitt trigger circuit - Google Patents

Description

The present invention relates to a Schmitt trigger circuit in a semiconductor integrated circuit, and more particularly, to a Bi-CMOS (bi-CMOS) in which a MOS transistor and a bipolar transistor are mixed on the same semiconductor substrate. The present invention relates to a Schmitt trigger circuit in a semiconductor integrated circuit.

(Prior Art) In recent years, for the purpose of compensating for the respective drawbacks of a MOS transistor and a bipolar transistor, a technique relating to a Bi-CMOS semiconductor integrated circuit formed by mixing a MOS transistor and a bipolar transistor on the same semiconductor substrate. Is developing.

Conventionally, as a technique in such a field, Japanese Patent Laid-Open No.
There was one described in 1216 gazette and the like. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing one configuration example of a conventional Schmitt trigger circuit.

This Schmitt trigger circuit has an input terminal 1 for an input potential Vi. The input terminal 1 is connected to a base of an NPN transistor 2 and to a first input terminal 3a of a two-input NAND gate 3. ing. NPN transistor 2
Is connected to power supply potential VCC, and the emitter is connected to ground potential VSS via node 4 and resistor 5. Further, the power supply potential VCC and the second input of the 2-input NAND gate 3
P-channel MOS transistor (hereinafter, referred to as PMOS) 6 is connected between the input terminal 3b and the input terminal 3b, and its gate is commonly connected to the output side of the 2-input NAND gate 3 and the output terminal 7 for the output potential Vo. .

 Next, the operation will be described.

First, when an “L” level input potential Vi is applied to the input terminal 1, both terminals 3 a and 3 b of the two-input NAND gate 3 become “L”.
Level, the output goes to “H” level and the PMOS
6 is an off state. Here, the input potential Vi starts to rise and N
When the forward voltage VF of the PN transistor 2 is reached, the transistor 2 is turned on. However, since the potential of the node 44 has not yet reached the threshold potential VTH of the NAND gate 3, "L"
Level, and its output remains at “H” level.

Further, the input potential Vi rises and the threshold potential VT
When the voltage exceeds H, the potential of the first input terminal 3a of the NAND gate 3 becomes "H" level.

However, the potential of the second input terminal 3b is
Of the NAND gate 3 is still at the "H" level because the voltage drops by the forward voltage VF of "1".

When the input potential Vi rises to (VTH + VF), N
The potential of the second input terminal 3b of the AND gate 3 becomes "H" level, and the output of the NAND gate 3 becomes "L" level. Accordingly, the PMOS 6 is turned on, the second input terminal 3b is fixed at the power supply potential VCC, and at the same time, the potential of the input terminal 1 also increases.

Conversely, the input potential Vi decreases and the threshold potential VTH
When the voltage falls below the threshold, the first input terminal 3b of the NAND gate 3 goes low, and the output of the NAND gate 3 is inverted to the high level. As a result, the PMOS 6 is turned off, so that the input potential Vi also decreases.

Thus, the circuit of FIG. 2 operates with a hysteresis characteristic.

(Problems to be solved by the invention) However, the Schmitt trigger circuit having the above configuration has the following problems.

The voltage obtained by dividing the power supply potential VCC and the ground potential VSS by the on-resistance of the PMOS 6 and the resistor 5 needs to be equal to or higher than the threshold potential VTH of the NAND gate 3.
Will be set higher.

On the other hand, after the input potential Vi changes from “H” level to “L” level, the potential of the node 4 depends on the time constant t (= R × C) between the resistor 5 and the drain connection capacitance C of the PMOS 6. descend. The time constant t increases because the resistance value R of the resistor 5 is high. Therefore, when the input potential Vi changes from “L” level to “H” level before the potential of the node 4 does not sufficiently decrease,
The actual switching delay time (the time from when the waveform enters the input terminal 1 to when it leaves the output terminal 7) becomes faster than the value determined at the time of circuit design depending on the frequency used, and there is a concern that circuit design may be hindered. .

Further, while the PMOS 6 is turned on, a direct current flows through the resistor 5 to increase power consumption.

An object of the present invention is to provide a Schmitt trigger circuit which solves the problems of the prior art in terms of circuit design difficulty and high power consumption.

(Means for Solving the Problems) According to the present invention, in order to solve the above-mentioned problems, the first power supply potential is connected between a node and an on-state by an input potential.
A bipolar transistor that turns off, a gate circuit that takes a logic of the input potential and the potential of the node, is connected between the first power supply potential and the node, and is turned on and off by an output of the gate. In a Schmitt trigger circuit including a first MOS transistor, the Schmitt trigger circuit is connected between the node and a second power supply potential, and is complementary to the first MOS transistor based on an output of the gate circuit. A second MOS transistor that performs on / off operation is provided.

(Operation) According to the present invention, since the Schmitt trigger circuit is configured as described above, the bipolar transistor works so as to input an input potential, and the gate circuit takes logic of the potential of the node based on the input potential.

The first MOS transistor works to fix the potential of the node to the first or second power supply potential. Furthermore, the second
MOS transistors together with the first MOS transistor constitute a CMOS inverter, and by the output of the gate circuit, they operate on / off complementarily to cut off between the first or second power supply potential. There is. Therefore,
The above problem can be solved.

FIG. 1 is a circuit diagram of a Schmitt trigger circuit according to a first embodiment of the present invention.

This Schmitt trigger circuit has an input terminal 10 for an input potential Vi, and the input terminal 10 has an NPN transistor 20
And the first input terminal 30a of the two-input NAND gate 30 is connected. NPN transistor
The collector of 20 is connected to the power supply potential (first power supply potential) VCC, and the emitter is connected via a node 40 to the second potential of the NAND gate 30.
Is connected to the input terminal 30b. Furthermore, the power supply potential VCC
A CMOS inverter 50 is connected between the second power supply potential and the ground potential VSS.

This CMOS inverter 50 has a PMOS 51 and an NMOS 52,
The source of the PMOS 51 is connected to the power supply potential VCC, and the PMOS 51
Through the output node 53 of the inverter 50
Connected to the drain of NMOS52 and the transistor
It is connected to 20 emitter-side nodes 40. And NMOS
52 sources are connected to the ground potential VSS. Also, PMO
The gates of the S51 and the NMOS 52 are respectively connected via an input node 54, and the node 54 is commonly connected to the output side of the NAND gate 30 and the output terminal 70, respectively.

FIG. 3 is a waveform diagram of the input / output potentials Vo and Vi of FIG.
The operation of FIG. 1 will be described with reference to FIG.

First, when an "L" level input potential Vi is applied to the input terminal 10, the output of the NAND gate 30 becomes "H" level because the first terminal 30a of the NAND gate 30 is at "L" level. The potential of the node 54 also becomes “H” level. Therefore, the PMOS 51 is turned off, the NMOS 52 is turned on, and the output node 53 of the inverter 50 is set at the “L” level potential. At this time, the power supply potential VC
No current flows between C and the ground potential VSS.

Here, a case where the input potential Vi increases will be described.

Operation at Point A in FIG. 4 The input potential Vi increases and the forward voltage Vf of the transistor 20 increases.
Then, the transistor 20 is turned on, and the emitter current flows into the node 53. However, since the current has not yet sufficiently flown, the second input terminal 30 of the NAND gate 30
b remains at the “L” level. On the other hand, the first input terminal 30a of the NAND gate 30 has risen to the potential Vf, but has not reached the threshold potential Vth of the NAND gate 30, and thus is at the “L” level. Therefore, the output of the NAND gate 30 remains at “H” level.

Operation at point B in FIG. 4 Furthermore, the input potential Vi rises and the threshold potential Vt
When the voltage exceeds h, the potential of the first input terminal 30a of the NAND gate 30 becomes "H" level. On the other hand, the potential rises because the emitter current of the transistor 20 flows into the node 53, which is the output of the inverter 50. However, the potential of the second input terminal 30b is equal to the forward voltage Vf of the transistor 20 from the input terminal 10.
As a result, the voltage of the NAND gate 30 remains at the “H” level because the voltage is lowered by the amount corresponding to the “L” level.

Operation at Point C in FIG. 4 When the input potential Vi rises above (Vth + Vf), the potential of the second input terminal 30b of the NAND gate 30 goes to "H" level.
Therefore, the output of the NAND gate 30 becomes “L” level,
The output potential Vo of the output terminal 60 is also at the “L” level.

Operation at the point D in FIG. 4 As a result, the PMOS 51 turns on and the NMOS 52 turns off.
The output of inverter 50 rises to "H" level. Therefore, the second input terminal 30b is fixed to the power supply potential VCC, so that the transistor 20 is turned off, and the power supply potential VCC and the ground potential V
No current flows between SS.

Next, a case where the input potential Vi decreases will be described.

Operation at Point E in FIG. 4 When the input potential Vi becomes (Vth + Vf), the input potential Vi
When rising, the output of the NAND gate 30 changes from “H” level to “L” level.
Flipped to a level. However, when the input potential Vi drops,
The first input terminal 30a of the NAND gate 30 is higher than the threshold potential Vth and at “H” level, and the second input terminal 3a
0b is also at the “H” level because the node 53 is at the “H” level, and the output of the NAND gate 30 remains at the “L” level.

Operation at the point F in FIG. 4 Further, when the input potential Vi falls below the threshold level potential Vth of the NAND gate 30, the first input terminal 3b of the NAND gate 30 becomes "L" level. , NAND gate 30
Is inverted to “H” level. As a result, the PMOS 51 is turned off and the PMOS 52 is turned on, so that the potential of the output node 53 of the inverter 50 becomes “L” level, and the second input terminal 3b of the NAND gate 30 becomes “L” level. At this time, the emitter potential of the transistor 20 is
It decreases in a short time due to the potential “L” level of 53.

Thus, the Schmitt trigger circuit shown in FIG. 1 operates with a hysteresis characteristic as shown in FIG.

 The present embodiment has the following advantages.

Since complementary on / off operations are performed using the PMOS 51 and the PMOS 52, no DC current flows between the power supply potential VCC and the ground potential VSS, and power consumption can be reduced.

Since the circuit components are all active devices, instead of using driven elements such as resistors as conventional circuit components, the potential of each node 40, 53, 54 is determined at high speed, and the switching delay time is frequency dependent. Can be reduced. This eliminates the need to finely simulate the switching delay time for each frequency at the circuit design stage, and facilitates circuit design.

FIG. 3 is a circuit diagram of a Schmitt trigger circuit showing a second embodiment of the present invention.

This Schmitt trigger circuit is configured such that the NPN transistor 20 in FIG.
Is replaced by a two-input OR gate 31. Elements common to those in FIG. 1 are denoted by the same reference numerals.

This Schmitt trigger circuit has an input terminal 10 for an input potential Vi. The input terminal 10 is connected to the base of a PNP transistor 21 and the first terminal of a two-input OR gate 31.
Is connected to the input terminal 30a. The collector of the PNP transistor 31 is connected to the ground potential VCC, which is the second power supply potential, and the emitter is connected via the node 40 to the second input terminal 31b of the OR gate 31. Further, a CMOS inverter 50 is connected between the power supply potential VCC and the ground potential VSS. The input side of the inverter 50 is commonly connected to the input side of the OR gate 31 and the output terminal 60, and the output side
21 emitters are connected.

In this Schmitt trigger circuit, the same operation as in FIG.
Has an effect.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, in the second embodiment, the input side node 40 of the gate circuit 31 is fixed at “H” level, but “L”
It may be fixed to the level. In that case, PMOS51 becomes NMOS,
It is necessary to replace NMOS 52 with PMOS.

(Effects of the Invention) As described in detail above, according to the present invention, by turning on and off complementarily using PMOS and NMOS,
Since the first and second power supply potentials are cut off, no DC current flows between the first and second power supply potentials, and power consumption can be reduced.

Further, since each circuit component is configured using an active element, the potential of each node is determined at high speed, and the switching delay time can be kept constant in a wide frequency range. Thereby, an effect of facilitating circuit design can be expected.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a Schmitt trigger circuit showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional Schmitt trigger circuit, FIG. 3 is a waveform diagram of input / output potentials in FIG. FIG. 4 is a circuit diagram of a Schmitt trigger circuit according to a second embodiment of the present invention. 10 input terminal, 20 NPN transistor, 30 two-input NAND gate, 30a, 30b first and second input terminals, 40, 5
3,54 …… node, 50 …… CMOS inverter, 51 …… PMOS,
52 ... NMOS, 60 ... Output terminal, VVi ... Input potential, Vo ...
... output potential, VCC, VSS ... first and second power supply potentials.

Claims (1)

(57) [Claims] A bipolar transistor that is connected between a first power supply potential and a node and that is turned on and off by an input potential; a gate circuit that takes a theory of the input potential and the potential of the node; A first MOS transistor that is connected between the power supply potential of the first node and the node and that is turned on and off by an output of the gate; And a second MOS transistor that is turned on and off in a complementary manner to the first MOS transistor based on an output of the gate circuit.