JPH02306713A - Schmitt trigger circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by using PMOS and NMOS so as to turn on/off them in a complementary way and interrupting a 1st and a 2nd power supply level. CONSTITUTION:A CMOS inverter 50 connecting between a power level VCC and a ground level VSS is provided with a P-channel MOS 51 and a Bchannel MOS 52, a source of the PMOS 51 connects to the power unit potential VCC and the drain connects to a drain of the NMOS 52 via an output node of the inverter 50 and an emitter of a transistor(TR) 20. Then a source of the NMOS 62 connects to the ground potential VSS, gates of the PMOS 51 and the NMOS 52 are connected together via an input node 54 respectively and the node 54 connects in common to the output of a NAND gate 30. Then the PMOS 51 and the NMOS 52 in use are turned on and off complementarily. Thus, the power consumption is reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a Schmitt trigger circuit in a semiconductor integrated circuit, and particularly to a B i -CM in which a MOS transistor and a bipolar transistor are mixed on the same semiconductor substrate.
The present invention relates to a Schmitt trigger circuit in an O8 (Pi Simos) semiconductor integrated circuit.

(Prior Art) In recent years, technology related to Bi-CMO8 semiconductor integrated circuits in which MOS transistors and bipolar transistors are mixedly formed on the same semiconductor substrate has been developed in order to compensate for the respective drawbacks of MOS transistors and bipolar transistors. is developing.

Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 62-1
There were some that were described in 71216, etc. below,
Its configuration will be explained using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional Schmitt trigger circuit.

This Schmitt trigger circuit has an input terminal 1 for the input potential Vi, and the input terminal 1 is connected to an NPN transistor 2.
, and the first input terminal 3a of the two-man power NAND gate 3 is connected thereto. The collector of the NPN transistor 2 is connected to the power supply potential VCC, and the emitter is connected to the ground potential VSS via a node 4 and a resistor 5.
It is connected to the. Furthermore, the power supply potential ■CC and the two-man power N
A P-channel MOS transistor (hereinafter referred to as PMO8) 6 is connected between the second input terminal 3b of the AND gate 3, and its gate is connected to the output 1 of the two-power NAND gate 3 and the output for the output potential ■0. Commonly connected to terminal 7.

Next, the operation will be explained.

First, when an input potential ■i of "Lll level" is applied to the input terminal 1, both terminals 3a, 3 of the two-manufactured NAND gate 3
b are both at “L” level, so their outputs are lI HI
It becomes the I level, and the PMO 86 is in the off state. Here, when the input potential Vi begins to rise and reaches the forward voltage VF of the NPN transistor 2, the transistor 2 turns on, but
Since the potential of the node 4 has not yet reached the threshold potential VTR of the NAND gate 3, it is at the "L" level, and its output remains at the "H11" level.

Furthermore, the input potential Vi rises to the threshold potential V
When TH is exceeded, the first input terminal 3 of the NAND gate 3
The potential of a becomes "H'" level.

However, the potential of the second input terminal 3b is
Since the voltage is dropped by the forward voltage VF of , it is at the "Lll level", so the output of the NAND gate 3 still remains at the "HIT level".

Then, when the input potential Vi rises to (VTH+VF), the potential of the second input terminal 3b of the NAND gate 3 becomes I
Therefore, the output of the NAND gate 3 becomes the "L++" level. Accordingly, the PMO 86 is turned on, the second input terminal 3b is fixed at the power supply potential VCC, and at the same time, the potential of the input terminal 1 is also increased.

Conversely, the input potential Vi decreases and the threshold potential VT
When the voltage drops below R, the first input terminal 3b of the NAND gate 3 becomes "L" level, so the output of the NAND gate 3 is inverted to "H" level. As a result, the PMO 86 is turned off, so that the input potential Vi also descends.

In this manner, the circuit shown in FIG. 2 operates with hysteresis characteristics.

(Problem to be solved by the invention) However, in the Schmitt trigger circuit with the above configuration,
The following issues were encountered.

The voltage obtained by dividing the power supply potential VCC and the ground potential VSS by the on-resistance of the PMO 86 and the resistor 5 needs to be higher than the threshold voltage VTH of the NAND gate 3, so the resistance value R of the resistor 5 should be set high. become.

On the other hand, the input potential Vi changes from the HIT level to "°L".

After changing to the level, the potential of node 4 is equal to that of resistor 5 and PM
Which time constant t (=RXC) is the drain junction capacitance C of O86?
decreases depending on The time constant t becomes large because the resistance value R of the resistor 5 is high, and therefore the input potential Vi rises from the "L" level to the "H" level before the potential of the node 4 falls sufficiently.
° When the level changes, the actual switching delay time (
The time required for a waveform to enter the input terminal 1 and exit from the output terminal 7) may be faster than the value determined at the time of circuit design depending on the frequency used, which may cause problems in circuit design.

Furthermore, while the PMO 86 is on, a direct current flows through the resistor 5, resulting in an increase in power consumption.

The present invention provides a Schmitt trigger circuit that solves the problems of the prior art, such as difficulty in circuit design and high power consumption.

(Means for Solving the Problem) In order to solve the problem, the present invention provides a bipolar transistor connected between a first power supply potential and a node and turned on and off depending on the input potential; and a gate circuit that takes logic between the voltage and the potential of the node, and a first MO3 type transistor connected between the first power supply potential and the node and turned on and off by the output of the gate. In the trigger circuit, a second MO8 type transistor is connected between the node and a second power supply potential and turns on and off in a complementary manner to the first MO8 type transistor based on the output of the gate circuit. It is equipped with a transistor.

(Function) According to the present invention, since the Schmitt trigger circuit is configured as described above, the bipolar transistor works to input the input potential, and the gate circuit takes the logic of the potential of the node based on the input potential.

The first MO8 type transistor works to fix the potential of the node to the first or second power supply potential.

Further, the second MO8 type transistor is connected to the first MO3 type transistor.
configuring a CMOS inverter with type transistors,
The outputs of the gate circuits turn them on and off in a complementary manner.
It has the function of turning off and cutting off the first or second power supply potential. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a Schmitt trigger circuit shown in a first embodiment of the present invention.

This Schmitt trigger circuit has an input terminal 10 for the input potential Vi, and the base of the NPN transistor 20 is connected to the input terminal 1o.
A first input terminal 30a of the D gate 3o is connected. The collector of the NPN transistor 20 is at the power supply potential (first
(power supply potential) VCC, and the emitter is connected to node 40
The second input terminal 30b of the NAND gate 30 is connected to the second input terminal 30b of the NAND gate 30 via. Furthermore, a CMOS inverter 50 is connected between the power supply potential Vcc and the ground potential VSS, which is a second power supply potential.

This CMOS inverter 50 has PMO851 and NMO
852, the source of the PMO 851 is connected to the power supply potential VCC, the drain of the PMO 351 is connected to the drain of the NMO 852 via the output node 53 of the inverter 50, and the emitter side node 40 of the transistor 20. It is connected to the. And N.M.O.
The source of 852 is connected to the ground potential SS. Further, the PMO 851 and N1MO 852 (7) gates are connected via an input side node 54, and the node 54 is connected to the output side of the NAND gate 30 and the output terminal 70.
are commonly connected to each other.

FIG. 3 is a waveform diagram of the input/output potentials Vo and Vi in FIG. 1, and the operation in FIG. 1 will be explained with reference to this diagram.

First, when an input potential Vi of "L'° level is applied to the input terminal 10, the first terminal 30a of the NAND gate 30
is at II L 11 level, so its output is “H’
° level, and the potential of the node 54 also becomes H" level. Therefore, the PMO 351 is in the off state, and the NMO 852 is in the off state.
is turned on, and the output of the inverter 50 is 1-rule node 5.
3 becomes the potential of IIL" level. At this time, the power supply potential V
No current flows between CC and ground potential VSS.

Here, a case where the input potential Vi increases will be explained.

When the second Ω operating input potential Vi rises to the forward voltage Vf of the transistor 20, the transistor 2o turns on and emitter current flows into the node 53.

However, since the current has not yet reached a sufficient level, N
The second input terminal 30b of the AND gate 3o is llt,"
remains at the level. On the other hand, the first
The input terminal 30a of has risen to the potential Vf, but the NA
Since the threshold potential vth of the ND gate 30 has not been reached, it is at the it L ++ level. Therefore, NA
The output of the ND gate 30 remains at the "°H" level.

In addition, the input potential Vi rises to the threshold potential V
When the voltage exceeds th, the potential at the first input terminal 30a of the NAND gate 30 becomes u H++ level. On the other hand, the transistor 20 is connected to the node 53 which is the output of the inverter 50.
Since the emitter current flows in, the potential rises. However, the potential of the second input terminal 30b remains at the "l L l" level because it is lowered by the forward voltage Vf of the transistor 20 than the input terminal 10, and as a result, N
The output of the AND gate 30 still maintains the H'' level state.

When the Ω operation input potential Vi rises above (Vth+Vf) at the ΩΩ point in the U-th ward, the NA
The potential of the second input terminal 3ob of the ND gate 30 becomes the "H" level. Therefore, the output of the NAND gate 30 becomes the "Lll" level, and the output potential Vo of the output terminal 60 also becomes the "L" level.

Due to this, the PMO 851 is turned on and the NMO 352 is turned off, so that the output of the inverter 50 rises to the ゛°H power level. Therefore, the second input terminal 30b is fixed to the power supply potential VCC, so the transistor 20 is turned off,
No current flows between the power supply potential ■CC and the ground potential VSS.

Next, a case where the input potential Vi decreases will be explained.

When the Ω operation input potential Vi becomes (Vth+Vf) at the Ω end point, the output of the NAND gate 30 becomes “H+” when the input potential Vi rises.
It was reversed from + level to 11 L 11 level.

However, when the input potential Vi falls, the NAND gate 3
0 first input terminal 30a is at the threshold potential vth
is higher than “°H” level, and the second input terminal 3
0b is also “H′° because node 53 is at “H++ level”
Therefore, the output of the NAND gate 30 remains at the "L" level.

Furthermore, when the input potential Vi of the fourth F-counter falls and becomes lower than the threshold level potential vth of the NAND gate 30, the NAND
Since the first input terminal 3b of the gate 30 goes to the "L" level, the output of the NAND gate 30 is inverted to the "H'" level. This turns off PMO851 and NMO8
52 is turned on, the output side node 5 of the inverter 50
3 becomes the "L" level, and the second input terminal 3b of the NAND gate 30 becomes the "L" level. At this time, the emitter potential of the transistor 20 decreases in a short time due to the potential "Lll level" of the output side node 53 of the inverter 50.

In this way, the Schmitt trigger circuit shown in FIG.
It operates with hysteresis characteristics as shown in the figure.

This embodiment has the following advantages.

(2) Since the PMO 851 and the NMO 852 are used to turn on and off in a complementary manner, no direct current flows between the power supply potential VCC and the ground potential VSS, thereby reducing power consumption.

■ Instead of using passive elements such as resistors in the circuit elements as in the past, all circuit elements are made into active elements.
The potential of each node 40, 53, 54 is determined quickly, and the frequency dependence of the switching delay time can be reduced. This eliminates the need for detailed simulation of the switching delay time for each frequency at the circuit design stage, making circuit design easier.・
FIG. 3 is a circuit diagram of a Schmitt trigger circuit showing a second embodiment of the present invention.

This Schmitt trigger circuit replaces the NPN transistor 20 in FIG.
It has a configuration in which the D gate 30 is replaced with a two-man operated OR gate 31, and elements common to those in FIG. 1 are given the same reference numerals.

This Schmitt trigger circuit has an input terminal 10 for the input potential Vi, and the input terminal 10 is connected to the base of the PNP transistor 21 and to the first input terminal 31a of the two-man OR gate 31. ing. P.N.
The collector of the P)- transistor 31 is connected to the ground potential ■cC which is a second power supply potential, and the emitter is connected to the second input terminal 31b of the OR gate 31 via a node 40. Furthermore, a CMOS inverter 50 is connected between power supply potential VCC and ground potential VSS. The output side of the OR gate 31 and the output terminal 60 are commonly connected to the input side of the inverter 50, and the emitter of the transistor 21 is connected to the output side.

This Schmitt trigger circuit has the same functions and effects as those shown in FIG.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, in the second embodiment, the input side node 40 of the gate circuit 31 is fixed at the "H" level.
It may be fixed at "L" level. In that case, PMO35
It is necessary to replace 1 with NMO8 and NMO352 with PMO3.

(Effects of the Invention) As explained in detail above, according to the present invention, PMO8
and NMO3 are used to turn them on and off in a complementary manner to cut off the first and second power supply potentials, so no direct current flows between the first and second power supply potentials. Power consumption can be reduced.

Furthermore, since each circuit component is configured using an active element, the potential of each node can be determined quickly, and the switching delay time can be made constant over a wide frequency range. This can be expected to have the effect of facilitating circuit design.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a Schmitt trigger circuit showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional Schmitt trigger circuit, and FIG. 3 is a waveform diagram of input and output potentials shown in FIG. FIG. 4 is a circuit diagram of a Schmitt trigger circuit showing a second embodiment of the present invention. 10...Input terminal, 20...NPN transistor, 30...2 manual NAND gate,
30a, 30b... 1st. second input terminal, 4
0.53.54... Node, 50...
CMOS inverter, 51...PMO3, 52
・・・・・・NMOS, 60・Tune・Output terminal, vi・
...Input potential, Vo...Output potential, vc
c, vss... 1st. Second power supply potential.

Claims (1)

[Scope of Claims] A bipolar transistor connected between a first power supply potential and a node and turned on and off depending on the input potential; a gate circuit that takes a logic between the input potential and the potential of the node; a first MOS connected between a first power supply potential and the node and turned on and off by the output of the gate;
A Schmitt trigger circuit comprising a MOS type transistor connected between the node and a second power supply potential, and configured to turn on and off complementary to the first MOS type transistor based on the output of the gate circuit. Second MOS to operate
A Schmitt trigger circuit characterized by having a type transistor.