JPS6080316A - Voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To attain the circuit integration of an element whose oscillated frequency is changed in one IC chip by inserting an MOS transistor (TR) in series with a path to make a pulse delay time variable in an inverter section. CONSTITUTION:A ring oscillator is constituted by connecting CMOS inverters 1, 2, 3 in series, a P-channel MOSFET14 and an N-channel MOSFET15 are inserted to a path between the inverters 2 and 3 and a control voltage is applied to each gate terminal G of the FETs 14, 15. The control voltage is changed to change the time constant and delay time of the parallel circuit comprising the N-channel MOSFET13 or the P-channel MOSFET12 and the FETs 14, 15 thereby controlling the oscillated frequency. Thus, it is possible to integrate all the oscillators on one chip IC thereby decreasing number of components.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a voltage-controlled token vibrator whose oscillation frequency can be controlled by flow pressure, and particularly to a voltage-controlled token vibrator suitable for IC implementation.

[Background of the invention]

An example of a conventional voltage controlled oscillator is shown in FIG. Figure 1 shows an example using a known ring oscillation circuit in which an odd number of inverters are connected in series and the output of the final stage inverter is fed back to the input of the first stage.
, 2.5Y is used. Inno Kuichita 1, 2.
Input voltage waveforms 4, 5, and 6'r of each stage of 5 are shown with the same numbers in FIG. The basic operation of the oscillator shown in FIG. 1 will be explained below. Now, suppose that the input signal 4 or the logic level IQ level reaches 11 levels and increases. When the input signal 4 exceeds the threshold voltage shown by the broken line in FIG. 2 at time α, the polarity of the output level of the inverter 1 is reversed.

The input 5 of the inverter 2 at the next stage decreases from time α from 11 lvl to 10 lvl along a curve determined by the time constant of the output resistance of the b1 inverter 1 and the capacitor 7.

Note that in FIG. 2, the transient portion of the input waveform is shown using an approximate straight line. Furthermore, if a well-known complementary metal oxide semiconductor (CMOS) is used for the inverter, the threshold voltage will generally be a value near the midpoint voltage between the '1' level and 10 lb.

As described above, when the voltage of the input signal 5 decreases and passes the threshold at time 6, the polarity of the output level of the inverter 2 is reversed. A capacitor 8 and a variable capacitance diode 9 are connected to the input end of the inverter 6. The variable capacitance diode 9 has a characteristic that its capacitance value changes depending on the reverse DC voltage applied thereto.

The capacitor 8 is for the current power cant, and generally has a sufficiently larger capacitance value than the value of the variable capacitance diode 9. Therefore, if a DC voltage is applied to the terminal 10 in the configuration shown in FIG. 1, a variable capacitor will be attached to the input terminal of the inverter 30.

Here, when the polarity of the output of the inverter 2 is reversed as described above, the input signal 6 is transferred to the inverter 2 from the time point 6.
The curve of the time constant determined by the output resistance of the variable capacitance diode 9 and the capacitance value of the variable capacitance diode 9 is drawn. When the input signal 6 exceeds the threshold at time C, the polarity of the output of the inverter B is reversed, and the input signal 4g of the inverter 1 becomes inno (
- A curve determined by the output resistance of 3 and the capacitor 11. After time C, the input level fluctuation transient part in the opposite direction to the above explanation is changed to d in the same way as the above explanation.
, e, and f, and returns to the same pulse phase state as at time α at time a'. After time α′, the above α
The operation from to time α' is repeated, and the circuit shown in FIG. 1 oscillates. If the time difference between each time point explained above is tl~t6 as shown in Fig. 2, one oscillation period T is T""t
+ + t2 +ts + t4 + ta + ta
becomes.

If the capacitance value of the variable capacitance diode 9 is changed by changing the DC voltage applied to the terminal 10, the times t2 and t described above change, and therefore the oscillation period T changes. That is, the oscillation Al wave number can be controlled by the DC voltage applied to the terminal 10. Generally, a floating capacitor parasitic to the inverter input section is often used as the capacitor 7.11.

By the way, the conventional method described in 1 above, σ)' Making a tortoise-controlled oscillator into an integrated circuit (IC),' is to form the capacitor 8 or the variable capacitance diode 9 of the large capacity capacitor 8 on the same IC chip as the inverters 1 to 3. It is extremely difficult to do so, and therefore it is necessary to add it as a separate part from the IC.
This resulted in an increase in the number of Ota power terminals and an increase in the number of parts.

[Purpose of the invention]

The object of the present invention is to provide an element that changes the oscillation frequency with the same
The object of the present invention is to provide a voltage-controlled keepsake that can be integrated into a C-chip.

[Summary of the invention]

The key point of the invention is that an odd number of CMOS inverters are connected in series to form a ring@oscillator circuit, and at least one of the inverters forming this inverter is connected to the next-stage inverter input via this inverter. Insert a new KMOS transistor in series in the path that supplies voltage to the terminal.

The structure is such that the pulse delay time in the inverter sK can be varied by regulating the four-way resistance by a direct current screw pressure applied to the gate terminal of the inserted MOS transistor.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In the following figures, those having the same a-ability as in Fig. 1 are given the same -bud+j'J:r: as in Fig. 1.

FIG. 3 shows an example in which the present invention is applied to a ring oscillation circuit using inverters 1 to 6 similar to those shown in FIG. In FIG. 6, the inverter 2 is shown as a MOS transistor circuit.
As is well known in the MO5 technology, the inverter is constructed by connecting a P-channel MOS transistor (PMos) 12 and an N-channel 7-channel MOS transistor CNMO3) 1s as shown. Gate terminals G of the PMO 512 and NMO 515 are connected in common and serve as input terminals of the inverter. One terminal of NA10515 is connected to the first power supply voltage Vs.
s' (ground in Figure 6) K connected, pMO512
One terminal of the NMOS 13, PM is connected to a second power supply voltage (VDJ) having a higher voltage value than the first power supply voltage.
Another terminal of the OS12 terminals is connected in common and serves as the output terminal of the inverter.

In the embodiment shown in FIG. 3, the output of the inverter 2 and the input of the inverter 30 are connected to
15) k insert L till. As is well known in the 0M05 circuit, one of the PMO 312 and NMO 515 of the inverter 2 becomes conductive (low resistance) and the other becomes open (high resistance) depending on the voltage level of the input 5. When pMO512 is in conduction state (5MO515 & @ open state), Vnn Kara P
A current flows through the parallel circuit of the MOS 12, the pMO 514, and the NMO 515 to the capacitor 16 attached to the input terminal of the inverter 2, and the capacitor 16 is photoelectrically charged. Also, NMO513 is in a conductive state (pMO512 is in an open state)
When , PMO514 and NMO51 from capacitor 16
5 parallel circuits, cVss (3rd
Current flows through the ground (ground in the figure).

Capacitor 16 is discharged. As is well known, the conduction resistance of the NOS transistors 14 and 15 depends on the DC voltage value applied to the gate terminal G thereof.

In PMO514, when the gate voltage is -f, the NMO
515 has a characteristic that the lower the gate voltage, the higher its conduction resistance value? have Therefore, PMOS14, NM
By using each gate terminal G of the OS 15 as a control @j voltage input terminal and appropriately changing the period of the DC voltage applied thereto, the time t2+'5 in Fig. 2 can be controlled. It is possible to control the oscillation frequency with the same ftp as in the conventional example.

By the way, in the embodiment of FIG. 3, 'C' is the capacitor 1.
6 is a stray capacitance parasitic to the input terminal of the inverter, similar to the capacitors 7 and 11, or a CMOS IC.
Since a small-capacity capacitor that can be easily produced on a chip can be used, all of the voltage-controlled optical oscillators shown in FIG. 3 can be integrated on the same IC chip.

FIG. 4 shows another embodiment according to the present invention.

In the figure, PMO 512 and NMO 515 operate equivalent to inverter 2 in the N2 diagram. Here pMO5121
)E When in the conductive state, from Vj)n, PMO512,
A current flows through the PMO 514 and the capacitor 16 .

In addition, RVCtt with NMO51s in a conductive state, Contin + 16 Color NM OS 15, NMO51
Current flows through 3 towards ground.

fa S Figure Ij5'J VcP, M OS 14
, NMOS 15. By applying a control voltage to each of the tD gate terminals G, a voltage-controlled older camera device can be realized with the configuration shown in FIG. It is also clear from the explanation of FIG. 3 that the voltage-controlled optical oscillator shown in FIG.
All can be integrated on top.

FIG. 5 shows yet another embodiment of the present invention. Fifth
The embodiment shown in the figure is an example in which a 7-channel MOS transistor is inserted in one of the charging path and the discharging path of the capacitor 16, and the 7-star MOS transistor is controlled to control the single-circuit resistance. Insert it again. FIG. 6 shows pulse waveforms for each part of FIG. 5.

In the embodiment shown in FIG. 5, only the number of hours in which the input voltage of the inverter 3 @ No. 6 changes from "1 level" to "0 level" by the DC' voltage applied to the gate terminal G of 1'1M0515. Since this changes, frequency control is realized by varying only i'ij4 (1) at the time indicated by t in FIG.

In the embodiments shown in FIG. 6 and FIG.
Are two systems for MO515 necessary?

In the embodiment shown in FIG. 5, "C" can perform frequency control with one control '1 pressure for the IVMO 515.

In general, the CMOS inverters 1, 2, and 3 shown in Figures 13, 4, and 5 have the following characteristics: the input voltage at the point where the input pulse changes from the "0" level to the 11" level, the delay time between the output pulses, and the delay time between the output pulses. , is designed so that the above-mentioned delay time at the part where the input pulse changes from 11 level color IO level VC is almost the same.In other words, inverter 1 has H'Ht4s, and inverter 3 has almost the same time as t8 and t6. Therefore, the implementation f of Figure 3 and Figure 4
1, the voltages applied to the gate terminals G of the p-MO 514 and the NM OS 15 are set to t and t in the second phase.

If they are set so that they are the same, the time of each half cycle of the oscillation pulse obtained from the oscillator can be kept almost the same even if the frequency is changed. That is, it is possible to control the frequency while maintaining the following relationship.

However, in the embodiment of FIG. 5, only t in FIG. 6 changes and the frequency changes, so the time of the excavation pulse waveform of one oscillator changes every half cycle.

Therefore, FIG. 7 shows an embodiment in which one frequency control can be controlled by pressure and the time of each half cycle of the oscillation pulse can be kept the same.

In FIG. 7, PM
PMOS 12' and NMO51 have the same configuration as the circuit configured with OS12, NMOS 13, and 15.
3' and 15' circuits are used. In this embodiment, the discharge time constant of the capacitor 7 is also controlled in the same way as the discharge time constant of the capacitor 16 is controlled. FIG. 8 shows pulse waveforms at various parts in FIG. 7. In Figure 7 p: IO512', NM
pros 12 at O513' and 15', respectively.
Using MOS transistors having the same electrical characteristics as the NMOs 513 and 15, and designing the capacitors 7 and 16 to have the same capacitance can be achieved with the current CMO5 technology. In this way, t2 and t4 in FIG. 8 become approximately 4-. Even if the gate terminals G of the NMO 515 and 15' are connected in common and used as the control voltage input terminal 10, and the oscillation frequency is changed by changing the DC voltage applied thereto, tl and t in Fig. 8 will remain approximately the same. Since they are the same, the relationship in equation (2) above is maintained.

Therefore, if the oscillator output is taken from the output of the inverter 3, an oscillation output cabal of approximately one foot (that is, a pulse duty of approximately 50%) can be obtained regardless of the oscillation frequency or the time of each half cycle.

However, in FIG. 7, if the slope of the fall of input pulse 5 from time point α in FIG. 8 and the slope of fall of input pulse 4 from time C in FIG. 8 become significantly different as the frequency is controlled, It is conceivable that t2 and t may also be different, but the MOS transistors 12' and 15' in FIG.
, 13' and the primary stage M O
S) By inserting an even number of inverters similar to inverter 3 in series between the input terminals to which the gate terminals of transistors 12 and 13 are commonly connected, it is possible to prevent t2 from being different from t4.

In addition, in the examples shown in Part 3, Figure 4, and Figure 5,
An example was shown in which the conduction resistance of a path from one inverter to the next inverter in a ring oscillation circuit in which an odd number of inverters are connected in series is controlled. It can be easily understood from the above description that a voltage-controlled optical oscillator with the above-mentioned conduction resistance control function can also be realized.

In the embodiments shown in FIGS. 5 and 7, only NHO2 is used as the conduction resistance control element, or NHO
4, 5, and 7 show that it is possible to realize a voltage-controlled optical oscillator using only PMO5 instead of PMO2 and changing only the time constant of the charging path of the capacitor. It is clear from the description.

Furthermore, in a voltage-controlled optical oscillator in which the conduction resistance of only one of the charging path and the discharging path of the capacitor is controlled, the conduction resistance is controlled as shown in the embodiment shown in FIG.
Inverter with added functions: If an even number of 2 or more is used, the oscillation frequency can be controlled with one DC voltage as explained in Figure 7, and the oscillation frequency can be controlled as the oscillator output regardless of the number of oscillation frequencies. A voltage-controlled optical oscillator in which a pulse having a testity of approximately 50% is preferable can be easily constructed. The case where two inverters with the above-mentioned conduction resistance control function are used has been described with reference to FIG. 7, but it will be explained below that the same effect can be obtained even if an even number of inverters greater than two are used.

FIG. 9 shows a case where a ring oscillation circuit is constructed using an arbitrary odd number of three or more inverters, and a conduction resistance control element is added between two of the inverters.

In the following figures of the 4-way resistance controlled inverter, the logic d pin is indicated by an arrow.

As shown in Fig. 9, since the total number of inverters is an odd number, one of the two inverters with arrows has an even number including oy between the input and output, and the other has an odd number of ordinary (arrows). ) Connected with an inverter: ratio. As is clear from the explanation of the embodiment shown in Fig. 7, is it possible to connect directly to any part between the output and input of the arrowed inverter connected by an odd number of normal inverters or to the normal inverter? An oscillator output with a pulse duty of 50% can be taken out through the oscillator.

Next, we will discuss the case in which two more conduction resistance control inverters are added to FIG. Any two of the normal inverters in FIG. 9 are marked with arrows.

If this is transferred, it becomes either Figure 10 (α) or ill. In the following figures, normal inverter parts are shown with broken lines without logical symbols, and only the number of inverters is an even number or an odd number, including 00.
Or it was indicated by "odd".

Figure 10 (from al, [bl, inverter 4 with arrow
When using an inverter with an arrow, the input/output of the inverter is an odd number.
This is a path that is connected by an inverter, and when the loop of the ring oscillation circuit is cut on this path, the input and output are connected by an even number of inverters (including those with arrows), and a set of two inverters with arrows is connected. 4. The circuit is configured. It can be seen that there is always a route such that Figure 10 1al, tb
This is the route indicated by "odd" marked with a circle in l.

If the oscillator output is extracted from any part between the input and output of the arrowed inverters in the above path as described above, the 2
Since the two inverter delay times are distributed for each half cycle of one oscillator output, it is possible to obtain an output with a pulse duty of 50%. Further, in FIG. 10 1al, the same rc oscillator output can be obtained from the "even" portions marked with circles.

Hereinafter, it will be explained that the above effect can be obtained using any even number of inverters with arrows of 2 or more.

FIG. 11 shows a ring oscillation circuit using an arbitrary odd number of inverters of three or more. Since the total number of inverters is an odd number, if arrowed inverters are used as an even number of inverters, there will always be a portion where the input and output of the arrowed inverters are connected by an even number of normal inverters. This part is shown in Figure 11 with an underlined ``even''.

The other input/output of the arrowed inverters A and H connected by "even", that is, the output of B and the input of 4 are connected by an odd number of inverters.

Next, consider adding two arrowed inverters C and D'l'7, which are normally connected to vcA and B only by inverters. If the output of C and the input of D are connected by an even number of inverters, then if the oscillator output is taken between the output of D and the input of C, then A
, B, C, and D are distributed in equal numbers every half cycle. When adding inverters with arrows two at a time in this way, the part connected by several inverters per corner (including those with arrows) between the input and output of the newly added inverter with arrows is Once all the inverters with arrows are included, the pulse duty is 50% from the part connected with several regular inverters between the input and output of the inverter with arrows that was added last.
The oscillator output is obtained.

〔Effect of the invention〕

According to the present invention, since the voltage-controlled bone oscillator can be configured with only a MOS transistor or a MOS transistor and a small capacitor, the oscillator can be constructed using only one chip of I/O.
This makes it possible to integrate the circuit on a chip, which is effective in reducing the number of circuit components.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional voltage-controlled bone vibrator. The second factor is the waveform diagram of each part in Fig. 1, the claws 5, 4, and 5゜7 are respectively the configuration diagrams of the embodiment of the present invention, and the f and 6゜8 are the center MMf of Fig. 5.7, respectively. Waveform diagram of each part of l, No. ? ,
Figures 10 and 11 are simplified configuration diagrams for detailed explanation of the X invention. 12, 12', 14, 14'...P channel MOS transistor 13, 13', 15, 15'...N channel MOS transistor Fig. 1 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] t P-channel MOS transistor and N-channel M
The gate terminals of the OS transistors are commonly connected to serve as input terminals, one terminal of the P-channel MOS transistor is connected to the first power supply and the other terminal is used as the output terminal, and one terminal of the N-channel MOS transistor is connected to the second power supply. In a device comprising an odd number of logic gates connected in series in a ring shape, each of which is connected to a power supply and whose other terminal is an output terminal, in at least one of the odd number of logic gates,
A first conductive path connects the first power source and the input terminal of the logic gate at the next stage via the P-channel transistor, and connects the second power source to the logic gate at the next stage via the N-channel transistor. An MO whose conduction resistance is changed by the voltage applied to the gate terminal of one or both of the four conductive paths and the second conductive path to which the input terminal of the gate is connected.
Two terminals of the S transistor are inserted in series, and the output terminals of the P channel MOS transistor and the N channel MOS transistor of the other logic gate are connected in common and connected to the input terminal of the logic gate of the next stage. A voltage controlled oscillation device characterized in that it is configured to apply a control voltage to the gate terminal of a MOS transistor inserted in series with the conductive path. 2. Voltage control according to claim 1 d. In the type oscillator, an even number of two or more logic gates in which MOS transistors are inserted in series only in the first conductive path are used, and the gate terminals of the MOS transistors inserted in series are connected in common, and a control tube is provided. 6. A voltage controlled oscillator device configured to apply voltage. 6. In the voltage controlled oscillator device according to claim 1, a MOS transistor is connected in series only to the second conductive path. Using several logic gates in 1 of 2 or more,
A voltage controlled oscillator device characterized in that the gate terminals of the MOS transistors inserted in series are connected in common to apply a control voltage.