JPH05268002A - Voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To attain the oscillation over a wide frequency range by providing a MOS transistor(TR) connecting in series with a 2nd power supply of a complementary inverter circuit and whose gate receives an oscillation control signal. CONSTITUTION:Inverter circuits 1-4 connected in series in a ring form and a NAND circuit 5 form a ring oscillator. The circuit 5 is a circuit using an oscillation circuit signal CR to control the oscillation and its stop, and when the signal CR reaches logical '1' and the oscillation is started, the circuit 5 acts like an inverter circuit. An output OUT of the voltage controlled oscillator is outputted via an inverter 16 connecting to a node K5. An oscillating frequency of the ring oscillator depends on a delay time per stage of the circuits 1-4, 5 and the delay time of each inverter circuit varies with a voltage of an oscillation control signal IN. Thus, the oscillation over a wide frequency range is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator,
In particular, it relates to a voltage controlled oscillator in a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional voltage controlled oscillator includes inverters I1 to I4 which are complementary MOS inverters connected in series in a ring shape to form a loop.
NAND circuit A1 connected to the input side of the inverter I1
And an output inverter I6 and nodes J1 to J which are connection points of the NAND circuit A1 and the inverters I1 to I4.
N-channel MOS transistors N1 to N5 each having a drain connected to 5 and a gate connected to the input IN
And capacitors C1 to connect between the sources of the N-channel MOS transistors N1 to N5 and the ground.
It was configured with C5 and.

Next, the operation of the conventional voltage controlled oscillator will be described.

The NAND circuit A1 is a circuit for controlling oscillation and stop by the oscillation start signal CR, and operates as an inverter when the oscillation start signal CR becomes "1" and oscillation starts. Output OUT of this voltage controlled oscillator
Is output via the inverter I6 connected to the node J3.

Here, according to the voltage of the input IN, the node J1
~ The load situation at J5 changes. That is, input I
When the voltage of N is the ground potential VS, N-channel MOS
Since the transistors N1 to N5 are in the cut-off state, and the capacitors C1 to C5 are isolated from the respective nodes J1 to J5, the load is minimized. vice versa,
When the voltage of the input IN is the power supply potential VC, the N-channel MOS transistors N1 to N5 are in the conductive state in which the ON resistance RO is the minimum, and therefore the capacitors C1 to C5 are the minimum ON resistance ROM at the respective nodes J1 to J5. Since it is grounded, the load is maximum. When the voltage of the input IN is an intermediate potential between the power supply potential VC and the ground potential VS, the ON resistance RO has an intermediate value between the maximum value and the minimum value, and thus an intermediate load. The oscillation frequency is determined by the delay time of each stage of the inverters I1 to I5 and the NAND circuit A1. The delay time of each inverter depends on the capacitance of the capacitors C1 to C5 and the ON resistance RO. That is, if the capacitance of the capacitor is constant,
The lower the ON resistance RO, the longer the delay time. As a result, the oscillation frequency is the lowest frequency determined by the capacitance of the capacitor when the voltage of the input IN is the power supply potential VC.

[0006]

In the above-mentioned conventional voltage-controlled oscillator, even if the maximum load that determines the delay time of the inverter is only the capacitance of the capacitor, the limit of the minimum oscillation frequency depending on this delay time is considered. However, there is a drawback that it is difficult to expand the oscillation frequency range.

[0007]

A voltage-controlled oscillator according to the present invention is a voltage-controlled oscillator which comprises an odd number of inverter circuits connected in series in a ring shape and whose frequency is controlled by the voltage of an oscillation control signal. The first and second MOS transistors of the first and second conductivity types, which are respectively connected in series with the first and second power supplies, are commonly connected to each other to serve as input terminals. The drains of the two MOS transistors are commonly connected as an output terminal, the drains are connected to the sources of the second MOS transistors, the sources are connected to the second power supply, and the gates are connected to the oscillation control signal. It is configured to include a third transistor of the second conductivity type.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the voltage controlled oscillator of the present invention.

As shown in FIG. 1, the voltage controlled oscillator of this embodiment includes inverter circuits 1 to 4 connected in series in a ring shape to form a loop, and a NAND circuit connected to the input side of the inverter circuit 1. 5 and inverter I6 for output
And is configured.

The inverter circuits 1 to 4 have the same circuit configuration. Taking the inverter circuit 1 as an example, the ground side of a complementary MOS inverter composed of a P channel MOS transistor P11 and an N channel MOS transistor N11 connected in series. N-channel MOS transistor N1
Oscillation control signal IN at the gate between the source of 1 and ground
Is connected to the N-channel MOS transistor N12. Similarly, the NAND circuit 5 includes a P-channel MOS transistor P51 and an N-channel MOS transistor.
An N-channel MOS transistor N52 whose gate is connected to the oscillation control signal IN is connected between the ground and the source of the ground-side N-channel MOS transistor N51 of the complementary MOS inverter including the transistor N51.
Furthermore, the P channel MO to which the oscillation start signal CR is input
It has an S transistor P52 and an N channel MOS transistor N53.

Next, the operation of this embodiment will be described.

The inverter circuits 1 to 4 and the NAND circuit 5 connected in series in a ring form a ring oscillator. First, the NAND circuit 5 is a circuit for controlling oscillation and stop by the oscillation start signal CR, as in the above-mentioned conventional example, and operates as an inverter circuit when the oscillation start signal CR becomes '1' and oscillation starts. .. The output OUT of the voltage controlled oscillator is output via the inverter I6 connected to the node K5.

As described in the above-mentioned conventional example, the oscillation frequency of the ring oscillator depends on the inverter circuits 1 to 4 and NA.
It is determined by the delay time per stage of the ND circuit 5. The delay time of each inverter circuit changes depending on the voltage of the oscillation control signal IN.

FIG. 2 is an operational characteristic diagram showing an example of changes in the delay time of the oscillation control signal IN of the inverter circuit 1 with respect to the voltage VIN. In FIG. 2, it is assumed that the potential of the node K1 changes as shown by the solid line A. First, when the voltage VIN of the oscillation control signal IN is high and is, for example, 5 V, the on-resistance of the N-channel MOS transistor N12 decreases, so that the output of the inverter circuit 1 falls sharply and the potential at the node K2 is as shown by the dotted line B. Change. That is, the delay time TH becomes smaller. Next, when the voltage VIN of the oscillation control signal IN is low, for example, 2V, the N channel M
Since the on-resistance of the OS transistor N12 becomes high, the fall of the output of the inverter circuit 1 becomes gentle, and the potential of the node K2 changes as shown by the one-dotted line C. That is, the delay time TL becomes large.

Therefore, the voltage VI of the oscillation control signal IN
When N is high, the oscillation frequency is high, and when the voltage VIN of the oscillation control signal IN is low, the oscillation frequency is low. FIG. 3 shows, as an example, inverter circuits 1 to 4 and NA.
Set the MOS transistor of the ND circuit 5 as follows,
FIG. 6 is a diagram showing changes in the waveform of the output OUT when the voltage of the oscillation control signal IN is 0.8V for (A) and 5.0V for (B). Here, the gate length of the P-channel MOS transistors P11, P21, P31, P41, P51 is 1.0 μm, the gate width is 8.0 μm, and the N-channel MOS transistors N11, N12, N21, N2.
2, N31, N32, N41, N42, N51, N5
2, N53 gate length 1.0 μm, gate width 4.0
μm, and the power supply voltage VD is 5V. In FIG. 3A, the period is about 20 nS, that is, the frequency is 50 MHz.
In (B), the period is about 3 nS, that is, the frequency is about 300.
It becomes MHz. That is, the frequency range in which oscillation is possible is expanded to about 6 times the lowest frequency.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, it is of course possible to insert an N-channel depletion MOS transistor between the power supply and the P-channel MOS transistor to increase the duty ratio without departing from the gist of the present invention.

[0018]

As described above, the voltage controlled oscillator of the present invention has a wide range by including the MOS transistor connected in series to the second power source side of the complementary inverter circuit and inputting the oscillation control signal to the gate. There is an effect that oscillation in the frequency range is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a voltage controlled oscillator according to the present invention.

FIG. 2 is a waveform diagram showing an example of the operation of the inverter circuit in the voltage controlled oscillator of the present embodiment.

FIG. 3 is a waveform diagram showing an example of the operation of the voltage controlled oscillator according to the present embodiment.

FIG. 4 is a block diagram showing an example of a conventional voltage controlled oscillator.

[Explanation of symbols]

1 to 4 Inverter circuit 5, A1 AND circuit I1 to I4, I6 Inverter N1 to N5, N11, N12, N21, N22, N3
1, N32, N41, N42, N51, N52, N53
N-channel MOS transistors P11, P21, P31, P41, P51, P52
P-channel MOS transistors C1 to C5 capacitors

Claims (1)

[Claims] 1. A voltage-controlled oscillator having an odd number of inverter circuits connected in series in a ring shape, the frequency of which is controlled by the voltage of an oscillation control signal, wherein the inverter circuit is connected in series between a first power supply and a second power supply. The gates of the first and second MOS transistors of the first and second conductivity types respectively connected are commonly connected to serve as input terminals, and the drains of the first and second MOS transistors are commonly connected. An output terminal, a drain is connected to a source of the second MOS transistor, a source is connected to the second power supply, and a gate is connected to the oscillation control signal. A voltage-controlled oscillator characterized in that