JPH04152711A - Voltage controlled oscillator circuit - Google Patents

Abstract

PURPOSE:To attain stable oscillation by connecting the odd number of inverting circuits in series, connecting the output terminal of the inverting circuit of a final stage to the input terminal of a 1st inverting circuit and connecting the control terminals of the inverting circuits to a frequency control signal terminal. CONSTITUTION:Let the input signal of an inverting circuit 1 be 0V at a time T, the output of the inverting circuit 1 is inverted while charging a timing capacitor 4 and reaches a power supply voltage VDD. Moreover, the output of the inverting circuit 1 is delivered to inverting circuits 2, 3 and the level of the input terminal of the inverting circuit 1 goes to the VDD. Then the level of an output terminal of the inverting circuit 1 goes to 0V while discharging the timing capacitor 4 rapidly and when a signal is transported to the input terminal of the inverting circuit 1 again at a time T3, the level of the output terminal is again 0V, and the circuit acts like the oscillating circuit. Moreover, the logic threshold level of the inverting circuits 1, 2, 3 is adjusted by a voltage applied to a frequency control terminal 6 by a current flowing out of a P- channel MOS TR 13. Thus, the logic threshold level is not fluctuated by a current from the current source.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a voltage controlled oscillation circuit used in a phase-locked loop or the like, and particularly to a voltage controlled oscillation circuit suitable for semiconductor integrated circuits.

2. Description of the Related Art As a conventional oscillation circuit, a ring oscillator in which an odd number of inverters are connected as shown in FIG. 3(a) is known. In this conventional circuit, the inverting circuit 31 is the third (a
) As shown in the figure, a voltage control current source 36 is provided between the P-channel transistor 34, the N-channel transistor 35, and the power supply terminal, and the timing capacitor 37 and the input terminal of the inverter 32 are connected to the output terminal of the inverting circuit 31. , the input terminal of an inverter 33 is connected to the output terminal of the inverter 32, the input terminal of the inverter 31 is connected to the output terminal of the inverter 33, and a signal is extracted from the output terminal of the inverter 33.

Furthermore, the operating principle of the conventional circuit shown in Fig. 3(a) is as follows.
If the input signal of the inverting circuit 31 is OV at time T1 as shown in the signal waveform section shown in FIG.
The output terminal of 1 increases while charging the timing capacitor 37. When the output of the 0 inversion circuit 31 exceeds the logic threshold, the output of the inverter 32 is inverted and becomes Ov, and the output terminal of the inverter 33
The output becomes VDD when the power supply voltage is VDD. Here, when the output of the inverter 33 exceeds the logic threshold, the output of the inverting circuit 31 is inverted and the timing capacitor 37 is rapidly discharged. When the output of the inverter 31 exceeds the logic threshold, the output of the inverter 32 is inverted and becomes VDD, and the inverter 3
The output of 3 becomes 0■. Here, when the output of the inverter 33 exceeds the logic threshold, the output of the inverting circuit 31 is inverted again.
It begins to rise while charging the timing capacitor 37.

In this way, the circuit shown in the conventional example operates as an oscillation circuit. At this time, if the time for discharging the timing capacitor 37 and the delay time of the inverters 32 and 33 are sufficiently long, the oscillation frequency is determined by the time for charging the timing capacitor 37. Since the charging time is inversely proportional to the product of the current value flowing from the constant current source and the capacitance value of the timing capacitor 37, the current value changes depending on the voltage applied to the frequency control terminal, and the oscillation frequency can be changed.

Problems to be Solved by the Invention In the conventional voltage control circuit described above, the logical threshold value VINVI of the inverting circuit 31 is equal to the current value of the current source I. , the threshold value of the N-channel MOS transistor is V? N,) transistor gain coefficient is β9, N channel MOS transistor 2
Let the gate width be IIIN and the channel length LN, then V
DINVI = ((LN/WN)X (IO/β
N))”2+VTN ・=(1), and the logical threshold V
TINV, is I. Although there is a dependence on the inverter 32.
33, the current I because the logic threshold is independent. As VTINVI increases, the deviation of the logical threshold value VTINVI increases. Furthermore, as the current 10 increases, the frequency increases and the amplitude decreases, so there is a drawback that oscillation no longer occurs.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel voltage-controlled oscillation circuit which eliminates the above-mentioned drawbacks inherent in the conventional technology and enables stable oscillation operation.

Means for Solving the Problems In order to achieve the above object, the voltage controlled oscillation circuit according to the present invention connects the drain terminal of the first MOS transistor to the second MOS transistor.
The drain terminal of the first MOS transistor is connected to serve as an output terminal, the gate terminal of the first MOS transistor is connected to the gate terminal of the second MOS transistor as an input terminal, and the gate terminal of the first MOS transistor is connected as an input terminal. a source terminal is connected to a drain terminal of a third MOS transistor, a gate terminal of the third MOS transistor is used as a control input terminal, a source terminal of the third MOS transistor is connected to a first power supply, An odd number of inverting circuits formed by connecting the source terminal of the second MOS transistor to a second power supply are connected in series, and the output terminal of the final stage inverting circuit is connected to the input terminal of the first inverting circuit. connection,
The control terminals of these inversion circuits are connected to a frequency control signal terminal.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIGS. 1(a) and 1(b) are circuit block configuration diagrams showing a first embodiment of the present invention.

Referring to FIGS. 1(a) and (b), FIG. 1(a)
is a circuit configuration diagram of the inverting circuit 1, and the inverting circuit 1 includes P-channel MO5) transistors 11, 13, . N channel) 4
0S) consists of a transistor 12, P channel M
The drain terminal of the O5 transistor 11 is an N-channel MO
S) Connected to the drain of the transistor 12 and becomes the output of the inverting circuit 1, its gate terminal is connected to the gate terminal of the N-channel MOS transistor 12 and becomes the input terminal of the inverting circuit 1, and its source terminal is connected to the drain of the P-channel MOS transistor 13. connected to the terminal. P channel M
The gate terminal of the OS transistor 13 becomes a control terminal,
A source terminal is connected to a power supply, and a source terminal of N-channel MOS transistor 12 is grounded.

In FIG. 1(b), the inverting circuit 2.3 has the same configuration as the inverting circuit 1, and the first terminal of the timing capacitor 4 whose second terminal is grounded to the output terminal 102 of the 0 inverting circuit 1 and the inverting circuit The output terminal 102 of the inverting circuit 2 is connected to the input terminal 101 of the inverting circuit 3, and the output terminal 102 of the inverting circuit 3 is connected to the input terminal 1 of the inverting circuit 1.
01 and an output terminal 5, and the output signal is taken out from the output terminal 5, and the control terminal 103 of the inverting circuit 1.2.3 is connected to the frequency control terminal 6.

Next, the principle of operation of the first embodiment of the present invention will be explained. The basic operating principle is the same as that of the ring oscillator shown in the conventional example. As shown in the signal waveform diagram shown in FIG. 1(C), if the input signal of the inverting circuit 1 is OV at time T1, the logic threshold of the inverting circuit 1 is normally set to V
If it is DD, it will be set to VDD/2, so inverting circuit 1
The output of is inverted while charging the timing capacitor 4 and becomes VD.
It becomes D. Further, the output of the inverting circuit 1 is transmitted to the inverting circuit 2.3, and at time T2, the input terminal of the inverting circuit 1 reaches VDD.
becomes. Then, the output terminal of the inverting circuit 1 becomes 0■ without rapidly discharging the timing capacitor 4, and when it propagates to the inverting circuit 2.3 and is again propagated to the input terminal of the inverting circuit 1 at time T3, it becomes 0■ again. Assuming that the delay time of the zero inversion circuit 2.3 operating as an oscillation circuit is sufficiently smaller than the time for charging the timing capacitor 4, the oscillation frequency is determined by the time for charging and discharging the timing capacitor 4. The time for charging the timing capacitor 4 is inversely proportional to the current flowing from the P-channel MOS transistor 13 of the inverting circuit 1, which is a current source. Since the current flowing from the current source transistor 13 changes depending on the voltage applied to the frequency control terminal 6, the oscillation frequency can be controlled by the voltage.

In addition, the logic threshold of inverting circuit 1.2.3 is a P-channel MOS
) Since the current flowing from the transistor 13 is adjusted by the voltage applied to the frequency control terminal 6, the logic threshold value does not vary depending on the current value of the current source as in the conventional example.

FIGS. 2(a) and 2(b) are circuit block configuration diagrams showing a second embodiment of the present invention.

Referring to FIGS. 2(a) and 2(b), FIG. 2(a) is a circuit configuration diagram of an inverting circuit 1, and this inverting circuit 1 has P
channel MOS) transistor 11, N channel MOS
P-channel M constituted by transistors 12 and 13
OS) The drain terminal of transistor 11 is N channel M
OS) is connected to the drain terminal of the transistor 12 and becomes the output of the inverting circuit 1, and the gate terminal is an N-channel MOS
The inverting circuit 1 is connected to the gate terminal of the transistor 12.
The source terminal is connected to the power supply. The drain terminal of N-channel MOS transistor 13 is connected to the source terminal of N-channel MOS transistor 12,
The gate terminal becomes a control terminal of the inverting circuit 1, and the source terminal is grounded.

In FIG. 2(b), an inverting circuit 2.3 has the same configuration as the inverting circuit 1, and a first terminal of a timing capacitor 4 whose second terminal is grounded to the output terminal 102 of the 0 inverting circuit 1 and an inverting circuit. The input terminal 101 of the inverting circuit 2 is connected to the input terminal 101 of the inverting circuit 2, and the output terminal 102 of the inverting circuit 2 is connected to the input terminal 101 of the inverting circuit 3.
Output terminal 102 of inverting circuit 3 is input terminal 1 of inverting circuit 1
01, the output terminal 102 of the inverting circuit 3 is connected to the output terminal 5, and the output signal is taken out from the output terminal 5.
The control terminal 103 of the inverting circuit 1.2.3 is connected to the frequency control terminal 6.

Next, the operating principle of the second embodiment will be explained. The basic operating principle is the same as that of the ring oscillator shown in the conventional example. As shown in the signal waveform diagram shown in FIG. 1(C), if the input signal of the inverting circuit 1 is Ov at time T1, the logic threshold of the inverting circuit 1 is usually VDD when the power supply voltage is VDD.
Since it is set to DD/2, the output of the inverting circuit 1 is inverted to VDD while charging the timing capacitor 4. The output of the 0 inverting circuit 1 is further transmitted to the inverting circuit 2.3, and is inverted at time T2. The input terminal of circuit 1 becomes VDD. Then, the output terminal of the inverting circuit 1 becomes 0■ without rapidly discharging the timing capacitor 4, propagates to the inverting circuit 2.3, and reaches the time T.
3, when it is propagated again to the input terminal of the inverting circuit 1, it becomes OV again, and the 0 inverting circuit 2.3 operates as an oscillation circuit.
If the delay time of 3 is sufficiently small compared to the time to charge timing capacitor 4, the oscillation frequency will be equal to the timing capacitor 4.
determined by the time it takes to charge and discharge. The time to charge the timing capacitor 4 is determined by the N channel M of the inverting circuit 1 which is a current source.
Since the current flowing into the current source transistor 13 changes depending on the voltage applied to the 0 frequency control terminal 6, which is inversely proportional to the current flowing into the O5 transistor 13, the oscillation frequency can be controlled by the voltage.

As described in detail, according to the circuit of the present invention, since the connected all-inverting circuit has a current source, there is no deviation in the logic value of the all-inverting circuit, and the power supply f. becomes larger, allowing stable oscillation even if the amplitude becomes smaller6

[Brief explanation of the drawing]

1(a) and 1(b) are circuit configuration diagrams showing a first embodiment of the present invention, FIG. 1(c) is a signal waveform diagram of the circuit shown in FIG. 1(b), and FIG. (a) and (b) are circuit configuration diagrams showing a second embodiment of the present invention, FIG. 3(a) is a circuit diagram of a conventional example, and FIG. 3(b) is a circuit diagram shown in FIG. 3(a). FIG. 3 is a signal waveform diagram of the circuit. 1.2.3... Inverting circuit, 4.37... Timing capacity, 5.102... Output terminal, 6.1 (D... Frequency control terminal, 11.13.34.36...・P channel MO3) transistor, 12.35...N channel 1
4OS transistor, 32.33... Inverter, 1
01... Input terminal patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai 4Il Financials C

Claims (1)

[Claims] The drain terminal of the first MOS transistor is connected to the second MOS transistor.
The drain terminal of the S transistor is connected to the output terminal, and the gate terminal of the first MOS transistor is connected to the second MOS transistor.
The source terminal of the first MOS transistor is connected to the drain terminal of a third MOS transistor, and the gate terminal of the third MOS transistor is used as a control input terminal. , an odd number of inverting circuits formed by connecting the source terminal of the third MOS transistor to a first power source and connecting the source terminal of the second MOS transistor to a second power source are connected in series; A voltage controlled oscillation circuit characterized in that an output terminal of a final stage inverting circuit is connected to an input terminal of a first inverting circuit, and a control terminal of each of the inverting circuits is connected to a frequency control signal terminal.