JPH0427729B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a voltage-controlled oscillator whose oscillation frequency can be controlled by a direct current voltage, and particularly to a voltage-controlled oscillator suitable for IC implementation.

[Background of the invention]

An example of a conventional voltage controlled oscillator is shown in Figure 1. Figure 1 uses a known ring oscillator circuit in which an odd number of inverters are connected in series and the output of the final stage inverter is fed back to the input of the first stage. This is an example, and the figure shows an example using three inverters 1, 2, and 3. Input pulse voltage waveforms 4, 5, and 6 of each stage of inverters 1, 2, and 3 are shown in FIG. 2 with the same numbers attached. The principle operation of the oscillator shown in FIG. 1 will be explained below. Suppose now that the input signal 4 increases from the logic level "0" to the "1" level. When the input signal 4 exceeds the threshold voltage indicated by the broken line in FIG. 2 at time a, the polarity of the output level of the inverter 1 is reversed, so that
The input 5 goes from the "1" level to the "0" level from time a, and descends along a curve determined by the time constant of the output resistance of the inverter 1 and the capacitor 7. Note that in FIG. 2, the transient portion of the input waveform is shown using an approximate straight line. Furthermore, if a well-known complementary metal oxide semiconductor (CMOS) is used for the inverter, the threshold voltage will generally be a value near the midpoint voltage between the "1" level and the "0" level.

As described above, when the voltage of input signal 5 decreases and passes the threshold at time b, inverter 2
The polarity of the output level is reversed. A capacitor 8 and a variable capacitance diode 9 are connected to the input end of the inverter 3. The variable capacitance diode 9 has a characteristic that its capacitance value changes depending on the reverse DC voltage applied thereto. The capacitor 8 is used for cutting DC power, and generally has a capacitance sufficiently larger than that of the variable capacitance diode 9. Therefore, if a DC voltage is applied to the terminal 10 in the configuration shown in FIG. 1, the input terminal of the inverter 3 will be provided with a variable capacitor. When the polarity of the output of the inverter 2 is reversed as described above, the input signal 6 rises from time point b along a time constant curve determined by the output resistance of the inverter 2 and the capacitance value of the variable capacitance diode 9. do. When the input signal 6 exceeds the threshold at time c, the polarity of the output of the inverter 3 is reversed, and the input signal 4 of the inverter 1 falls along a curve determined by the output resistance of the inverter 3 and the capacitor 11. . After time c, the input level fluctuation transient part in the opposite direction to the above explanation is transmitted at each time d, e, and f in the same way as the above explanation, and at time a' the state returns to the same pulse phase state as at time a. . After time a', the operation from a to a' is repeated, and the circuit shown in FIG. 1 oscillates. If the time difference between the above-described points is t ₁ to _{t 6} as shown in FIG. 2, then the oscillation period T is T=t ₁ +t ₂ +t ₃ +t ₄ +t ₅ +t ₆ .

Here, if the DC voltage applied to the terminal 10 is changed to change the capacitance value of the variable capacitance diode 9, the above-mentioned times _t2 and _t5 change, so the oscillation period T
changes. That is, the oscillation frequency can be controlled by the DC voltage applied to the terminal 10. Generally, as the capacitors 7 and 11, stray capacitances parasitic to the inverter input section are often used.

By the way, when converting the conventional voltage controlled oscillator described above into an integrated circuit (IC), it is extremely difficult to form the large capacitor 8 or the variable capacitance diode 9 on the same IC chip as the inverters 1 to 3. Therefore, it is necessary to add a component separate from the IC, leading to an increase in the number of input/output terminals of the IC and an increase in the number of components.

Therefore, the elements that change the oscillation frequency are
As a voltage controlled oscillator that can be integrated into an IC chip, an odd number of CMOS inverters are connected in series to form a ring oscillator circuit, and at least one of the inverters composing this inverter A new path for supplying voltage to the next stage inverter input terminal via
A configuration has been proposed in which MOS transistors are inserted in series, and the conduction resistance is controlled by a DC voltage applied to the gate terminal of the inserted MOS transistors, so that the pulse delay time in the inverter section can be varied. .

An example of such a conventional device will be explained with reference to FIG. In the following figures, parts having the same functions as those in FIG. 1 are given the same numbers as in FIG. 1. In Fig. 3, inverter 2, which is indicated by a logic symbol in Fig. 1,
is shown using a MOS transistor circuit for ease of explanation. As is well known in the CMOS technology, an inverter is constructed by connecting a P-channel MOS transistor (PMOS) 12 and an N-channel MOS transistor (NMOS) 13 as shown. Gate terminals G of the PMOS 12 and NMOS 13 are commonly connected and serve as an input terminal of the inverter. One terminal of NMOS13 is connected to the first power supply voltage V _SS
(ground in Figure 3), and one terminal of the PMOS 12 is connected to the second power supply voltage, which has a higher voltage value than the first power supply voltage.
NMOS13, _PMOS
12, each other one terminal is connected in common and becomes an output terminal of the inverter.

In the conventional example shown in FIG. 3, PMOS1 is connected between the output of inverter 2 and the input of inverter 3.
4, NMOS15 is inserted. As is well known in CMOS circuits, PMOS12 of inverter 2,
Depending on the voltage level of the input 5, one of the NMOS 13 becomes conductive (low resistance) and the other becomes open (high resistance). When PMOS12 is conductive (NMOS13 is open), _PMOS
12. Current flows through the parallel circuit of PMOS 14 and NMOS 15 to capacitor 16 attached to the input terminal of inverter 2, and capacitor 16 is charged. Also, when NMOS13 is in a conductive state (PMOS12 is in an open state), the PMOS
A current flows to V _SS (ground in FIG. 3) through the parallel circuit of NMOS 14 and NMOS 15 and NMOS 13, and capacitor 16 is discharged. As is well known, the conduction resistance value of the MOS transistors 14 and 15 depends on the DC voltage value applied to the gate terminal G, and the PMOS
14, the higher the gate voltage, the higher the NMOS1
5 has a characteristic that the conduction resistance value increases as the gate voltage decreases. Therefore, PMOS14,
By using each gate terminal G of the NMOS 15 as a control voltage input terminal and appropriately changing the DC voltage value applied thereto, t ₂ ,
The time _t5 can be controlled, and the oscillation frequency can be controlled in the same way as in the conventional example shown in FIG.

By the way, in the conventional example shown in FIG. 3, the capacitor 16 is a stray capacitance parasitic to the input terminal of the inverter, similar to the capacitors 7 and 11, or a small capacitor that can be easily generated on a CMOS IC chip. The voltage controlled oscillators shown in Figure 3 are all built on the same IC.
It is possible to integrate it on a chip.

FIG. 4 shows another conventional example. In the figure,
The PMOS 12 and NMOS 13 operate equivalent to the inverter 2 shown in FIG. Here, when PMOS12 is conductive, _PMOS12 , PMOS
A current flows into the capacitor 16 via the capacitor 14 . Further, when the NMOS 13 is in a conductive state, a current flows from the capacitor 16 to the ground via the NMOS 15 and the NMOS 13. Similar to Figure 3
By applying control voltages to the gate terminals G of the PMOS 14 and NMOS 15, a voltage controlled oscillator can be realized with the configuration shown in FIG. Furthermore, as is clear from the explanation of FIG. 3, the voltage controlled oscillators shown in FIG. 4 can all be integrated on the same IC chip.

FIG. 5 shows still another conventional example. The conventional example shown in FIG. 5 is an example in which a MOS transistor whose conduction resistance value is controlled is inserted in only one of the charging path and the discharging path of the capacitor 16, and the illustrated configuration has an NMOS 15 inserted in the discharging path. . FIG. 6 shows pulse waveforms at each part in FIG. 5.

In the conventional example shown in FIG. 5, only the time constant of the portion where the voltage of the input signal 6 of the inverter 3 changes from the "1" level to the "0" level changes due to the DC voltage applied to the gate terminal G of the NMOS 15. , frequency control is realized by varying only the time shown as _t5 in FIG.

In the conventional examples shown in FIGS. 3 and 4 described above, the DC voltage for frequency control is
Two systems are required, one for NMOS15 and one for NMOS15, but the fifth
In the conventional example shown in the figure, frequency control is possible with one control voltage for the NMOS 15.

In addition, in general, Figures 3, 4, and 5
The CMOS inverter 1, 2 or 3 has a delay time between the input pulse and output pulse at the part where the input pulse changes from "0" level to "1" level,
It is designed so that the delay time at the portion where the input pulse changes from the "1" level to the "0" level is approximately the same. That is, in inverter 1, t ₁ and t ₄ are approximately the same time, and in inverter 3, t ₃ and t ₆ are approximately the same time. Therefore, in the conventional examples shown in Figs. 3 and 4, if the voltages applied to the gate terminals G of PMOS 14 and NMOS 15 are respectively set so that t ₂ and t ₅ in Fig. 2 are the same, the frequency can be changed. However, the time for each half cycle of the oscillation pulse obtained from the oscillator can be kept approximately the same. That is, it is theoretically possible to control the frequency while maintaining the following relationship.

t ₁ + t ₂ + t ₃ ≒ t ₄ + t ₅ + t ₆ ≒ T/2 ...(2) However, in the conventional example shown in Fig. 5, only t ₅ in Fig. 6 changes and the frequency changes. The time of the oscillation pulse waveform of the oscillator changes every half cycle.

As explained above, both of the conventional examples shown in FIGS. 3 and 4 use MOS transistors of two different conductivity types, PMOS 14 and NMOS 15, as conduction resistance control elements. For this reason,
For controlling PMOS14 and controlling NMOS15,
Two systems of control DC voltages are required, which differ not only in voltage value but also in the direction of increase/decrease in voltage value during frequency control.

Here, in the configuration shown in FIG. 3 or 4, in order to obtain an output with a pulse duty of approximately 50% at the output 4, it is necessary to make the conduction resistance values of the PMOS 14 and the NMOS 15 approximately the same. Therefore, in order to keep the pulse duty almost constant when changing the oscillation frequency, the conduction resistance value variable characteristics of the PMOS 14 and the NMOS 15 must be made almost the same. For this reason, extremely delicate consideration is required in selecting the element sizes of PMOS14 and NMOS15 and in designing the circuit that generates the control voltages for the two systems, and when implementing the IC, the balance of the above-mentioned conduction resistance variable characteristics may be lost. However, there were problems in implementation, such as difficulty in obtaining desired characteristics.

In addition, in the conventional example shown in Fig. 5, only one type of conductivity is used.
Since only the MOS transistor is used as the conduction resistance control element, there is no need for a well-balanced design like the conventional examples shown in Figures 3 and 4 above, but it is possible to vary the frequency while maintaining the pulse duty of approximately 50% output. It is impossible.

[Purpose of the invention]

An object of the present invention is to make it possible to integrate elements that change the oscillation frequency in the same IC chip, and to easily obtain an oscillation output that maintains the pulse duty at approximately 50% even when the oscillation frequency is varied. An object of the present invention is to provide a voltage-controlled oscillator.

[Summary of the invention]

The gist of the present invention is to configure a ring oscillation circuit by connecting an odd number of CMOS inverters in series, and to connect two or more even number of inverters to the next stage through the inverter. Insert a new MOS transistor in series only in the path that charges the inverter input terminal, or connect a new MOS transistor in series only in the path that discharges the inverter input terminal of the next stage through that inverter in the even number of inverters mentioned above. By inserting one of the above into a single DC voltage,
By making it possible to control the conduction resistance value of the MOS transistor, that is, to control the oscillation frequency, and by performing the conduction resistance value control using the even number of inverter sections, the output pulse duty can be maintained at approximately 50%. .

[Embodiments of the invention]

FIG. 7 shows an embodiment in which control with one frequency control voltage is possible and the time of each half cycle of the oscillation pulse can be kept the same.

In FIG. 7, the circuit has the same configuration as PMOS12', NMOS13, and 15 instead of inverter 1 in FIG.
3' and 15' circuits are used. In this embodiment, the discharge time constant of the capacitor 7 is also controlled in the same way as the discharge time constant of the capacitor 16 is controlled. FIG. 8 shows pulse waveforms at various parts in FIG. 7. In figure 7
PMOS12', NMOS13', 15', respectively.
Using MOS transistors having the same electrical characteristics as the PMOS 12, NMOS 13, and 15, and designing the capacitor 7 and the capacitor 16 so that their capacitances are the same can be realized using current CMOS technology. If this is done, t ₂ and t ₄ in FIG. 8 will be almost the same. In addition, the gate terminals G of NMOS 15 and 15' are commonly connected to serve as a control voltage input terminal 10,
Even if the oscillation frequency is changed by changing the DC voltage applied to this, t ₁ and t ₅ in FIG. 8 become almost the same, so the above-mentioned relationship of equation (2) is maintained. Therefore,
If the oscillator output is taken from the output of the inverter 3, an oscillation output pulse can be obtained in which the time of each half cycle is approximately constant (that is, the pulse duty is approximately 50%) regardless of the oscillation frequency and regardless of which half cycle.

However, in FIG. 7, the 8th pulse of input pulse 5
If the slope of the fall from time a in the diagram and the slope of the fall of input pulse 4 from time c become significantly different due to frequency control, it is possible that t ₂ and t ₄ will also differ. It will be done.

That is, if the slope of the fall of the input pulse 5 becomes extremely gradual, the gain of the inverter that outputs the pulse 6 will be insufficient, and the slope of the rise of the pulse 6 from time point b will suddenly become gradual. On the other hand, at the rising edge of pulse 5, since inverter 3 acts as a buffer amplifier, the slope does not change much.

As a result, the waveform symmetry between pulses 5 and 6 is lost, and especially if time e arrives before pulse 6 reaches its highest potential, an imbalance between t ₁ and t ₅ will occur and the duty of pulse 4 will be reduced. Stabilization performance deteriorates.

In order to prevent this, an inverter may be inserted as a buffer amplifier into the output section of the pulse 5. For example, in the example shown in Figure 7, an example was shown in which only NMOS was used as the conduction resistance control element, but NMOS
The fourth point is that it is possible to realize a voltage-controlled oscillator that uses only PMOS instead of the oscillator and changes only the time constant of the capacitor charging path.
This is clear from the description of FIGS. 5, 5, and 7.

Furthermore, in a voltage controlled oscillator that controls the conduction resistance of only either the charging path or the discharge path of the capacitor, two inverters each having a function of controlling the conduction resistance are used as shown in the embodiment shown in FIG. If an even number of the above is used, the oscillation frequency can be controlled with one DC voltage as explained in Figure 7, and a voltage that can obtain a pulse with approximately 50% duty as the oscillator output regardless of the oscillation frequency. A controlled oscillator can be easily constructed. The case where two inverters with the above-mentioned conduction resistance control function are used has been described with reference to FIG. 7, but it will be explained below that the same effect can be obtained even if an even number of inverters greater than two are used.

FIG. 9 shows a case where a ring oscillation circuit is constructed using an arbitrary odd number of three or more inverters, and two of these inverters are provided with the above-mentioned unidirectional conduction resistance control function. In the subsequent figures, the conduction resistance controlled inverter is shown with an arrow attached to the logic symbol.

As shown in Figure 9, since the total number of inverters is an odd number, one of the inverters with arrows has an even number including 0 between the input and output, and the other has an odd number of ordinary (no arrow) Connected with an inverter. At this time, as is clear from the explanation of the embodiment shown in FIG. 50% oscillator output can be extracted.

Next, consider the case in which two sets of conduction resistance control inverters are added to FIG. If any two of the normal inverters in FIG. 9 are marked with arrows and rearranged, either a or b in FIG. 10 will be obtained. Note that in the subsequent figures, normal inverter parts are shown by broken lines without logic symbols, and "even" or "odd" indicates that the number of inverters is even or odd, including only 0.

From Figure 10a and b, when four inverters with arrows are used, the input and output of the inverters with arrows are connected by an odd number of normal inverters, and the loop of the ring oscillation circuit is cut in this route. , it can be seen that there is always a path in which a circuit is constituted by a set of two inverters with arrows connected between input and output by an even number of inverters (including those with arrows). This is the route indicated by "odd" marked with a circle in FIGS. 10a and 10b.

If the oscillator output is extracted as described above from any part between the input and output of the inverters with arrows in the above path, the two inverter delay times that can be varied by one set of the two inverters with arrows are combined. Since it is distributed every half cycle of the oscillator output,
It is possible to obtain an output with a pulse duty of 50%. Further, in FIG. 10a, a similar oscillator output can be obtained from the "even" portion marked with a circle.

Hereinafter, it will be explained that the above effect can be obtained using any even number of inverters with arrows of 2 or more.

FIG. 11 shows a ring oscillation circuit using an arbitrary odd number of inverters of three or more. Since the total number of inverters is an odd number, if arrowed inverters are used as an even number of these inverters, there will always be a portion where the input and output of the arrowed inverters are connected by an even number of normal inverters. This portion is indicated by an underlined "even" in FIG.

Inverters A and B with arrows connected by the above “even”
The other input/output of , that is, the output of B and the input of A are coupled by an odd number of inverters.

Next, consider adding two inverters C and D with arrows, which are normally connected to A and B only by inverters.If the output of C and the input of D are connected by an even number of inverters, the output of D If the oscillator output is taken between the inputs of ~C, the same number of inverter delay times of A, B, C, and D are distributed every half cycle. When adding two inverters with arrows in this way, the part connected by an even number of inverters (including those with arrows) between the input and output of the newly added inverter with arrows will be connected to the inverter with arrows before this. If all are included, an oscillator output with a pulse duty of 50% can be obtained from the part connected by an odd number of ordinary inverters between the input and output of the inverter with an arrow added at the end.

〔Effect of the invention〕

According to the present invention, the voltage controlled oscillator can be configured with only MOS transistors or only MOS transistors and small capacitance capacitors, making it possible to integrate all the oscillators on one chip IC, which reduces the number of circuit components. effective.

[Brief explanation of drawings]

Figures 1, 3, 4 and 5 are block diagrams showing conventional voltage controlled oscillators, and Figures 2 and 6 are main parts of the block diagrams shown in Figures 1 and 5. A waveform diagram of each part, FIG. 7 is a configuration diagram showing an embodiment of the present invention, FIG. 8 is a waveform diagram of each part of the configuration diagram of FIG. 7,
FIG. 9, FIG. 10, and FIG. 11 are simplified configuration diagrams for explaining the effects of the present invention, respectively. 12, 12', 14, 14'...P channel
MOS transistor, 13, 13', 15, 15'
...N-channel MOS transistor.

Claims (1)

[Claims] 1. The gate terminals of the P-channel MOS transistor and the N-channel MOS transistor are commonly connected to serve as an input terminal, one terminal of the P-channel MOS transistor is connected to a first power supply, and the other terminal is an output terminal. as a terminal, and also as the above N-channel MOS
A voltage-controlled oscillator having a configuration in which an odd number of logic gates are connected in series in a ring shape, with one terminal of a transistor connected to a second power source and the other terminal serving as an output terminal, is configured with the following: be done. a First logic gate An even number of two or more is provided in the device. Each logic gate has a first conductive path connecting the first power supply and the input terminal of the next stage logic gate through the P-channel MOS transistor, and a second power supply through the N-channel MOS transistor. The second conductive path is connected to an input terminal of a next-stage logic gate, and a MOS transistor has two terminals whose conductive resistance is changed by a voltage applied to the gate terminal. The two terminals of the MOS transistor are connected in series to one of the first conductive path and the second conductive path. The gate terminal of the above MOS transistor is 2
It is commonly connected between an even number of logic gates, and a control voltage is applied thereto. b Second logic gates An odd number of them are provided in the device. The output terminals of the P-channel MOS transistor and the N-channel MOS transistor are commonly connected. 2. The voltage controlled oscillator according to claim 1, wherein the second logic gate is provided between adjacent first logic gates.