JP3003594B2 - Three-state ECL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a three-state type ECL (Emitter Coupled Logic) circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, high integration is progressing, and reduction in power consumption is also required. However, an ECL logic circuit suitable for high-speed operation has a relatively large power consumption. In particular, low power consumption is desired.

FIG. 4 shows an example of a configuration of a conventional three-state type ECL inverter circuit.

Referring to FIG. 4, the differential amplifier circuit includes NPN bipolar transistors Q11 and Q12 having emitters connected in common and connected to the collector of NPN bipolar transistor Q13 to form a differential pair. The collectors of the transistors Q11 and Q12 are connected to one ends of the resistors R11 and R12, respectively.
Is connected to a high-potential power source (high-potential source) GND, and the emitter of the bipolar transistor Q13 is connected to a low-potential power source (low-potential source) VEE via a resistor R13.

[0005] The base of the bipolar transistor Q13 is connected to the reference voltage VCS and acts as a constant current source.

An NPN type bipolar transistor Q21 is provided as an output emitter follower circuit to which the output of the differential amplifier is input. The collector of the transistor Q21 is connected to the higher power supply GND, and the base is a bipolar transistor forming a differential pair. The collector is connected to the transistor Q12, and the emitter is connected to the output terminal OUT.

The state control circuit includes NPN bipolar transistors Q31 and Q32 whose emitters are commonly connected to form a differential pair, and a bipolar transistor Q33 whose collector is connected to the commonly connected emitters of transistors Q31 and Q32. And the transistor Q33
Is connected to the lower power supply VEE via a resistor R31, and the base of the transistor Q33 is connected to a reference potential VCS.
To form a constant current source.

Here, a current flowing through a constant current source consisting of bipolar transistor Q13 and resistor R13 is I1, a current flowing through a constant current source consisting of bipolar transistor Q33 and resistor R31 is I2, and bipolar transistor Q13 is
13, assuming that the forward voltage between the base and the emitter of Q33 is VF, I1 and I2 are given by the following equations (1) and (2), respectively.

I1 = (VCS-VF) / R13 (1) I2 = (VCS-VF) / R31 (2)

The collector of the bipolar transistor Q31 is connected to the higher power supply GND, and its base is connected to the output of the inverter circuit INV1 that inverts and outputs the state control terminal CT.

The collector of the bipolar transistor Q32 is connected to the output stage (collector of the transistor Q12) of the differential amplifier circuit, and the base is connected to the reference voltage Vr.

The input terminal IN is connected to an inverter circuit INV2.
, And the other input terminal of the two-input NAND circuit NAND is connected to the output of the inverter circuit INV1, that is, the base of the bipolar transistor Q31, and the output of the two-input NAND circuit NAND Is the bipolar transistor Q of the differential amplifier circuit.
12 bases.

In the above configuration, the state control terminal CT is
In the Low state, the output of the two-input NAND circuit NAND outputs the state of the input terminal IN as it is.

At this time, if the base potential of the bipolar transistor Q12 is higher than the reference voltage Vr, the constant current I1 flows through the bipolar transistor Q12, so that the base potential of the bipolar transistor Q21 (the output potential of the differential amplifier). ) Is −I1 × R12, the output voltage Vout is Vout = −I1 × R12−VF (3), and the low level of the ECL is output.

Conversely, if the base potential of the bipolar transistor Q12 is lower than the reference voltage Vr, the constant current I1 flows through the bipolar transistor Q11 and does not flow through the bipolar transistor Q12.
The base potential of the bipolar transistor Q21 rises to the level of the higher power supply GND, and the output voltage Vout becomes −
VF, and the ECL High level is output.

When the state control terminal CT is in the High state, the output of the two-input NAND circuit NAND is fixed at the High level regardless of the input signal IN, the bipolar transistors Q12 and Q32 are turned on, and the bipolar transistors Q11 and Q31 are turned on. Are both turned off.

Therefore, the load resistance R12 of the differential amplifier circuit
The current flowing through I1 + I2 (constant current sources Q13 and Q33)
), The base potential of the emitter follower transistor Q21 becomes-(I1 + I2) × R12 (4).

Normally, the ECL output is output through a terminating resistor,
Termination voltage VT = -2V.

However, in this case, the base potential of the bipolar transistor Q21 drops to, for example, about -1.7 V, so that a forward voltage between the base and the emitter is not obtained in the transistor Q21, and the transistor Q21 is turned off.

Therefore, the output potential drops to the termination voltage VT. In the case of the ECL circuit, this is called "Z state".

FIG. 5 shows a three-state type E different from the above.
An example of the configuration of a CL circuit is shown (see JP-A-4-256217).

Referring to FIG. 5, in the three-state type ECL circuit, the differential amplifier circuit differs from the differential amplifier circuit shown in FIG. 4 in that the source is connected between the resistor R11 and the higher power supply GND. Power supply GND, drain with resistor R
Similarly, a p-channel MOS transistor M1 inserted so as to be connected to a resistor R12 and a higher power supply GN
D, a p-channel MOS inserted to connect the source to the higher power supply GND and the drain to the resistor R12
One end of a resistor R13 is connected to a common connection point of the transistor M2 and the anodes of the diodes D11 and D12 whose cathodes are connected to the collectors of the bipolar transistors Q11 and Q12, respectively. It is connected to the source of the connected n-channel MOS transistor M3.

P channel MOS transistors M1, M2
The gates of the n-channel MOS transistor M3 are commonly connected, and are connected to the state control terminal CT.

The collectors of the bipolar transistors Q21 and Q22 forming the output emitter follower circuit are both connected to the higher power supply GND, and the bases are respectively connected to the collectors of the bipolar transistors Q12 and Q11 forming a differential pair. Are output terminals OU
T and OUT2. Here, the output terminal OU
T and OUT2 are so-called complementary outputs, and when compared with FIG. 4, the bipolar transistor Q22 and the output terminal OUT2 may be omitted. Further, in the circuit shown in FIG. 5, the state control circuit (differential pair Q3
1, Q32, current source Q33, etc.) are not required.

In the above configuration, the state control terminal CT is at L
In the ow state, the n-channel MOS transistor M3 is turned off, and the p-channel MOS transistor M1,
M2 is turned on, and in this case, as a so-called ECL differential circuit, the output terminal O
The UT has an input terminal IN and an inverted state, and an output terminal OUT.
2 outputs the same state as the input terminal IN.

Conversely, when the state control terminal CT is in the High state, the n-channel MOS transistor M3 is turned on, the p-channel MOS transistors M1 and M2 are turned off, and a current flows through any of the load resistors R11 and R12. Instead, only the current flows to the resistor R13.

At this time, assuming that the current flowing through the constant current source Q13 is I1 and the voltage between the terminals of the diode is VF, the base potentials of the bipolar transistors Q21 and Q22 constituting the output emitter follower circuit are both -I1 × R13- VF (5) and outputs the Z state.

[0028]

However, the above-mentioned prior art has the following problems.

(1) The first problem is that the conventional three-state ECL circuit shown in FIG. 4 requires two current sources (ie, a constant current source transistor for a differential amplifier circuit). In addition to Q13, the constant current source Q33 for three-state control increases its power consumption.

(2) As a second problem, in the conventional three-state ECL circuit shown in FIG. 5, a MOS transistor (three MO transistors) is provided on the load side of the bipolar differential pair.
Although the complete current path switching is performed using the S transistors M1, M2, and M3), the switching speed is reduced, which may hinder high-speed operation, which is an advantage of the ECL circuit.

(3) As a third problem, in the conventional three-state type ECL circuit shown in FIG. 5, the output level in the Z state is determined by the series connection of the resistor R13 and the diode D11 or D12. However, there is a difference between the current values flowing through the diodes D11 and D12 depending on the state of the input terminal IN.
This means that the output level may fluctuate due to the difference in VF of the diode. Further, since the VF of the diode changes with temperature, there is a possibility that the output level also changes with temperature.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a three-state type ECL circuit which can solve the above problems and reduce power consumption. is there.

[0033]

To achieve the above object, a three-state ECL circuit according to the present invention has an emitter commonly connected, connected to a lower power supply through a constant current source, and connected to a reference voltage and an input. In an ECL circuit including first and second bipolar transistors each having a signal as a base input and a collector connected to a higher power supply via first and second resistors to form a differential pair, And an emitter in common with the collector and the emitter of one of the bipolar transistors of the differential pair,
A third bipolar transistor having a base to which a state control signal is input; a third resistor between a collector of the third bipolar transistor and the higher power supply;
Switch means connected in series to the third resistor and controlled to be on / off by the state control signal.

According to the present invention, by controlling on / off of the third bipolar transistor and the switch means by the state control signal, a constant current is supplied to the first resistor and the second resistor connected in parallel to the first resistor. And a third resistor,
Alternatively, switching is performed so as to flow through the second resistor, and the output potential is output in three states of High, Low, and Z.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. According to the present invention, in a preferred embodiment, the resistance for the logic amplitude of the ECL circuit is set to two.
One parallel resistor, one of which is turned on / off by a switch means, and a third state control transistor connected in parallel with one of the ECL differential transistor pairs to provide a logical amplitude resistance value and a constant current path. Is changed, and three states, that is, a normal High level and a Low level, and a Z state can be output.

FIG. 1 is a diagram showing a configuration of a preferred embodiment of the present invention. Referring to FIG. 1, a three-state type ECL circuit according to an embodiment of the present invention has first and second emitters connected in common, and a differential pair comprising a reference voltage Vr and an input signal voltage as base inputs, respectively. Two bipolar transistors Q1 and Q2, and the collectors of the first and second bipolar transistors Q1 and Q2 are connected to a higher power supply (high potential source) via first and second resistors R1 and R2, respectively. The first and second bipolar transistors Q1,
The commonly connected emitter of Q2 is connected to a lower power supply (low potential source) via a constant current source I, and an output is taken from the collector of the second bipolar transistor Q2.
In the CL circuit, the second bipolar transistor Q2
A third bipolar transistor Q3 sharing the collector and the emitter of the third bipolar transistor Q3 is connected in parallel, a state control signal (CT) is connected to the base of the third bipolar transistor Q3, and the collector is connected to the third resistor R3 and the switch means. It is connected to the higher power supply via SW.

The switch means SW is provided with a state control signal C
The third bipolar transistor Q3 is turned on / off by T. The third bipolar transistor Q3
And by controlling the switch means SW, the constant current I
To the first resistor R1 (output is High), or both the second resistor R2 and the third resistor R3 (output is Low), or only the second resistor R2 (output is Z). And outputs the potential of the output terminal in three states of High, Low, and Z.

When the state control signal CT is in the low state, the switch means SW is turned on, the third bipolar transistor Q3 is turned off, and the resistance for obtaining the logical amplitude of the parallel combined resistance of the resistances R2 and R3 is obtained. And normal E
Functions as a CL inverter circuit. Conversely, when the state control signal CT is in the High state, the switch means SW is turned off, the third bipolar transistor Q3 is turned on, and the current drawn by the constant current source flows only through the second resistor R2. The Z state can be output by the voltage drop.

[0039]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[0040]

Embodiment 1 FIG. 1 shows a configuration of a three-state ECL inverter circuit as a first embodiment of the present invention.

Referring to FIG. 1, in the differential amplifier circuit at the input stage of the three-state type ECL inverter circuit, the emitters are commonly connected, and a base (reference) voltage Vr and an input signal IN are input to a base, respectively. It includes first and second bipolar transistors Q1 and Q2 forming a differential pair, and includes first and second bipolar transistors Q1 and Q2.
Are connected to the higher power supply GND via the resistors R1 and R2, respectively. As a current source circuit of this differential pair,
The collectors are the first and second bipolar transistors Q1,
A bipolar transistor Q4 is connected to the commonly connected emitter of Q2, the base is connected to the reference voltage VCS, and the emitter is connected to the lower power supply VEE via the resistor R4.

As an output stage, the collector is a higher power supply GN
D, the emitter is connected to the output terminal OUT,
A bipolar transistor Q5 having an emitter follower configuration having a base connected to the collector (output of the differential pair) of the second bipolar transistor Q2 is provided.

As a state control circuit, the third bipolar transistor Q3 is connected to the second bipolar transistor Q2.
Connected to share the collector and emitter of
The base of the third bipolar transistor Q3 is connected to the state control terminal CT.

In this embodiment, as the switching means, the drain of the p-channel MOS transistor P1 is connected to the higher power supply GND, the gate is connected to the state control terminal CT, and the source is connected via the resistor R3. 2,
The third bipolar transistors Q2 and Q3 are connected to a commonly connected collector.

Next, the operation of the circuit according to this embodiment will be described.

When the state control terminal CT is set to Low level, the p-channel MOS transistor P1 is turned on, and the third bipolar transistor Q3 is turned off. In this case, the circuit operates as an ECL inverter circuit using the parallel combined resistance of the resistors R2 and R3 as a resistor for obtaining a logic amplitude.

On the other hand, when the state control signal terminal CT is set to a high level, the p-channel MOS transistor P1 is turned off, and the third bipolar transistor Q3 is turned on. In this case, since the third bipolar transistor Q3 is in the on state, the current flowing from the constant current source Q4 flows to the third bipolar transistor Q3 side, and the p-channel MOS transistor P1 is in the off state. No current flows through R3 (resistor R3 is removed from the current path), current flows only through resistor R2, and resistance R
2, a voltage drop occurs, and the Z state is output.

The base potential Vbase (Z) of the bipolar transistor Q5 at the output stage in this Z state is given by the following equation (6). Vbase (Z) = − I × R2 (6)

Here, I is a current flowing from the constant current source Q3, and is given by the following equation (7). I = (VSC−VF) / R4 (7)

Here, VF indicates a forward voltage between the base and the emitter of the bipolar transistor.

When the output is Low, the base potential Vbase (L) of the bipolar transistor Q5 in the output stage is output.
Is given by the following equation (8). Vbase (L) = − I × (R2 // R3) (8)

Here, R2 // R3 indicates a parallel combined resistance value of R2 and R3.

For example, when R2 = R3, the base potential of the output-stage bipolar transistor Q5 becomes the output state L
In the Z state, the voltage is about twice lower than in the ow state, and the bipolar transistor Q5 can be turned off.

In the above embodiment, the constant current source is set to 1
As a result, the power consumption is reduced to about half as compared with the prior art shown in FIG. 4, and the Z state can be output irrespective of the input level.

[0055]

Second Embodiment FIG. 3 shows a configuration of a three-state ECL circuit according to a second embodiment of the present invention.

Referring to FIG. 3, this circuit has the same configuration as the input terminal (IN) of the differential pair in the circuit configuration shown in FIG.
2 and the reference voltage VR. The circuit shown in FIG. 2 operates as an inverter in normal operation, whereas the circuit according to this embodiment operates as a buffer.

In this case, when the Z state is output, the current path changes depending on the input level. Therefore, when the state control terminal CT is in the High state, a Low level must always be input to the base of the bipolar transistor Q1. In the present embodiment, the bipolar transistor Q1 on the input terminal side is provided.
Is connected to the output of a two-input AND gate (AND), one input terminal of the two-input AND gate is connected to the input terminal IN, and the other input terminal is connected to the state control terminal CT.
Are connected via an inverter INV.

Therefore, when setting the Z state,
When the state control terminal CT is in the High state, the base of the bipolar transistor Q1 can always be at the Low level (turn off the bipolar transistor Q1), and the Z state is output irrespective of the input signal IN. be able to.

In this embodiment, the output states Low, H
The levels of the high state and the Z state are the same as in the first embodiment, and a description thereof will be omitted.

[0060]

As described above, according to the present invention, the following effects can be obtained.

(1) The first effect of the present invention is that the current consumption can be reduced to about half as compared with the three-state type ECL circuit using two constant current sources described as the prior art. It is.

The reason is that the present invention combines the constant current sources into one.

(2) A second effect of the present invention is that high integration can be achieved by simplifying the circuit configuration and reducing the number of elements.

(3) A third effect of the present invention is that a stable Z state can be maintained when the output state is the Z state.

The reason is that, in the present invention, when the output state is the Z state, the element for determining the output level is as follows.
This is because a diode is not used as in the above-described related art, and the state of the input terminal is made irrelevant to the level of the Z state.

[Brief description of the drawings]

FIG. 1 shows a three-state ECL according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of a circuit.

FIG. 2 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional three-state ECL gate.

FIG. 5 is a diagram showing a circuit configuration of another conventional three-state ECL gate.

[Explanation of symbols]

 Q1 to Q5 Bipolar transistor P1 P-channel MOS transistor R1 to R4 Resistance Vr Reference voltage (terminal) IN input signal (terminal) CT State control signal (terminal) GND Higher power supply VEE Lower power supply OUT Output terminal AND AND gate INV Inverter circuit

Claims (4)

(57) [Claims] An emitter is commonly connected and connected to a lower power supply through a constant current source, a reference voltage and an input signal are respectively used as base inputs, and a collector is connected to a higher power supply via first and second resistors, respectively. In an ECL circuit having first and second bipolar transistors connected to a power supply and forming a differential pair, a collector and an emitter are commonly connected to a collector and an emitter of one of the bipolar transistors of the differential pair. A third bipolar transistor having a base to which a state control signal is input, a third resistor connected in series between the collector of the third bipolar transistor and the higher power supply, and a third resistor in series with the third resistor. A three-state type ECL circuit, wherein a switch means connected and switched on / off by the state control signal is inserted. 2. The switch connected in series with the third resistor .
By changing the resistance value of the logic amplitude resistance and the constant current path by turning on / off the switch means , the normal H
2. The three-state ECL circuit according to claim 1, wherein the three-state ECL circuit is configured to output a total of three states, i.e., an high level, a low level, and a Z state. 3. A constant current is controlled by controlling the on / off of the third bipolar transistor and the switch means in accordance with the state control signal. Or the second resistor, and the output potential is changed to High, Low, Z
Three-state type ECL circuit according to claim 1, wherein the output of tri-state. 4. An emitter is commonly connected and connected to a lower power supply via a constant current source, an input signal and a reference voltage are respectively used as base inputs, and a collector is connected to a higher power supply via first and second resistors, respectively. In an ECL circuit having first and second bipolar transistors connected to a power supply and forming a differential pair, a collector and an emitter are commonly connected to a collector and an emitter of one of the bipolar transistors of the differential pair. A third bipolar transistor having a base to which a state control signal is input, a third resistor connected in series between the collector of the third bipolar transistor and the higher power supply, and a third resistor in series with the third resistor. And a switch means connected and controlled to be on / off by the state control signal. When the state control signal is in an active state, the first Three-state ECL circuit, characterized in that the means for fixing the state of the input signal to be input to the base of the bipolar transistor to Low level, with the.