JPS6175618A - Complementary bimis tri-state gate circuit - Google Patents

Abstract

PURPOSE:To prevent much rash current from flowing by using a bipolar transistor (TR) for an output stage and using a CMOS circuit for a pre-stage so as to turn on the bipolar TR requiring a large drive current at transient state. CONSTITUTION:The range of input voltages where the bipolar TRs are at off/off state is adjusted by combining CMOS TRs, the bipolar TRs and resistors so as to avoid completely the on/on state of the bipolar TRs. When an enable signal Tc goes to a low level, since both a PCMO TRP3 and an NMOS TRN3 are turned on, the base potential of the PNP TRT1 goes to a high level and the base potential of the NPNT2 goes to a low level. Thus, since the PNPTRT1 and the NPNTRT2 are both turned off forcibly, the input signal VIN is changed to a high or a low level, and the output OT is kept to a high impedance state.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention controls the amount of rush current that flows in a circuit having a PNPI transistor and an NPN transistor when both are turned on at the same time.

Furthermore, while reducing the rush current to almost 0,
The present invention relates to a complementary MIS bipolar mixed three-state gate circuit that can achieve low power consumption by realizing a state circuit and also eliminating current flowing through the circuit in a high impedance state.

(2) Technical background PMISI transistor (hereinafter referred to as PMO3I transistor) and NMI S transistor (hereinafter referred to as NMOS
CMIS circuit (hereinafter referred to as 0
Since the power consumption of the M03 circuit (referred to as M03 circuit) is small, its use as a semiconductor integrated circuit is expanding. Also, PNP
Power supply ■ between transistor and NPN transistor. Since the circuit connected in series between 0 and ■ss with their collectors in common is made of bipolar transistors, the output current can be increased, so the circuit has a large driving capacity and is suitable for an output-cover sofa.

Also, the 3-state circuit has low level and high level.

It has 3 high impedance output states.

For example, this circuit is used when a plurality of circuit elements are connected to one bus and only the necessary circuit elements are accessed from the bus.

(3) Problems with the prior art However, in the related bipolar transistor circuit, 0M0
When a 3-state circuit is realized in combination with 3 circuits, 9 When the input signal transitions from high level to low level or from low level to high level, the PNP l-transistor and NPN transistor in the output stage are turned on at the same time, Rush current is the power source ■. . There was a problem that there was a flow between the signal and VSS. Furthermore, due to this rush current, even though a bipolar transistor circuit was provided in the output stage.

The drawback was that it could not flow large output currents.

(4) Purpose of the Invention The present invention reduces power consumption by controlling rush current, and also allows a large output current to flow, making it suitable for output buffers. The purpose is to provide a 3-state gate circuit.

(5) Structure of the Invention According to the present invention, the first P-type MIS transistor connected to the high-potential power supply side, the first N-type MIS transistor connected to the low-potential power supply side, and both a first complementary MIS gate circuit having a first impedance element provided between the transistors, and receiving an input signal in common to the gates of the first P-type and N-type MIS transistors.

It has a second P-type MIS transistor connected to the high-potential power supply side, a second N-type MIS transistor connected to the low-potential power supply side, and a second impedance element provided between the two transistors. death.

a second complementary MIS gate circuit that commonly receives an input signal at the gates of the second P-type and N-type MIS transistors;

a pull-up bipolar transistor whose base is connected to the connection point between the first P-type MIS transistor and the first impedance element; and a pull-up bipolar transistor whose base is connected to the connection point between the first P-type MIS transistor and the first impedance element;
A bipolar circuit including a pull-down bipolar transistor connected to a connection point between an S transistor and a second impedance element, and having these connection points as an output terminal.

a third P-type M[S transistor connected between a high-potential power source and the base of the pull-up bipolar transistor; and a third N-type MIS connected between a low-potential power source and the base of the pull-down bipolar transistor. A complementary B i M I transistor having an enable signal and its inverted signal applied to the gates of the third P-type and N-type MIS transistors, respectively.
This is achieved by providing an S3 state circuit.

(6) Examples of the invention Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a CMOS bipolar mixed three-state gate circuit according to the present invention. 1st. The sources of the second PMOS transistors Pl and P2 are the power supply ■. . connected to,
1st. The sources of the second NMo5 transistors Nl, N2 are connected to the power supply VSS; Second PMO3I-transistor P+.

P2 and 1st. Second NMo5 transistor NI.

The gates of N2 are commonly connected to the input terminal IN.

Then, the first PMOS transistor P1 and the first NM
The O3I-transistor N1 constitutes a first CMOS transistor circuit, and the second PMOS transistor P2 and the second NMOS transistor N2 constitute a second CMQS transistor circuit.

Also, the emitters of the PNPNM transistor and NPN transistor T2 are each connected to the power supply ■. . .

Connected to VSS, pull-up transistor.

They constitute a pull-down transistor, and their collectors are commonly connected to the output terminal OUT. moreover.

The sources of the third PMO3I-transistor P3 and the third NMOS transistor N3 are connected to the power supply V, respectively. 0. Vs
The enable signal To is applied to the gate of this third PMOS transistor P3, and the third N
Enable signal T is applied to the gate of MOS transistor N3.
c is applied via inverter (2) to perform control to bring the output terminal into a high impedance state.

For example, a resistor R is used as the first impedance element.
1 as 1st. A third PMOS transistor Pl, connected between the drains of P3 and the drain of the first NMOS transistor N1, and a first PMOS transistor of this resistor R1
- the connection point B with the drain of the transistor is connected to the base of the PNP l-transistor T1; Further, as the second impedance element, for example, the resistor R2 is connected to the second PMO.
3 transistor drain, and the drain of the 2nd transistor. The resistor R is connected to the drain of the third NMOS transistor.
2 and the drain of the second NMOS transistor N2 is connected to the base of the NPN transistor T2.

Complementary CMOS according to the present invention configured as described above
The operation of the embodiment of the bipolar mixed three-state gate circuit will be described below.

First, when the enable signal is at a low level, both the third PMO3I transistor P3 and the NMOS transistor N3 are turned off.

A bipolar CMOS gate circuit operation that has the same configuration as the bipolar CMO3 circuit described in the previously filed Japanese Patent Application No. 130438/1982, and the output signal changes to high level or low level in response to the high level or low level of the input signal. This is what we do.

That is, the operation of the bipolar CMOS gate circuit having such a configuration will be explained using the voltage transfer characteristic diagrams shown in FIGS. 2 and 3. In particular, FIG. 3 shows the input signal voltage V1N and the potential V at point B,
, C point potential■. The voltage transfer characteristics between the two and shown by the solid line will be explained. First, the case where the input voltage 1N at the input terminal IN is at a low level will be described. When the input voltage ■1N is at a low level (low OV), the PMO3 transistor P
1°P2 is on and NMO3I-transistors Nl and N2 are off, so the connection point B is at a high level.
5V), and on the other hand, at the contact point C, the base current of the NPN l-transistor T2 flows through the resistor R2, and the V
Since s s = OV, it is clamped to a high level by a forward voltage drop of 8° (0.8 V) between the base and emitter of the NPN transistor T2.

Therefore, the PNPNM transistor is off, the NPNI
- Transistor T2 is turned on.

In other words, the input voltage ■1N=L level, that is, approximately Vis
=OV, the potential V8 at point B is approximately Vo. (5V)
, potential at point C■. is V, S+VB.

It is.

Conversely, when the input voltage ■1N is at a high level, °, PMO
S transistor P+ is off, NMO3I- transistor N
1 is on, PMO3I-transistor P2 is off, NMO
3I-Since transistor N2 is in the on state, point C is at a low level (approximately OV).

NPN I-transistor T2 is in the off state. At point B, the PNP transistor TI turns on and the base current of the PNP transistor T1 flows through R+ and the NMOS transistor N1. . -"at (forward voltage drop between base and emitter of pNP transistor T1■86 is approximately 0
．． 8V).

In other words, the voltage at point B is ■. is the input voltage V, N=VD
When D, 0 point is “C” vDD VBt, = 4.2
It has become v.

Next, for convenience to easily understand the operation, the input voltage V1 is
, 4 from low level to high level as shown in Figure 2.
That is, a case will be explained in which the values change in the order of ■, ■, ■, and ■.

First, as mentioned above, when the input voltages ■ and N are at low levels,
PMO3) Run disks P1 and P2 are on and NMO3I-
Since transistors N1 and N2 are off, the potential at point B is
8 is almost ■. . Since the NPN transistor T2 is on, the potential VC at the level 0 point is clamped to vss"vag.The input voltages ■ and N rise, and the
When the threshold voltage vth(N) of NMOS transistors Nl and N2 is reached as shown in FIG.
Since the signal 1 is turned on, the signal 8 gradually falls as shown in the section 2 in FIG. However, VC is an NMOS transistor N
2 is on but not deep enough yet, so N
Determined by forward voltage VIl□ of PN transistor T2 +
Clamped to VS S +VB Ig.

Next, when the input voltage V1 further increases, NMOS
Since transistor N1 turns on deeply, Vl
l falls further. At this time, NMOS transistor N
2 is also deeply turned on, so Vo is NMO3 at the point indicated by ■.
Since the impedance of the I-transistor N2 is influenced more strongly than the impedance between the base and emitter of the NPN transistor T2, the base potential of the NPN transistor T2 becomes lower than v'ss+veg.

Therefore, NPN I-transistor T2 is turned off and v
c begins to decline gradually. At point (2), the base potential of the PNP l-transistor T1 is set to the high power supply (2) due to the PMOS transistor P1 in the on state. . Since the level between base and emitter is not higher than 781, PNP
Transistor T1 remains off.

Then, when the input voltage ■1N further increases, the NMO3 transistor N1 becomes sufficiently deep (turned on) as shown by the point ■, so the potential at the point B becomes sufficiently low through the resistor R1, and ■...- ■Below 8 degrees and turn on PNP transistor T1. Therefore, ■8 is ■..-■11
．． It will be clamped to the voltage of .

Therefore, in ■, the PNP I-transistor T1 changes from on to off, and in ■, the NPN l-transistor T2 changes from off to on, so between ■ and ■.

Both the PNP l-transistor TI and the NPN transistor T2 are turned off.

Then, when the input voltages ■ and N further increase and exceed the dark voltage Vth(P) of the PMOS transistors PI and P2 (point 0 in Figure 2), the PMOS transistor P2 is completely turned off and the NMO3 transistor N2 is fully turned off. Since it is on, Vo becomes VSS as shown by ■. At this time, the NMOS transistor N1 is also sufficiently turned on.

PNP transistor T1 is also on, and VB is ■. .

-VII, remains clamped.

Then, the input voltage (■), N rises above Vth (P) and becomes (■).

. When reaching (■ in Figure 2), ■ is vo. -VB
, remains clamped at l.

V, is held at vss.

Next, the input terminals v and N are now Vo. from.

The case of descending in the order of ■, ■, ■ will be explained. Input voltage V
When 1N falls to Vth(P), PMO3 at point ■
Since the transistor P2 gradually starts to conduct, Vo rises from VS5 toward V 5 g+s as shown in (2). At this time, the base potential of the PNP transistor T1 is
The conduction of the MO3 transistor P1 is not yet sufficient and is therefore at a low level. Therefore, PNP transistor T1 is conductive, so ■8 is ■. o Remains clamped at VBH.

When the input voltage (1N) further decreases, the conduction of the PMOS transistor P1 becomes sufficiently deep, so that the potential at point B rises and the PNP l-transistor T1 is turned off at point (2). For this reason, (8) starts to rise as shown in Figure 9. At this time,
Since the PMOS transistor P2 also becomes more deeply conductive, the potential of ■0 continues to rise.

Next, the input voltage ■1N further decreases and VC becomes NP.
N When the threshold of transistor T2 exceeds g1, NPN
The I-transistor T2 is turned on, as shown by ■.

is clamped to ■ss+vIl□.

In other words, when the input voltage ■ and N are higher than ■, the PNPI
- Transistor T'+ is on, input voltage V from ■, 9. When is low, NPN transistor T2 turns on, and ■
and ■, PNP transistor T1 and NPN h
Both transistors T2 are off. For this reason9
Since both are never turned on, no rush current flows.

Next, when the input voltage V1N further decreases and becomes equal to or less than the threshold value Vth(N) of the NMOS transistors N1 and N2, the NMO3I-transistor N1 turns off at point (3). At this time, since the PMO3 transistor P2 is on, vc remains clamped to Vss+vIl□.

In Fig. 3, the dashed dotted lines y,',y,' represent the resistance R1,
When R2 is large, the PNP transistor T1 is conductive, and ■8 becomes ■. . −■81 requires a larger input voltage ■1N, and NPN
I-Resistor T2 conducts ■. requires a smaller input voltage v,N because it is clamped to vss+vtta.

Therefore, transistor T1. The range of input voltages in which T2 is turned off at the same time becomes large.

In addition, in FIG. 3, the two-dot chain lines V8'' and V(' indicate the case where the resistances R1 and R2 are small, contrary to the above, and the PNP
The input voltages at which the I-transistor T1 and the NPN transistor T2 are turned on become close to each other. When the resistors R1 and R2 are smaller, for example O, the PNP transistors T I, NP
There is a range of input voltages in which the N transistor T2 turns on simultaneously, and as in the conventional case, the PNP transistor T + ,
Rush flows through the NPN transistor T2.

As described in detail above, according to the two embodiments, by combining the 0MO3 transistor, the bipolar transistor, and the resistor, the bipolar transistor is turned off.
The range of input voltage that turns off can be adjusted, and the bipolar transistor turns on.

The on state can be completely eliminated.

Next, when the enable signal Tc becomes low level.

PMOS transistor P3 and NMO3I-transistor N
3 are both turned on, the base potential of the PNPI transistor T1 becomes high level, and the NPN transistor T2
The base potential of is at a low level.

Therefore, both the PNPI transistor T1 and the NPN transistor T2 are forcibly turned off, so the input signal v1N changes to high level or low level and the output OU
T is held in a high impedance state.

Therefore, depending on the high or low level of the enable signal Tc,
The embodiment of FIG. 1 will operate as a three-state gate circuit.

By the way, the enable signal TC becomes low level and the transistor P3. Both N3 are turned on.

When the output is in a high impedance state.

Now, if the input IN is at a low level, the PMO3 transistor P1. Since both P2 are turned on, the power supply V. . -R
Current flows through the path 2R2N5-Vss. However, the resistor R2 has an appropriate impedance that can sufficiently suppress the rush current when both the transistors P2 and N2 are turned on when the input IN is at an intermediate level between high and low levels, so the current as described above is not so large. This does not result in current consumption.

On the other hand, if the input IN is at a high level in the same high impedance state, then the power supply ■. o-P 3-R+ N+
Although a current of Vss flows, the current consumption can be sufficiently suppressed due to the impedance element R1.

In this way, the existence of R1 and R2 is! ! PNP on the output side
It has the function of preventing the transistor T1 and the NPN transistor T2 from being turned on at the same time, and also suppressing the current consumption that would otherwise flow when the output is high impedance.

Another embodiment of the present invention shown in FIG. 4 is an example in which the current flowing when the output is at high impedance can be almost completely eliminated.

This embodiment is in addition to the embodiment shown in FIG.

A fourth PMOS transistor P4 is connected between the drain of PMOS transistor P2 and resistor R2.

The fourth NMOS transistor N4 is connected to the resistor R1 and NMOS
Transistor N! Connect the two drains.

PMO3I - Control signal Tc is applied to the gate of transistor P4.
A control signal is applied to the gate of the NMO3 transistor N4.

In this embodiment, the enable signal T is now activated. Suppose that OUT is at a low level and the output OUT is in a high impedance state.

However, in this embodiment, PMOS transistors P4 and NM
Since both O5 transistor N4 are turned off, the input signal IN is at a low level.

Depending on the high level, any of the current buses created in the embodiment of FIG. 1 can be eliminated.

(7) Effects of the Invention As described above, according to the present invention, a bipolar transistor is used in the output stage, a CMO3 circuit is used in the previous stage, and the bipolar transistors with a large drive current are simultaneously turned on during a transient, causing a large rush current to flow. It is suitable for an output vanofer gate because it prevents this from happening, reduces power consumption, and allows a large output current. Furthermore, it can be used as a 3-state gate buffer, and the current flowing inside the circuit in a high impedance state can be suppressed to a small level.

There is no extra power consumption due to three states.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIGS. 2 and 3 are characteristic diagrams showing voltage transfer characteristics of the above embodiment of the present invention, and FIG. 4 is a circuit diagram showing another embodiment of the present invention. FIG. Pl, R2, R3, R4...PMO3l-transistor, Nl, N2. N3. Na...NMO5I
- transistor, T+...PNP transistor, T2...NPN l- transistor,
R1, R2...Resistor, Tc-...Enable signal, ■...Inverter. C-'---- Patent Applicant: Fujitsu Limited 1-'tsu □Representative Patent Attorney: Hiroshi Matsuoka i'i;,,;j'
::Figure 1

Claims (2)

[Claims] (1) A first P-type MIS transistor connected to the high potential power supply side and a first N-type MIS transistor connected to the low potential power supply side
A first complementary MIS gate circuit that includes an S transistor and a first impedance element provided between the two transistors, and receives an input signal in common to the gates of the first P-type and N-type MIS transistors. and a second P-type MIS transistor connected to the high-potential power supply side, a second N-type MIS transistor connected to the low-potential power supply side, and a second impedance element provided between the two transistors. and the second P-type and N-type M
a second complementary MIS gate circuit that commonly receives an input signal at the gates of the IS transistors; and a pull-up bipolar transistor whose base is connected to the connection point between the first P-type MIS transistor and the first impedance element. and the base is the second N-type MI
A bipolar circuit having a pull-down bipolar transistor connected to a connection point between the S transistor and the second impedance element, and having these connection points as an output terminal, a high potential power source, and a base of the pull-up bipolar transistor. a third P-type MIS transistor connected between the third P-type MIS transistor and a third N-type MIS transistor connected between the low potential power supply and the base of the pull-down bipolar transistor; Complementary BiMIS3 characterized in that an enable signal and its inverted signal are applied to the gates of the transistors, respectively.
state circuit. (2) The first impedance element and the first N-type MI
A fourth N-type MIS transistor is interposed and connected between the S transistor and a fourth P-type MIS transistor between the second impedance element and the second P-type MIS transistor.
Claim 1, wherein an S transistor is inserted and connected, and the enable signal and its inverted signal are applied to the gates of the fourth N-type and P-type MIS transistors, respectively. Complementary BiMIS 3-state circuit.