JP2908254B2 - Three-valued logic input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary logic input circuit, and more particularly to a ternary logic input circuit with reduced current consumption in the ternary logic input circuit.

[0002]

2. Description of the Related Art Referring to FIG. 5, a first conventional ternary logic circuit has two buffers 6 and 7 having different threshold values, and furthermore, the input voltage of input terminal 3 is high impedance. In this case, a pull-up resistor R1 and a pull-down resistor 2 are provided to prevent the inputs of the buffers 6 and 7 from becoming unstable.

Referring to FIG. 6, a second conventional ternary logic circuit has a P-ch having a mirror ratio adjusted to a predetermined value.
MOS current mirror circuit 12 and N-ch whose mirror ratio is adjusted to a desired value in the same manner as current mirror circuit 12
It has a MOS current mirror circuit 13 and further has current limiting resistors R1 and R2.

Further, this kind of technology is disclosed in, for example,
-181220.

Referring to FIG. 7, a third conventional ternary logic circuit includes a switching P-ch MOS in series with an input inverter 21 between a positive power supply 22 and a negative power supply 23.
The transistor P4 is connected, and has a logic circuit for holding an output level.

Next, the operation will be described.

A first conventional three-valued logic circuit shown in FIG.
Logical threshold value VT of two buffers 6 and 7
1 and VT2 are different from each other, so that when the resistance values of the pull-up resistor R1 and the pull-down resistor R2 are appropriately set, the output voltage of the output terminal 4 and the output terminal 5 will be higher if the input voltage of the input terminal 3 is the high potential VDD. Both become high potential VDD, and when the input voltage of the input terminal 3 is an intermediate potential between the high potential VDD and the ground potential VND or high impedance, one output terminal becomes the high potential VDD and the other output terminal becomes the ground potential GND. When the input voltage of the input terminal 3 is the ground potential GND, both become the ground potential GND. From the above results, three combinations of output voltages can be output by the input voltage applied to the input terminal 3.

FIG. 6 shows a second conventional example in which P-ch MOS transistors (P1, P2, P3) and N-ch MO transistors are used.
The current drive capability of each of the S transistors (N1, N2, N3) is determined by the P-ch MOS transistor P1 and the Nc
h The MOS transistor N1 is set equal, and P-c
When the h MOS transistor P2, the P-ch MOS transistor P1, and the P-ch MOS transistor P3 are set in this order, and the N-ch MOS transistor is set in the order of the transistor N3, the transistor N1, and the transistor N2, the output terminal 4 and the output terminal 5 are obtained. The output voltage of
When the input voltage of the input terminal 3 is the high potential VDD, both become the high potential VDD, and the input voltage of the input terminal 3 becomes the high potential V
In the case of an intermediate potential between DD and the ground potential GND or high impedance, the output terminal 5 is VDD and the output terminal 4 is G
ND, and when the input voltage of the input terminal 3 is GND, both become GND. From the above results, three types of output voltages can be output by the input voltage applied to the input terminal 3.

In the third conventional example shown in FIG. 7, an output terminal 4 and an output terminal 5 are formed by a logic circuit comprising an input section inverter 21, a NOR gate 18, an inverter 19, and an AND gate 20.
When the input voltage of the input terminal 3 is the high potential VDD, the output terminal 4 outputs the ground potential GND, the output terminal 5 outputs the high potential VDD, and the input voltage of the input terminal 3 is the ground potential G.
In the case of ND, both output a high potential, and when the input voltage of the input terminal 3 is a low potential (-VDD), the output terminal 4 outputs the high potential VDD and the output terminal 5 outputs the ground potential GND. From the above results, three types of output voltages can be output by the input voltage applied to the input terminal 3.

[0010]

However, in the first conventional ternary logic input circuit shown in FIG. 5, the input voltage of the input terminal 3 is an intermediate potential between the high potential VDD and the ground potential GND or a high impedance. In this case, the input voltage of each of the buffers 6 and 7 is the intermediate potential applied to the input terminal 3 or a voltage obtained by dividing the voltage between the high potential VDD and the ground potential GND by the pull-up resistor R1 and the pull-down resistor R2. Join.

Normally, in order to make the resistance values of the pull-up resistor R1 and the pull-down resistor R2 equal, the input voltage of the buffer 6 and the buffer 7 is set to the high potential V in either case.
There is a problem in that the voltage becomes an intermediate voltage between DD and the ground potential GND, so that a through current is generated in the buffer 6 and the buffer 7 and the current consumption increases.

Further, there is a problem that a current always flows through each of the pull-up resistor R1 and the pull-down resistor R2, and from this point the current consumption also increases.

Further, in the second conventional ternary logic input circuit, the input voltage of the input terminal 3 is high potential VDD and ground potential G.
In the case of an intermediate potential between ND or high impedance, the P-ch MOS transistor P1 and the N-ch M
The OS transistor N1 is turned on at the same time. for that reason,
A through current is generated in the path of the transistor P1, the resistor R1, the resistor R2, and the transistor N1, and the P-ch MOS
The current mirror circuit 12 and the N-ch MOS current mirror circuit 13 have a problem that the through current is further amplified and the current consumption increases.

When the input voltage of the input terminal 3 is high potential VD
Also in the case of D, the input terminal 3 → the resistor R2 → the transistor N1
When the input voltage of the input terminal 3 is at the ground potential GND, the current flows through the path of the transistor P1 → the resistor R1 → the input terminal 3, and the current consumption increases from this point. Was.

Still further, the third conventional ternary logic circuit does not generate a through current during operation, but when the input voltage of the input terminal 3 is high impedance, the input voltage of the input inverter 21 and the input voltage of the NOR gate 18 is increased. Becomes indefinite, so that a predetermined voltage must always be applied to the input terminal 3. Therefore, it has been impossible to directly receive a signal from a tri-state type output buffer.

Further, when using a single power supply, the high potential V
An output buffer that can stably output the midpoint potential between the DD and the ground potential GND is required, and there is a problem that the current consumption in this output buffer increases.

[0017]

A ternary logic input circuit according to the present invention comprises a high potential level, a low potential level, and a high potential level.
Bell and each of the intermediate potential levels between the low potential levels
-Valued logic input circuit having an input terminal for receiving an input signal
A pull-up resistor connecting one end to the input terminal.
Resistance and a pull-down resistor connecting one end to the input terminal
And a first current supplied with power from a high potential power supply.
A mirror circuit, an input side of the first current mirror, and the
A first switch inserted between the first switch and the pull-up resistor;
Second current mirror receiving power supply from low potential power supply
Circuit, the input side of this second current mirror and the pull
A second switch inserted between the second switch and a down resistor;
A high-potential power supply and an input side of the first current mirror circuit;
A third switch inserted in parallel between the
Between the source and the input of the second current mirror circuit.
A fourth switch to be inserted in a column;
The control signal is set so that the circuit current of the power circuit becomes substantially zero.
Each of the first and second switches is turned on
When each of the third and fourth switches is
Off and each of the first and second switches
When in the off state, the third and fourth switches are turned off.
Each is turned on .

Further, three-valued logic input circuit of the present invention, the first switch is constituted by a first P-channel type MOS transistor receiving a pre-SL control signal to the gate, the second
The switch is constituted by a second P-channel type MOS transistor receiving a pre-SL control signal to the gate, the third switch and the third receiving an inverted signal of the previous SL control signal to the gate
Is composed of a P-channel type MOS transistor, said fourth switch is three-valued logic input circuit according to claim 2, characterized in that it is composed of N-channel type MOS transistor receiving a pre-SL control signal to the gate.

[0019]

[0020]

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a ternary logic input circuit according to a technique related to the present invention.

[0023] The three-valued logic input circuit of this is, on the switch SW1 high potential power supply 1 and the pull-up resistor during operation R1
And the other terminal of the pull-up resistor R1 is connected to the input terminal 3, one end of the pull-down resistor R2, and a switch SW3 which is turned on during operation. Further, a switch SW2 which is turned on during operation is connected between the other terminal of the pull-down resistor R2 and the ground potential 2, and one terminal of the switch SW4 which is turned off during operation is connected to the high potential power supply 1
And the other terminal of the switch SW4 is connected to the switch SW4.
3 is connected to each of the other terminal, the input of the buffer 6, and the input of the buffer 7. Furthermore, the output of the buffer 6 is connected to the output terminal 4 via a latch circuit 8, and the output of the buffer 7 is connected to the output terminal 5 via a latch circuit 9.

Switches SW1, SW2, SW3 and S
Each on / off operation of W4 is controlled by a control signal PS2, and the through / latch operations of the latch circuits 8 and 9 are controlled by a control signal PS1.

Next, the operation of the ternary logic input circuit of the technique related to the present invention will be described.

[0026] The three-valued logic input circuit of this is, and each is on switches SW1, SW2 and SW3 is in operation,
SW4 is off, and each of the latch circuits 8 and 9 is also in a through state.

In this state, when the input voltage of the input terminal 3 is at the high level, both of the output voltages of the output terminal 4 and the output terminal 5 are output at the high level. When the input voltage of the input terminal 3 is at the low level, both output the low level. When the input voltage of the input terminal 3 is an intermediate potential between the high potential VDD and the ground potential GND or a high impedance, a High level is output to one output terminal and a Low level is output to the other output terminal. As described above, three types of output voltages can be output according to the input voltage applied to the input terminal.

Next, after the output setting is completed, the control signal P
By switching S1, the output levels of the output terminals 4 and 5 are latched. Thereafter, as shown in FIG.
After a lapse of time equal to or longer than the delay time between input and output of the entire ternary logic input circuit of the embodiment, the control signal PS2 is switched to turn off each of the switches SW1, SW2 and SW3, and to turn on the switch SW4 to turn on the buffers 6 and 7. Enter a non-operation state in which the input is set to a high level.

These control signal PS1 and control signal P
The through current can be completely eliminated by performing the switching signal of S2. As a result, the current consumption can be reduced irrespective of the input voltage of the input terminal 3 except when the output levels of the output terminals 4 and 5 are set.

Switches SW1, SW2, SW3 and S
The reason for providing a time difference between the switching timing of each of W4 and each of the switching timings of the latch circuits 8 and 9 is that the buffer 6 and the buffer 7 and the latch circuits 8 and 9 are inactive before latching due to the delay time. In order to prevent the set output level from changing.

FIG. 2 is a block diagram of a ternary logic input circuit according to the first embodiment of the present invention.

The ternary logic input circuit of the first embodiment has
One end of a switch SW3 and a P-ch MOS transistor (P1, P2, P
3), the gates of P-ch MOS transistors (P1, P2, P3) are all connected to Pc
h Drain of MOS transistor P1, switch SW
3 and a switch SW1 which is turned on during operation.
In each of the two terminals. Also,
The drain of the P-ch MOS transistor P2 is set to Nc
h Connected to the drain of the MOS transistor N2 and one input of the NOR gate 14. Furthermore, P-ch MO
The drain of the S transistor P3 is connected to the drain of the N-ch MOS transistor N3 and one input of the NOR gate 15. Further, the P-ch MOS transistors (P1, P2, P3) use the current mirror circuit 1
Constituting No. 2.

Further, in the ternary logic input circuit of this embodiment, one terminal of the resistor R1 is connected to the other terminal of the switch SW1, the other terminal of the resistor R1 is connected to the input terminal 3, and one terminal of the resistor R is connected. Switch S which is connected to and turned on during operation
One terminal of W2 is connected to the other terminal of the resistor R2, and the other terminal is connected to one terminal of a switch SW4 that is turned off during operation, and N-ch MOS transistors (N1, N2, N
The configuration is connected to all the gates of 3) and the drain of the N-ch transistor N1. Furthermore, switch SW
4 and the sources of all the N-ch MOS transistors (N1, N2, N3) are connected to the ground potential 2. Further, the N-ch MOS transistors (N1, N2, N3) constitute a current mirror circuit 13.

Further, the ternary logic input circuit of this embodiment has a configuration in which the outputs of the NOR gate 14 and the NOR gate 15 are connected to the output terminal 4 and the output terminal 5 through the latch circuits 8 and 9, respectively. Switch S
OFF / OFF of each of W1, SW2, SW3 and SW4
OFF, and NOR gate 14 and NOR gate 1
5 is controlled by a control signal PS2,
The through / latch operation of the latch circuits 8 and 9 is controlled by a control signal PS1.

Next, the operation of the three-valued logic input circuit of the first embodiment.

In the ternary logic input circuit of the first embodiment, the switches SW1 and SW2 are turned on and the switches SW3 and SW
4 is off, and each of the latch circuits 8 and 9 is also in a through state. The outputs of the NOR gate 14 and the NOR gate 15 are also inverted outputs of the outputs of the current mirror circuit 12 and the current mirror circuit 13.

In this state, the current driving capabilities of the P-ch MOS transistors (P1, P2, P3) and the N-ch MOS transistors (N1, N2, N3) are equal to those of the transistor P1 and the transistor N1, and the current driving capability of the transistor P2 is Is set larger than the current driving capability of the transistor P1, the current driving capability of the transistor P1 is set larger than the current driving capability of the transistor P3, the current driving capability of the transistor N3, the current driving capability of the transistor N1, and the current driving capability of the transistor N2 are set. When the capacities are set in order, the output voltages of the output terminal 4 and the output terminal 5 are both at the high level when the input voltage at the input terminal 3 is at the high level. When the input voltage of the input terminal 3 is at a low level,
ow level is output. Further, when the input voltage of the input terminal 3 is an intermediate potential between the high potential VDD and the ground potential GND or a high impedance, Lo is applied to the output terminal 4.
The w level is output to the output terminal 5 and the High level is output.

As described above, three types of output voltages can be output by the input voltage applied to the input terminal 3.

Next, after the output setting is completed, the control signal P
By switching S1, the output levels of the output terminals 4 and 5 are latched. Thereafter, a first aspect of the present invention as shown in FIG. 4
After a lapse of time equal to or longer than the delay between input and output of the entire ternary logic input circuit of the embodiment, the control signal PS2 is switched to enter a non-operation state.

By performing these control signal switching operations, it is possible to eliminate the through current. As a result,
Except when setting the output of the output terminal 4 and the output terminal 5, regardless of the input voltage of the input terminal 3, current consumption can be completely eliminated.

Switches SW1, SW2, SW3 and S
W4 and NOR gate 14 and NOR gate 1
The reason for providing a time difference between the switching timings of the latch circuit 5 and the latch circuits 8 and 9 is that the buffer 6
In addition, the delay time between the buffer 7, the latch circuit 8 and the latch circuit 9 causes a non-operating state before latching, thereby preventing a change in the set output level.

Next, a ternary logic input circuit according to a second embodiment of the present invention will be described.

Referring to FIG. 3, in the ternary logic input circuit of this embodiment, a switch SW1 is formed by a P-channel MOS transistor 26, and a switch SW2 is formed by a P-channel MOS transistor.
The switch SW3 is composed of an inverter 24 and a P-channel MOS transistor 25, and the switch SW4 is composed of an N-channel MOS transistor 2
8, except that the configuration is the same as that of the ternary logic input circuit of the first embodiment, the same components are denoted by the same reference numerals, and the detailed description of the configuration and operation is omitted. I do.

[0044]

As described above, according to the present invention, the switches SW1, SW2, and SW that are switched between operation and non-operation are provided.
By adding each of SW3 and SW4, there is an effect that current consumption can be eliminated when the circuit is not operating. In addition, since a latch circuit 8 and a latch circuit 9 for holding the output level once set even during non-operation are added, it is possible to directly connect to a tri-state type output buffer, and to simply connect the output buffer without affecting the others. This has the effect of enabling use with a power supply.

[Brief description of the drawings]

FIG. 1 is a block diagram of a ternary logic input circuit according to an embodiment of the technology related to the present invention.

FIG. 2 is a block diagram of a ternary logic input circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a ternary logic input circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart of switching between operation and non-operation of the ternary logic input circuit of the present invention.

FIG. 5 is a block diagram of a first conventional ternary logic input circuit.

FIG. 6 is a block diagram of a second conventional ternary logic input circuit.

FIG. 7 is a block diagram of a third conventional ternary logic input circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 High potential power supply 2 Ground potential 3 Input terminal 4,5 Output terminal 6,7 Buffer 8,9 Latch circuit 10 Control signal PS1 11 Control signal PS2 12 P-ch MOS current mirror 13 N-ch MOS current mirror 14,15 NOR Gate 16, 17, 19, 24 Inverter 18 NOR gate 20 AND gate 21 Input inverter 22 Positive power supply 23 Negative power supply 25, 26, 27, P1, P2, P3 P-channel MOS transistor 28, N1, N2, N3 N-channel Type MOS transistor SW1, SW2, SW3, SW4 switch

Claims (2)

(57) [Claims] 1. A ternary logic input circuit having an input terminal for receiving an input signal at each of a high potential level, a low potential level, and an intermediate potential level between the high potential level and the low potential level. , A pull-down resistor having one end connected to the input terminal, a first current mirror circuit receiving power supply from a high potential power supply, an input side of the first current mirror, and the pull-up resistor A second switch connected between the first switch and the second current mirror, and a second switch connected between the input side of the second current mirror and the pull-down resistor. 2 switch, a third switch inserted in parallel between the high-potential power supply and the input side of the first current mirror circuit, the low-potential power supply and the second switch.
A fourth switch inserted in parallel between the input side of the current mirror circuit and the first and the third signals by a control signal so that the circuit current of the ternary logic input circuit becomes substantially zero. When each of the two switches is on, each of the third and fourth switches is off, and when each of the first and second switches is off, each of the third and fourth switches Is turned on. 2. The first switch comprises a first P-channel MOS transistor having a gate receiving the control signal, and the second switch has a second P-channel MOS transistor having a gate receiving the control signal. A third P-channel MOS transistor having a gate receiving an inverted signal of the control signal; and a fourth switch having an N-channel MOS receiving the control signal at a gate. 3. The ternary logic input circuit according to claim 2, comprising a transistor.