JP2000049584A - Voltage output circuit provided with level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage output circuit in which a chip area is reduced and power consumption is saved by reducing the breakdown strength of an output stage transistor. SOLUTION: An L-side output transistor 29 connected to -40 V is serially connected to an H-side output transistor 28 connected to 40 V and an output signal S3 is outputted from the connecting point 3. The voltage output circuit is provided with decoding circuits 21-23 generating two decoding signals from two input signals S1 and S2, a first level shift circuit 24 converting one decoding signal into a signal to change between 0 V and 40 V and giving it to the gate of the H-side output transistor 28, a second level shift circuit 25 converting the other decoding signal into the signal to change between -40 V and 5 V and giving it to the gate of the L-side output transistor 29 and a switch circuit for connecting an intermediate level VM to the connecting point of the L-side output transistor with the H-side output transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage output circuit having a level shift circuit, and more particularly, to an output stage MO.
The present invention relates to an improvement in a circuit configuration capable of lowering a breakdown voltage of an S-type transistor.

[0002]

2. Description of the Related Art A conventional output circuit shown in FIG. 3 is a voltage output circuit for supplying a power supply voltage to a liquid crystal display device. This voltage output circuit outputs an output H level V based on two input signals S1 and S2 input to input terminals 1 and 2.
CC (40 V), output L level VEE (-40 V) and intermediate level VM (2.5 V).
One is output to the output terminal 3 as the output signal S3.

The first input signal S1 inputted to the first input terminal 1 is a signal that changes between a logic L level GND (0 V) and a logic H level VDD (5 V). This signal is converted to VEE (−40 V) by the first level shift circuit 4.
The signal is converted to a signal that changes between VEE and VCC (40 V) by the second level shift circuit 5.

The output signal of the second level shift circuit 5 is
A first P-channel MOS transistor (hereinafter, Pc
h transistor), one input terminal of the NAND gate 7 and the inverter 6. The output of the inverter 6 is a first N-channel MOS transistor (hereinafter referred to as an Nch transistor) 10
And one input terminal of the NOR gate 8. The other input terminal of the NAND gate 7 and the other input terminal of the OR gate 8 are connected to the second input terminal 2. The NAND gate 7, the inverter 6, and the NOR gate 8 operate between VEE and VCC, respectively.
The second input signal S2 input to the input terminal 2 of VEE is VEE
And a signal which changes between VCC and VCC.

The source of the Pch transistor 9 and the source of the Nch transistor 10 are both at the intermediate potential VM (2.5
V). The drain of the Pch transistor 9 and the drain of the Nch transistor 10 are both connected to the output terminal 3. The output terminal 3 is further connected to the second Pch
The drain of the transistor 11 and the drain of the second Nch transistor 12 are also connected. The source of the Pch transistor 11 is connected to the positive power supply voltage VCC,
The gate is connected to the output of NAND gate 7. N
The source of the channel transistor 12 is connected to the negative power supply voltage VEE, and the gate is connected to the output of the NOR gate 8.

According to the above-described circuit configuration, the potential of the output signal S3 obtained at the output terminal 3 becomes V, depending on the combination of the H and L levels of the first and second input signals S1 and S2.
It becomes one of three potentials of CC, VEE and VM.

For example, as shown in FIG. 3, when the first input signal S1 is at L level, both the first Pch transistor 9 and the Nch transistor 10 are turned on regardless of the second input signal S2, Second Pch transistor 1
1 and the Nch transistor 12 are both turned off. Therefore, the potential of output signal S3 at this time is intermediate potential VM.
Becomes

When the first input signal S1 is at H level,
First Pch transistor 9 and Nch transistor 1
0 are both turned off and the second input signal S2
Pch transistor 11 and Nch transistor 12
Is turned on. That is, when the second input signal S2 is at the H level, the Pch transistor 11 is turned on, and the potential of the output signal S3 becomes VCC. When the second input signal S2 is at the L level, the Nch transistor 12 is turned on.
Is turned on, and the potential of the output signal S3 becomes VEE.

Thus, the two input signals S1, S
Output H level VCC (40V), output L level VEE (-40V) by a combination of H level or L level
And one of the three voltages of the intermediate level VM (2.5 V) is output from the output terminal 3 as the output signal S3.

[0010]

However, in the conventional voltage output circuit as described above, the output stage transistors, that is, the second Pch transistor 11 and the Nch
VEE (-40V) is applied to the gate of the transistor 12 from VEE.
The voltage of CC (40V) is fully applied. For this reason,
It is necessary to ensure a sufficient withstand voltage of each of the transistors 11 and 12, and as a result, in the case of an integrated circuit, the area for forming each transistor on a chip becomes large. Also,
The inverter 6, the NAND gate 7, and the NOR gate 8 are also applied with the full voltage from VEE to VCC, and therefore must be designed to have a high withstand voltage. For these reasons, the chip area increases. Further, there is also a problem that power consumption is increased due to a through current caused by momentarily turning on both of the transistors in the output stage when the output voltage is switched.

The present invention solves the above-mentioned conventional problems and can reduce the withstand voltage of the transistor in the output stage.
Accordingly, it is an object of the present invention to provide a voltage output circuit capable of reducing a chip area and power consumption.

[0012]

A voltage output circuit according to the present invention is based on an input signal that changes between a logic L level (for example, 0 V) and a logic H level (for example, 5 V).
An output L level lower than the level (for example, −40 V) and an output H level higher than the logical H level (for example, 40 V)
V) an output circuit for selectively outputting the output signal of V),
An L-side output transistor connected to the output L level and an H-side output transistor connected to the output H level are connected in series, an output signal is output from the connection point, and the input signal is set to a logical L level and an output H level. And a first level shift circuit that performs on / off control of the H-side output transistor with the level-converted signal, and converts the input signal between the output L level and the logical H level. A second level shift circuit that converts the level of the signal into a changing signal, and controls on / off of the L-side output transistor with the level-converted signal.

A second configuration of the voltage output circuit according to the present invention is based on two input signals that change between a logic L level (for example, 0 V) and a logic H level (for example, 5 V).
An output L level lower than the logical L level (for example, -40
V), the output H level higher than the logical H level (for example, 40
V) and an output circuit for selectively outputting an output signal of any one of an intermediate level (for example, 2.5 V) between the output L level and the output H level, which is connected to the output L level. The L-side output transistor and the H-side output transistor connected to the output H level are connected in series, an output signal is output from the connection point, and the first input signal is output from the two input signals.
And a decode circuit for generating a second decode signal; and converting the first decode signal into a signal that changes between a logical L level and an output H level, and using the level-converted signal to output an H-side output transistor. 1st on / off control
And a second level shift circuit for converting the level of the second decode signal into a signal that changes between the output L level and the logical H level, and performing on / off control of the L-side output transistor with the level-converted signal. And a switch circuit for connecting an intermediate level to a connection point between the L-side output transistor and the H-side output transistor when both the H-side output transistor and the L-side output transistor are off. And

According to the above configuration, the range of the voltage applied to the gate of the H-side output transistor ranges from the logic L level (0 V) to the output H level (40 V), which is half the conventional level. Similarly, the range of the voltage applied to the gate of the L-side output transistor is from the output L level (−40 V) to the logic H level (5 V), which is almost half of the conventional voltage. Therefore, the withstand voltage of the transistor in the output stage can be significantly reduced, and accordingly, the chip area and power consumption of the integrated circuit can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a voltage output circuit according to a first embodiment of the present invention. In FIG. 1, input signals S1 and S2 input to two input terminals 1 and 2 are converted into two decoded signals by a decoding circuit including an inverter 21, a NAND gate 22, and a NOR gate 23. One of them is provided to the first level shift circuit 24, and the other is provided to the second level shift circuit 25.
The input signals S1 and S2 are both at the logical low level GND (0 V)
And a logic H level VDD (5 V). Inverter 21, NAND gate 22, and NOR
Gate 23 operates between GND (0 V) and VDD (5 V).

The first level shift circuit 24 converts the input GND (0 V) level or VDD (5 V) level signal to the GND (0 V) level or the output H level VCC.
The signal is converted to a signal of (40 V) and applied to the gate of the H-side (Pch) output transistor 28. On the other hand, the second level shift circuit 25 outputs the input GND (0 V) level or VDD (5 V) level signal to the output L level VEE.
The signal is converted into a signal of (-40 V) or VDD (5 V) and is applied to the gate of the L-side (Nch) output transistor 29.

As in the conventional circuit shown in FIG. 3, the source of the H-side output transistor 28 is connected to the output H-level power supply voltage VCC, and the source of the L-side output transistor 29 is connected to the output L-level power supply voltage VEE. It is connected. The drain of the H-side output transistor 28 and the drain of the L-side output transistor 29 are connected, and this connection point is connected to the output terminal 3. An output signal S3 is output from the output terminal 3.

Further, another Pch and Nch transistor 2 is connected between the intermediate level VM (2.5 V) and the output terminal 3.
A switch circuit in which 6, 27 are connected in series is connected. The gate of the Pch transistor 26 is connected to the gate of the L-side output transistor 29, and the Nch transistor 2
The gate of 7 is connected to the gate of the H-side output transistor 28.

According to the above circuit configuration, the combination of the two input signals S1 and S2 at the H or L level allows
The output signal S3 obtained at the output terminal 3 has one of three potentials of VCC, VEE and VM.

For example, as shown in FIG. 1, if the first input signal S1 is at L level, the input signal of the first level shift circuit 24 becomes H level regardless of the second input signal S2. , The input signal of the second level shift circuit 25 is L
Become a level. As a result, both the H-side output transistor 28 and the L-side output transistor 29 are turned off. on the other hand,
The Pch transistor 26 to which the L level signal is input to the gate and the Nch transistor 27 to which the H level signal is input to the gate are both turned on. Therefore, the potential of the output signal S3 at this time becomes the intermediate potential VM.

When the first input signal S1 is at H level,
In response to the second input signal S2, both the input signal of the first level shift circuit 24 and the input signal of the second level shift circuit 25 become H level or L level. That is, the second
If the input signal S2 is at H level, the input signals of the first and second level shift circuits 24 and 25 are both at L level, and if the second input signal S2 is at L level, the first and second Input signals of the level shift circuits 24 and 25 attain the H level. In the former case, the H-side output transistor 2
8 is turned on, and the L-side output transistor 29 is turned off. At this time, the potential of the output signal S3 becomes VCC. In the latter case, since the H-side output transistor 28 is turned off and the L-side output transistor 29 is turned on, the potential of the output signal S3 at this time becomes VEE. In each case, the Pch transistor 26 and the Nch transistor 2
7, the intermediate potential VM and the output terminal 3 are cut off.

According to the above operation, the range of the voltage applied to the gate of the H-side output transistor 28 is GND.
(0V) to VCC (40V) and the conventional (-40V)
To 40V). Similarly, the range of the voltage applied to the gate of the L-side output transistor 29 is VEE (−
40V) to VDD (5V), which is nearly half of the conventional voltage (-40V to 40V). Therefore, the breakdown voltage of both transistors 28 and 29 can be greatly reduced, and the chip area and power consumption of the integrated circuit can be reduced accordingly.

(Embodiment 2) The first embodiment is a voltage output circuit for selectively outputting one of three voltages, VCC, VEE and VM, as an output S3. Is not limited to this, for example, VCC and VEE
The present invention can also be applied to a voltage output circuit that selectively outputs either one of them. A circuit diagram of such an embodiment is shown in FIG. In this circuit, a switch circuit between the VM and the output terminal 3 is deleted from the circuit of the first embodiment shown in FIG. Further, the input signal is only S1, and the decoding circuit is also omitted. Since other circuit configurations are the same, the description of the operation is omitted.

[0024]

As described above, according to the voltage output circuit of the present invention, the withstand voltage of the H-side (Pch) transistor and the L-side (Nch) transistor in the output stage can be reduced to almost half as compared with the prior art. Therefore, the chip area and power consumption of the integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a voltage output circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a voltage output circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional voltage output circuit.

[Explanation of symbols]

 1, 2 input terminals 3 output terminals 21 inverter 22 NAND gate 23 NOR gate 24, 25 level shift circuit 26, 28 P-channel transistor 27, 29 N-channel transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mayumi Matsushita 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5J056 AA04 AA11 BB17 BB57 CC00 CC21 DD12 DD28 FF07 FF09

Claims (2)

[Claims] 1. An output signal having an output L level lower than the logic L level or an output H level higher than the logic H level is selectively output based on an input signal which changes between a logic L level and a logic H level. An output circuit that connects an L-side output transistor connected to the output L level and an H-side output transistor connected to the output H level in series, and outputs the output signal from a connection point thereof; A first level shift circuit that level-converts an input signal into a signal that changes between the logical L level and the output H level, and controls on / off of the H-side output transistor with the level-converted signal; The input signal is level-converted into a signal that changes between the output L level and the logic H level, and the L-side output transistor is turned on / off with the level-converted signal. A second level shift circuit for controlling the voltage output circuit. 2. An output L level lower than the logic L level and an output H higher than the logic H level based on two input signals that change between a logic L level and a logic H level.
An output circuit for selectively outputting an output signal of any one of a level and an intermediate level between the output L level and the output H level, wherein the L side connected to the output L level An output transistor and an H-side output transistor connected to the output H level are connected in series, the output signal is output from the connection point, and a first and a second decode signal are generated from the two input signals. A circuit that converts the level of the first decode signal into a signal that changes between the logical L level and the output H level, and controls on / off of the H-side output transistor with the level-converted signal. And a level shift circuit for converting the level of the second decode signal into a signal that changes between the output L level and the logical H level. A second level shift circuit for controlling ON / OFF of the L-side output transistor; and when the H-side output transistor and the L-side output transistor are both off, the intermediate level is set to the L-side output transistor and the H-side output. A voltage output circuit comprising: a switch circuit connected to a connection point with the transistor.