JP3228260B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on circuit for monitoring a power supply voltage and outputting a power-on reset pulse when the power is turned on, and more particularly to a power-on circuit suitable for use in a semiconductor memory device and a semiconductor integrated circuit device. Circuit and a one-shot pulse generation circuit.

[0002]

2. Description of the Related Art A power-on circuit for detecting a rise in power supply voltage at the time of power-on and outputting a reset pulse will be described. FIG. 5 is a diagram showing an example of a configuration of a conventional power-on circuit. Referring to FIG. 5A, the power-on circuit includes a power-on signal PONB signal generation circuit 1 and a PONB signal.
And a PONS signal generation circuit 2 that detects a transition edge from Low level to High level and generates a one-shot pulse.

The power-on signal PONB signal generation circuit 1
A circuit for monitoring the power supply voltage VCC and detecting when the power supply voltage becomes higher than a predetermined level and generating a power-on signal PONB. There are various configurations, and FIG. 5A shows an example thereof. It is a thing. Referring to FIG. 5A, a power-on signal PONB signal generation circuit 1 includes a P-channel MOS transistor ("PMOS transistor") having a source connected to a power supply potential and a gate and a drain commonly connected.
Q1) and the drain is a PMOS transistor Q1
Connected to the power supply potential,
An N-channel MOS transistor (referred to as "NMOS transistor") Q2 having a source connected to the ground potential. Further, as a non-inversion type buffer circuit, a first inverter INV1 whose input terminal is connected to the drain of the PMOS transistor Q1, an input terminal is connected to the output terminal of the first inverter INV1, and PONB is connected from the output terminal. And a second inverter INV2 for outputting. The first inverter INV1 includes a PMOS transistor Q3 having a source connected to the power supply terminal, a source connected to the ground terminal, a gate connected to the gate of the PMOS transistor Q3 and the inverter input terminal, and a drain connected to the PMOS transistor Q3.
A CMO comprising an NMOS transistor Q4 connected to the output terminal of the inverter together with the drain of the transistor Q3.
SV inverter and a second inverter INV2
Also, like the first inverter, the PMOS transistor Q
5 and an NMOS transistor Q6.

The PONS signal generating circuit 2 includes a delay circuit having an odd number of stages (three stages in FIG. 5) connected in cascade with delay circuit means 4, an input terminal of the PONS signal generating circuit 2 and an output terminal of the delay circuit. And a two-input NAND logic gate G1 connected to the input terminal.

In FIG. 5A, a node N1 is a PM
A connection point between the drain of the OS transistor Q1 and the drain of the NMOS transistor Q2, PONB is an input terminal of the PONS signal generation circuit 2, and N3 is a delay circuit means 4 of the last stage.
Of the output terminal of the NAND gate G1 and the input terminal of the NAND gate G1,
NS is an output terminal of the NAND gate G1.

Referring to FIG. 5 (b), the delay circuit means 4 includes a PMOS transistor Q10 having a source connected to a power supply terminal, a source connected to a ground terminal, a gate having an inverter input together with a gate of the PMOS transistor Q10. It is composed of a CMOS inverter composed of an NMOS transistor Q11 connected to one end and having a drain connected to an inverter output terminal together with a drain of the PMOS transistor Q10.

The operation of the power-on circuit shown in FIG. 5 will be outlined. At power-on, when the difference potential between the potential level of the node N1 and the level of the power supply voltage VCC becomes a voltage level exceeding the threshold voltage VTP of the PMOS transistor Q1 due to the rise of the power supply voltage VCC, the PMOS transistor Q1 is turned on, and the node is turned on. The potential of N1 is
It rises to the level of [power supply voltage VCC level−VTP level].

The potential at the node N1 is equal to the potential at the first inverter INV.
1, the potential of the PON, which is the output terminal node of the first inverter INV1, drops to the ground potential level.
The output of NV2 is inverted, and PONB, which is the signal voltage at the output terminal of the second inverter INV2, rises from the ground potential level to the power supply voltage VCC level.

The node N3 is connected to a power supply voltage V
After the rise to CC, the power supply voltage falls from the VCC level to the ground potential level after a time determined by the delay time of the three stages of the delay circuit means 4.

From the output terminal PONS of the NAND gate G1, the time when PONB transits from the Low level to the High level, and the time when the node N3 which is the potential obtained by inverting the PONB with the delay circuit transits from the High level to the Low level, That is, a one-shot pulse having a pulse width determined by the delay time of three stages of the delay circuit means 4 is output.

[0011]

By the way, the power supply voltage VCC at the time of generating the PONB signal depends on the threshold voltage VT of the MOS transistor. Therefore PO
There is a problem that the pulse width of the NS signal fluctuates due to variations in the threshold voltage VT of the MOS transistor and the like.

That is, when the threshold voltage VTN of the NMOS transistor is low, the first inverter INV
, The potential of the power supply voltage VCC when the PONB signal is generated (when the PONB signal transitions from the low level to the high level) decreases,
On the other hand, the threshold voltage VT of the NMOS transistor
When N is high, the threshold voltage of the first inverter INV is low, so that the potential of the power supply voltage VCC when the PONB signal is generated (ie, when the PONB signal transits from a low level to a high level) increases.

The power supply voltage VC when the PONB signal is generated
When the potential of C is low, the operation speed of the delay circuit means 4 to which the power supply voltage VCC is supplied becomes slow, so that the signal propagation delay time of the delay circuit means 4 increases. As a result, the pulse width of the one-shot pulse signal PONS is increased. Becomes longer, while PON
When the power supply voltage VCC at the time of generation of the B signal is high, the operation of the delay circuit means 4 becomes faster, so that the signal propagation delay time of the delay circuit means 4 is reduced, and the pulse width of the one-shot pulse signal PONS is reduced.

As described above, the pulse width of the one-shot pulse signal PONS that functions as a power-on reset signal depends on the threshold voltage VT of the transistor. For this reason, in the circuit that executes the reset operation by inputting the one-shot pulse signal PONS, the reset cannot be performed, or the reset period is too long.
For example, current consumption increases.

If the pulse width of the one-shot pulse signal used for the power-on reset signal is too long, a circuit in a subsequent stage receiving the power-on reset signal has a D signal.
The C current will continue to flow, and therefore it is desirable that the pulse width be the minimum necessary. Conversely, if the pulse width is too short, the circuit cannot be reset. As described above, since the pulse width of the one-shot pulse signal PONS has a dependency on the threshold voltage VT of the transistor, it is necessary to design the circuit with a margin when designing the circuit.

[0016] For example, Japanese Patent Application Laid-Open No. Hei 5-26809 discloses a delay circuit comprising a CMOS inverter.
A P-channel MOS transistor driven at a constant current between a P-channel MOS transistor of a normal CMOS inverter and a high-potential power supply is provided. A P-channel MOS transistor driven at a constant current is driven between an N-channel MOS transistor of the normal CMOS inverter and a low-potential power supply. A configuration having an N-channel MOS transistor is disclosed.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to reduce the dependence of the pulse width of a power-on reset signal on the threshold voltage VT of a transistor so that a large current can flow. It is an object of the present invention to provide a power-on circuit capable of performing a stable reset without the need.

[0018]

SUMMARY OF THE INVENTION The present invention, which achieves the above object, comprises the steps of: receiving a power-on signal from a circuit for detecting a rise in a power supply terminal voltage and outputting a power-on signal when the power is turned on; A power supply circuit including a delay circuit that delays a signal, and a circuit that outputs a one-shot pulse signal having a pulse width defined by a delay time of the delay circuit from an output of the delay circuit and the power supply signal; The delay circuit includes a CMOS inverter to which a voltage obtained by subtracting a threshold voltage of an N-channel transistor from a power supply terminal voltage as a power supply voltage is included as a delay element.

In the present invention, the delay circuit may include, as a delay element, a CMOS inverter in which a voltage obtained by adding a threshold voltage of a P-channel transistor to a ground terminal voltage is supplied as a ground voltage.

[0020]

Embodiments of the present invention will be described. According to the present invention, at the time of power-on reset, a one-shot pulse PONS generation circuit for resetting a circuit includes a power supply voltage level VCC as a delay circuit element.
−CMOS inverter element using the threshold voltage VTN of an N-channel transistor as a power supply voltage (FIG. 1
(See FIG. 3B), or a CMOS inverter element (see FIG. 3B) using the threshold voltage VTP of the P-channel transistor as the ground voltage.

Transistor threshold voltage VT
Is lower than the typical value, referring to FIG. 1, the power supply voltage VCC level at the time when the power-on signal PONB transitions from the low level to the high level is lower than the level when the threshold voltage FVT of the transistor is the typical value. However, the operating power supply voltage of the CMOS inverter forming the delay circuit element is relatively higher (wider) than when the threshold voltage VT of the transistor is a typical value.
In other words, the delay circuit element works to suppress an increase in delay time per stage, and the pulse width of the one-shot pulse signal PONS is kept constant. On the other hand, when the threshold value voltage VT of the transistor is higher than the typical value, the power supply voltage VCC level at the time when the power-on signal PONB transitions from the Low level to the High level becomes higher than the case where the power supply signal VCC has the typical value. CMOS as delay circuit element
The operating power supply voltage of the inverter is relatively lower (narrower) than a typical value, and works to suppress a decrease in delay time per one stage of the delay circuit element. The pulse width of the one-shot pulse signal PONS is Be kept constant.

With the one-shot pulse generation circuit having the CMOS delay circuit element having such a configuration, the threshold voltage V of the transistor having the width of the one-shot pulse signal PONS is obtained.
Since the T dependency is suppressed and reduced, the DC current amount of the subsequent circuit due to the increase in the pulse width of the PONS is suppressed, and the pulse width of the PONS is kept constant, so that a stable reset operation can be performed.

[0023]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a power-on circuit according to one embodiment of the present invention. Referring to FIG. 1A, in the present embodiment, a power-on signal PONB signal generation circuit 1
And a PONS signal generation circuit 2 for detecting a transition edge of ONB from a low level to a high level and generating a one-shot pulse.

In one embodiment of the present invention, the PONB signal generating circuit 1 has the same circuit configuration as that described with reference to FIG. 5, in which a source is connected to a power supply terminal, and a gate and a drain are commonly connected. PMOS transistor Q1
And an NMOS transistor Q2 having a drain connected to the drain of the PMOS transistor Q1, a gate connected to the power supply terminal, and a source connected to the ground potential, and an input terminal connected to the drain of the PMOS transistor Q1. An inverter INV1 and an input terminal are connected to an output terminal of the first inverter INV1.
, And a second inverter INV2 that outputs
The first inverter INV1 includes a PMOS transistor Q3 having a source connected to the power supply terminal, a source connected to the ground terminal, a gate connected to the inverter input terminal together with the gate of the PMOS transistor Q3, and a drain connected to the PMOS transistor Q3.
CM comprising an NMOS transistor Q4 connected to the inverter output terminal together with the drain of the S transistor Q3
The second inverter INV
Similarly to the first inverter INV1, the CM 2 includes a PMOS transistor Q5 and an NMOS transistor Q6.
It consists of an OS inverter.

The PONS signal generating circuit 2 includes an odd-numbered cascade connection of the delay circuit means 3 and the delay circuit means 4, an input terminal of the PONS signal generating circuit 2, and an output terminal of the delay circuit. -Input NAN connected to the input terminal
And a D logic gate G1.

FIG. 1B shows the delay circuit means 3 shown in FIG.
(C) is a figure which shows an example of the structure of the delay circuit means 4, respectively.

Referring to FIG. 1B, the delay circuit means 3
Is an NMOS whose gate and drain are connected to the power supply terminal
Transistor Q7 and source is NMOS transistor Q
7, a PMOS transistor Q8 connected to the source of
The source is connected to the ground terminal, the gate is connected to the input terminal together with the gate of the PMOS transistor Q8, the drain is connected to the drain of the PMOS transistor Q8, and the NMOS transistor Q9 is connected to the output terminal.
And is provided.

Referring to FIG. 1C, the delay circuit means 4 is composed of a normal CMOS inverter and has a PMOS transistor Q10 having a source connected to a power supply terminal,
The NMOS transistor Q11 has a source connected to the ground terminal, a gate connected to the input terminal together with the gate of the PMOS transistor Q10, and a drain connected to the output terminal together with the drain of the PMOS transistor Q10.

In FIG. 1A, the node N1 is a PM
The connection point between the drain of the OS transistor Q1 and the drain of the NMOS transistor Q2, PON is the output terminal of the first inverter INV1, PONB is the input terminal of the PONS signal generation circuit 2, N3 is the delay circuit means 4 and the NAND gate G1 PONS is a NAND gate G
1 output terminal. N2 is a connection point between the source of the transistor Q7 and the source of the transistor Q8.

The operation of one embodiment of the present invention will be described. FIG. 2 is a timing chart showing operation timing waveforms of the embodiment of the present invention shown in FIG.

In FIG. 2, VCC is a power supply voltage, N1
Is a connection point between the drain of the PMOS transistor Q1 and the drain of the NMOS transistor Q2, PON is an output terminal of the first inverter INV1, PONB is an output terminal of the second inverter INV2 (input terminal of the PONS signal generation circuit 2), N3 is a connection point between the delay circuit means 4 and the input terminal of the NAND gate G1, PONS is the output terminal of the NAND gate G1, N2 is the source of the transistor Q7 and the transistor Q
8 shows respective voltage waveforms at connection points of the eight sources. In addition,
FIG. 2A shows the power supply voltage VCC, and FIG.
2 shows the signal waveforms of FIG.
MOS transistor threshold voltages VTN and PM
FIG. 2D shows a case where the threshold voltage VTP of the OS transistor is a typical value (Typical value) and a case where VTN is lower than the typical value and VTP is a typical value.
(E) shows the signal waveforms of PON, PONB, and PONS when VTN is higher than the typical value and VTP is the typical value.

The operation of the embodiment of the present invention will be described with reference to FIGS.

When the power is turned on and the power supply voltage VCC level slowly rises from 0 V, the potential of the node N1 is maintained at the ground potential via the transistor Q2.

As the power supply voltage VCC rises, the potential difference between the potential level of the node N1 and the power supply voltage VCC becomes P
When the voltage level exceeds the threshold voltage VTP of the MOS transistor Q1, the transistor Q1 is turned on, and the potential of the node N1 rises to the level of [power supply voltage VCC level−VTP level].

The potential at the node N1 is equal to the potential at the first inverter INV.
1, the potential of the PON, which is the output terminal node of the first inverter INV1, drops to the ground potential level.
The output of NV2 is inverted, and PONB, which is the output terminal node of the second inverter INV2, rises from the ground potential level to the power supply voltage VCC level.

The node N3 is at the power supply potential V of the PONB potential.
After a time determined by the delay time of the delay circuit means 3 or 4 from the rise to CC, the power supply voltage falls from the power supply voltage VCC level to the ground potential level.

From the output terminal PONS of the NAND gate G1, a one-shot pulse having a pulse width determined by the delay time of the delay circuit including the delay circuit means 3 and 4 is output by the logic determined by the node N3 and PONB. That is, the output terminal PONS of the NAND gate G1 outputs PO
The time when NB transitions from the Low level to the High level, and the time when the node N3 which is the potential obtained by inverting the PONB with the delay circuit transitions from the High level to the Low level, that is, two delay circuit means 3 and the delay circuit means 4 A one-shot pulse having a pulse width determined by the total delay time is output.

When the threshold voltage VTN of the N-channel transistor is low, the threshold voltage (logic threshold voltage) of the first INV1 is low, so that the potential of the power supply voltage VCC when the PONB signal is generated is low.

In the conventional circuit shown in FIG. 5, since only the delay circuit means 4 composed of a CMOS inverter is used as the delay circuit, if the potential of the power supply voltage VCC when the PON occurs is low, the delay value of the delay circuit And the pulse width of the one-shot pulse PONS increases.

On the other hand, in one embodiment of the present invention, the delay circuit means 3 is used, and the potential of the node N2 of the delay circuit means 3 is [power supply voltage VCC-threshold voltage VTN of NMOS transistor]. This potential is the power supply level of the inverter including the transistors Q8 and Q9.

Therefore, when the threshold voltage VTN of the NMOS transistor is small, the operating voltage of the inverter composed of the transistors Q8 and Q9 becomes higher than when VTN is a typical value, and the delay time of the delay circuit means 3 becomes VTN. Is smaller than in the typical case, the increase in the delay time is offset. As a result, FIG.
As shown in (d), the pulse width of the one-shot pulse PONS is the pulse width of the PONS of FIG. 2C when the threshold voltages VTN and VTP of the NMOS transistor and the PMOS transistor are both typical values (typical values). Is not changed and is kept constant.

When the threshold voltage VTN of the NMOS transistor is high, the threshold voltage of the first inverter INV1 increases, so that the power supply voltage VCC at the time of the occurrence of PONB increases.

In the conventional circuit, since the potential of the power supply voltage VCC at the time of occurrence of PON is high, the delay value of the delay circuit becomes small, and the width of the one-shot pulse PONS becomes small.

In one embodiment of the present invention, when the threshold voltage VTN of the NMOS transistor is large, the potential of the node N2 of the delay circuit means 3 becomes low, so that the operating voltage of the inverter formed by the transistors Q8 and Q9 becomes VT.
Since N becomes lower than the typical value and the delay time of the delay circuit means 3 becomes larger than the case where the VTN is the typical value, the decrease in the delay time is canceled out. As a result, FIG.
As shown in FIG. 2, the pulse width of the one-shot pulse PONS is the same as the pulse width of the PONS of FIG. 2C when the threshold voltages VTN and VTP of the NMOS transistor and the PMOS transistor are both typical values (typical values). , Is assumed to be constant.

In this embodiment, in order to more freely adjust the delay time, the delay circuit means 4 is used in combination with the delay circuit means 3, but the delay circuit means 4 composed of a CMOS inverter is not used. It is clear that this is acceptable. In this case, a delay circuit is formed by cascading the delay circuit means 3 in an odd number of stages.

Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 3A, in this embodiment, a power-on signal PONB signal generation circuit 1 has the same configuration as that of the above-described embodiment, and a PONS signal generation circuit 2 is provided by the delay circuit means 3 of the above-described embodiment. In that it is changed to a delay circuit means 6 from FIG.

Referring to FIG. 3B, the delay circuit means 6 includes a PMOS transistor Q9 having a gate and a drain commonly connected to a ground terminal, an NMOS transistor Q8 having a source connected to the source of the PMOS transistor Q9, and , The source is connected to the power supply terminal, and the drain is NM
PMOS connected to the drain of OS transistor Q8
A transistor Q7, and a PMOS transistor Q7
The gate of the NMOS transistor Q8 is commonly connected to the input terminal, and the drain of the NMOS transistor Q8 is commonly connected to the output terminal.

FIG. 4 is a timing chart showing the operation of the second embodiment of the present invention. In FIG. 4, VCC is the power supply voltage, N1 is the drain of the PMOS transistor Q1 and N1
Connection point of drain of MOS transistor Q2, PON
Is the output terminal of the first inverter INV1, PONB is the output terminal of the second inverter INV2 (the input terminal of the PONS signal generation circuit 2), N3 is the connection point between the delay circuit means 4 and the input terminal of the NAND gate G1, PONS indicates an output terminal of the NAND gate G1, and N2 indicates a voltage waveform at a connection point between the source of the transistor Q7 and the source of the transistor Q8. FIG. 4A shows the power supply voltage VCC, and FIG.
4 shows signal waveforms at the node N1, respectively.
(C) shows the threshold voltage VTN of the NMOS transistor and the threshold voltage V of the PMOS transistor.
When both TPs are typical values (typical values), FIG.
(D) shows the case where VTP is lower than the typical value and the VTN is the typical value, and FIG. 2 (e) shows the case where PON, PO when the VTP is higher than the typical value and the VTN is the typical value.
The signal waveforms of NB and PONS are shown respectively.

The operation of the second embodiment of the present invention will be described with reference to FIGS. When the threshold voltage VTP of the PMOS transistor is low, the node N1 has a higher potential than when the VTP shown in FIG. 4C has a typical (typical) value. .

In the conventional circuit, since only the delay circuit means 4 is used as the delay circuit, if VCC at the time of occurrence of PON is low, the delay value increases, and the one-shot pulse PON
The width of S has increased.

In the second embodiment of the present invention, although the delay circuit means 6 is used, the potential of the node N2 is determined by the threshold voltage VTP of the transistor Q5, and this potential is the CMOS voltage of the transistors Q3 and Q4. The ground level of the inverter. For this reason, when the threshold voltage VTP of the PMOS transistor is small, the operating voltage of the CMOS inverter composed of the transistors Q3 and Q4 becomes higher than when VTP is a typical value, and the delay time of the delay circuit means 6 becomes shorter. The increase in the delay value is canceled out. As a result, as shown in FIG. 4D, the pulse width of the one-shot pulse PONS is a typical value (typical value) for both the threshold voltages VTN and VTP of the NMOS transistor and the PMOS transistor. In this case, the pulse width of the PONS shown in FIG.

When the threshold voltage VTP of the PMOS transistor is high, the potential of the power supply voltage VCC at the time of the occurrence of the PON increases because the node N1 has a lower potential than when the VTP has a typical value.

For this reason, in the conventional example, since the VCC at the time of occurrence of PON is high, the delay value of the delay circuit means 4 is reduced, and the width of the one-shot pulse PONS is reduced.

On the other hand, in the second embodiment of the present invention, the threshold voltage VTP of the PMOS transistor is
Is large, the operating voltage of the inverter composed of the transistors Q3 and Q4 becomes lower than when the VTP has a typical value, and the delay of the delay circuit means 6 becomes longer than when the VTP has a typical value. The decrease is canceled, and as a result, as shown in FIG.
ONS pulse width is NMOS transistor and PMOS
FIG. 4C shows a case where the threshold voltages VTN and VTP of the transistors are both typical values (typical values).
The pulse width of the ONS does not change and is kept constant.

In this embodiment, the delay circuit means 4 is used in addition to the delay circuit means 6 for more freely adjusting the delay time. However, the delay circuit means 4 may not be used. In this case, a delay circuit is configured by connecting the odd number of delay circuit means 6.

The power-on signal PONB signal generation circuit may have any circuit configuration as long as it detects a rise in the power supply voltage VCC and generates a PONB signal, and the configuration shown in FIG. Of course, it is not limited. Also, an example has been described in which a NAND gate circuit that detects a Low active signal from the overlap of High level periods of two signals is used as a circuit for generating the one-shot pulse signal PONS, but the present invention is limited to the NAND gate circuit. Instead, a gate circuit suitable for the logic of the PONB signal and the logic of the one-shot pulse signal PONS is used.

[0057]

As described above, according to the present invention,
By canceling the dependence of the pulse width of the power-on reset signal on the threshold voltage VT of the transistor in the delay circuit of the one-shot pulse generation circuit, the pulse width of the power-on reset signal is made constant, and a large current flows. Thus, there is an effect that a stable reset can be executed without the need.

Further, according to the present invention, the pulse width of the power-on reset is made constant without depending on the threshold voltage of the transistor. This has the effect of stabilizing the operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing operation timing waveforms according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram showing operation timing waveforms according to the second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power-on signal PONB signal generation circuit 2 PONS signal generation circuit 3, 4, 6 Delay circuit means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-294063 (JP, A) JP-A-5-268009 (JP, A) JP-A-54-60849 (JP, A) JP-A-7-294 15308 (JP, A) JP-A-6-309877 (JP, A) JP-A-2000-181581 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17 / 70

Claims (5)

(57) [Claims] 1. A delay for receiving the power-on signal from a circuit for outputting a power-on signal upon detecting that a power supply terminal voltage has become equal to or higher than a predetermined value at the time of power-on, and delaying and outputting the power-on signal. A power supply circuit including a circuit, and a circuit that outputs a one-shot pulse signal having a pulse width defined by a delay time of the delay circuit from an output signal of the delay circuit and the power supply signal. And at least one delay circuit element comprising: an N-channel MOS transistor having a drain and a gate connected to a power supply terminal; and a CMOS inverter connected between a source of the N-channel MOS transistor and a ground terminal. A power-on circuit characterized by the above. 2. A delay for receiving the power-on signal from a circuit for outputting a power-on signal upon detecting that a power supply terminal voltage has become equal to or higher than a predetermined value at power-on, and delaying and outputting the power-on signal. A power supply circuit including a circuit, and a circuit that outputs a one-shot pulse signal having a pulse width defined by a delay time of the delay circuit from an output signal of the delay circuit and the power supply signal. And at least one delay circuit element including a P-channel MOS transistor having a drain and a gate connected to a ground terminal, and a CMOS inverter connected between a source and a power supply terminal of the P-channel MOS transistor. A power-on circuit characterized by the above. 3. A first P-channel MOS transistor having a source connected to a power supply terminal and a gate and a drain commonly connected, and a drain connected to a drain of the first P-channel MOS transistor and a gate connected to the power supply terminal. The first N-channel MO whose source is connected to the ground terminal
An S transistor and an input terminal connected to the first P-channel MO.
A power-on signal generation circuit for outputting a power-on signal; and a power-on signal from the power-on signal generation circuit, the power-on signal including at least a CMOS inverter connected to the drain of the S transistor. A one-shot pulse comprising: a delay circuit for delaying the delay signal; and a gate circuit for outputting a one-shot pulse signal having a pulse width defined by a delay time of the delay circuit from an output signal from the delay circuit and the power-on signal. And a delay circuit of the one-shot pulse generation circuit, wherein the one-shot pulse generation circuit includes a second N-channel MOS transistor having a drain and a gate connected to the power supply terminal, and a source connected to the second N-channel MOS transistor. A second P-channel MOS transistor connected to the source of the N-channel MOS transistor; The second terminal is connected to the ground terminal, the gate is commonly connected to the gate of the second P-channel MOS transistor to form an input terminal, and the drain is commonly connected to the drain of the second P-channel MOS transistor to form an output terminal. 3. A power-on circuit comprising at least one delay element comprising: three N-channel MOS transistors. 4. A first P-channel MOS transistor having a source connected to a power supply terminal and a gate and a drain commonly connected, a drain connected to a drain of the first P-channel MOS transistor, and a gate connected to the power supply terminal. A first N-channel MOS transistor having a source connected to the ground terminal, and a CM having an input terminal connected to the drain of the first P-channel MOS transistor.
An OS inverter; a power-on signal generation circuit for outputting a power-on signal; a delay circuit for receiving the power-on signal from the power-on signal generation circuit and delaying the power-on signal; And a gate circuit that outputs a one-shot pulse signal having a pulse width defined by the delay time of the delay circuit from the output of the circuit and the power-on signal. A delay circuit comprising: a second P-channel MOS transistor having a drain and a gate connected to a ground terminal; a second N-channel MOS transistor having a source connected to a source of the second P-channel MOS transistor; The source is connected to the power supply terminal, and the gate is commonly connected to the gate of the second N-channel MOS transistor. And a third P-channel MOS transistor having a drain connected to the drain of the second N-channel MOS transistor and having an output connected to the drain of the second N-channel MOS transistor. Power on circuit. 5. A semiconductor device comprising the power-on circuit according to claim 1.