JP3535811B2 - Pulse width control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width control circuit, and more particularly to a pulse width control circuit for controlling the pulse width of a one-shot pulse created based on an input pulse.

[0002]

2. Description of the Related Art A conventional pulse width control circuit is used, for example, in an input stage of a semiconductor memory device, in order to perform normal writing even when the power supply voltage is low.
It is provided as a compensation circuit for the write pulse. Such a technique is known from Japanese Patent Laid-Open No. 6-244685, and a write pulse is obtained by using a delay circuit for an input pulse and comparing the input pulse itself with a delayed pulse signal generated by the delay circuit. As one shot pulse is created.

7 (a) and 7 (b) are a pulse width control circuit diagram and an operation timing diagram thereof showing an example of such a conventional example, respectively. First, as shown in FIGS. 7 (a) and 7 (b), the conventional pulse width control circuit uses the input pulse signal source 1
A NOR circuit 2 that receives the input pulse signal IP from one side as one input, and a delay circuit 3 formed by an inverter train composed of inverters of even stages to delay the input pulse signal IP. Output A to N
By supplying it to the other input of the OR circuit 2, the one-shot pulse signal OS as an output signal is created.

In such a control circuit, when the input pulse signal IP changes from low level to high level, the output signal OS changes from high level to low level. At this time, the output signal A of the delay circuit 3 is
Is raised from a low level to a high level while maintaining the delay time difference of 1 and is supplied to the NOR circuit 2. Similarly, even after the input pulse signal IP transits from the high level to the low level, the output signal A of the delay circuit 3 transits from the high level to the low level while maintaining the delay time difference of the delay circuit 3.
It is supplied to the NOR circuit 2. Therefore, the output OS of the pulse width control circuit is the output signal A of the delay circuit 3 after the input pulse signal IP transits from the low level to the high level.
Is a one-shot pulse having a pulse width that is the time required for a transition from a high level to a low level.

In short, the conventional pulse width control circuit obtains the one-shot pulse signal OS of a desired width by adjusting the delay time of the delay circuit 3.

On the other hand, in various personal computers and portable electronic devices using the current semiconductor integrated circuits, from the viewpoint of size and weight reduction, battery driving is required, that is, a power supply voltage of ultra-low voltage of about 1.5V. Moreover, there is a demand for high-speed operation.
In addition, there is a demand for operation when the power supply voltage, which is the conventional operating voltage range, is about 3.6 V, and it has become necessary to realize high-speed operation in a wide power supply voltage range.

However, when the conventional pulse width control circuit is used, the pulse width of the one-shot pulse signal is unnecessarily widened on the low voltage side when the power supply voltage is operating in a wide range.
This makes it difficult to achieve high speed at low voltage. In order to prevent this, that is, in order to realize high-speed operation at a low voltage, it is conceivable to configure the pulse width control circuit with a transistor having a low threshold voltage (Vt). Leak current increases.

For example, when the circuit of FIG. 7 (a) is used and the power supply voltage is 4.6V, 3.0V, 1.7V,
The pulse width of the one-shot pulse OS in (b) is
These are 8.0 nS, 9.0 nS, and 14.7 nS, respectively.

In any case, in the circuit of FIG. 7 described above, since it is composed of the transistor of high Vt,
The current capability of the transistor at low voltage is significantly reduced, which is due to the excessive dependence of the one-shot pulse width on the fluctuation of the power supply voltage.

Therefore, in such a pulse width control circuit, in order to maintain high-speed operation and suppress the leak current during standby, the circuit is constructed by using a transistor of low Vt and a transistor of high Vt. It is possible. For example, as such a technique, Japanese Patent Laid-Open No.
2. Description of the Related Art A semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 210976 is known.

FIG. 8 is a pulse width control circuit diagram showing another conventional example. As shown in FIG. 8, a pulse width control circuit for a semiconductor integrated circuit, which is a conventional low voltage high speed technology,
It is called a multi-threshold voltage CMOS circuit, and a circuit corresponding to the delay circuit 3 in FIG. 5 described above is formed by a low Vt delay circuit 6 including a plurality of CMOS inverters, and a high Vt PMOS transistor Q1 is added. Composed.

That is, the low Vt delay circuit 6 is composed of all low Vt transistors, one of the power supply terminals (in this case, the P channel side forming the CMOS) is connected to the pseudo power supply line VDD, and moreover, true. Power supply line VCC
And the pseudo power supply line VDD, a high-Vt transistor Q1
Are connected. During normal operation, the control signal SL is set to low level to turn on the high Vt transistor Q1, so that the pseudo power supply line VDD functions as a true power supply line VCC. Further, since each CMOS logic circuit is composed of low Vt transistors, it operates at high speed even at a low voltage without significantly deteriorating the current capability. On the other hand, during standby, the control signal S
Since the high Vt transistor Q1 is made non-conductive by setting L to the high level, it is possible to suppress the leak current due to the low leak property of the high Vt transistor Q1.

[0013]

The above-mentioned conventional pulse width control circuit is constituted by only high Vt transistors and the pulse creating operation at a low voltage, that is, the pulse width is sacrificed to some extent, or the high Vt transistors are used. The low Vt transistor is used to realize high-speed operation at a low voltage and suppress the leak current. However, in the case of a multi-threshold voltage CMOS circuit, which is a low-voltage high-speed technology, it is necessary to manufacture MOS transistors that realize two types of Vt, which complicates the manufacturing process.
There is a problem that the manufacturing cost becomes high.

It is an object of the present invention to use a high voltage to generate a one-shot pulse from an input pulse even when the power supply voltage fluctuates or when both a high voltage and a low voltage are used as the power supply voltage. It is to provide a pulse width control circuit that can realize high speed operation when a low voltage is used as in the case of time.

[0015]

A pulse width control circuit according to the present invention includes a NOR circuit for supplying an input pulse to one input terminal to determine the pulse width of a one-shot pulse signal.
A first NMOS connected between a delay circuit for delaying the input pulse for a predetermined time and an output end of the delay circuit and the other input end of the NOR circuit to supply a power supply voltage to a gate to perform a normally-on operation. A second transistor that is connected between the transistor and the other input terminal of the NOR circuit and the ground, supplies a power supply voltage to the gate to perform a normally-on operation, and has a current supply capacity smaller than that of the first NMOS transistor. An NMOS transistor, and is configured to control the pulse width of the one-shot pulse signal by changing the current supply capacity of the first NMOS transistor according to the power supply voltage.

In this pulse width control circuit, when the power supply voltage is high, the power supply is caused by the rising of the input pulse and the falling of the delay pulse at the node to which the first and second NMOS transistors are connected. When the voltage is low, the path of the signal line that determines the pulse width of the one-shot pulse signal is changed by the rising and falling of the input pulse.

Further, in this pulse width control circuit,
A circuit including the delay circuit, the first NMOS transistor, and the second NMOS transistor is connected in cascade, and the output of each stage is connected as an input of the NOR circuit, and the delay of each stage is connected. The current supply capability of each NMOS transistor connected to the circuit is sequentially reduced, and the pulse width of the one-shot pulse signal is determined stepwise according to the power supply voltage.

Furthermore, the delay circuits in each of these stages can set the delay time arbitrarily.

Further, the first NMOS transistor is formed by connecting in parallel a plurality of NMOS transistors having different current supply capacities, and one N-type transistor is formed by an external input signal.
The MOS transistor can be formed to be arbitrarily selected.

Further, the pulse width control circuit of the present invention comprises a NOR circuit for supplying an input pulse to one input terminal to determine the pulse width of the one-shot pulse signal, and for delaying the input pulse for a predetermined time. Delay circuit, a decode circuit for expanding a plurality of external inputs different from the input pulse, an output terminal of the delay circuit and the NOR circuit.
A plurality of NMOS transistors which are connected between the other input terminals of the circuit, and which supply the expanded output of the decoding circuit to the gate to perform a normally-on operation, and the other input terminals of the NOR circuits and the ground, and Supply a power supply voltage to the normally-on operation and
Another NMOS transistor having a current supply capacity smaller than that of the OS transistor, and by selecting a plurality of arbitrary NMOS transistors in combination with the external input to change the current supply capacity, the one-shot pulse signal Is configured to control the pulse width of the.

Further, the pulse width control circuit of the present invention includes a NAND circuit for supplying an input pulse to one input terminal to determine the pulse width of the one-shot pulse signal, and for delaying the input pulse for a predetermined time. And a first PMOS transistor connected between the output terminal of the delay circuit and the other input terminal of the NAND circuit to supply a GND potential to the gate for a normally-on operation.
A second PMOS transistor which is connected between the other input terminal of the NAND circuit and a power supply, supplies a GND potential to the gate to perform a normally-on operation, and has a current supply capacity smaller than that of the first PMOS transistor; And the first PMOS according to the power supply voltage.
The pulse width of the one-shot pulse signal is controlled by changing the current supply capacity of the transistor.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a pulse width control circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, according to the present embodiment, the positive input pulse signal IP output from the input pulse signal source 1 is used as one input N.
Between the OR circuit 2, the delay circuit 3 including a plurality of stages of inverters for delaying the input pulse signal IP, the output terminal (output A) of the delay circuit 3 and the other input (node B) of the NOR circuit 2 The drain and source are connected between the first NMOS transistor 10 whose drain and source are connected to each other and whose gate is supplied with the power supply voltage, and the other input of the GND and NOR circuit 2, that is, the node B, and the power supply voltage is connected to the gate. Is supplied with the first NM
Second, which has much smaller current capacity than the OS transistor
, And the one-shot pulse OS is output from the NOR circuit 2. The second NMOS transistor 20 is provided to prevent the potential of the node B from floating and to stabilize the level. Furthermore, the NOR circuit 2 is also a normal NMOS.
It is formed using a transistor.

In this pulse width control circuit, the output terminal (output signal A) of the delay circuit 3 for determining the pulse width of the one-shot pulse signal OS, which is an output signal, and NO.
It is characterized in that normally-on NMOS transistor transistors 10 and 20 are arranged between the other input terminal (node B) of the R circuit 2 and between the GND and the node B, respectively.

In the normally-on NMOS transistor 10, the current capability changes according to the power supply voltage applied to the gate electrode. That is, when the power supply voltage is high,
The current capacity becomes large, and when the power supply voltage is low, the current capacity becomes small. In addition, the NMOS transistor 20
Similarly, the current capacity changes.

Thus, the potential of the node B with respect to the threshold voltage of the internal NMOS forming the NOR circuit 2 becomes as follows depending on the power supply voltage. That is, when the power supply voltage is high, the potential of the node B exceeds the threshold voltage of the internal NMOS transistor forming the NOR circuit 2, and conversely, when the power supply voltage is low, the potential of the node B is low. The potential does not exceed the threshold voltage.

Therefore, the path of the signal line for determining the pulse width of the one-shot pulse signal OS is set to the node B synchronized with the output A of the delay circuit 3 at the time of high voltage, and the node B at the time of low voltage.
Does not exceed the threshold voltage of the internal NMOS transistor of the NOR circuit 2, the pulse width is determined by the input pulse signal IP without delay.

In this way, the control is performed by changing the input of NOR2, which determines the pulse width of the one-shot pulse signal OS by the power supply voltage, to the output A of the delay circuit 3 or the input pulse signal IP without delay. It is characterized by doing.

FIGS. 2A and 2B are timing charts of various signals at high voltage and low voltage in FIG. 1, respectively. First, as shown in FIG. 2A, when the power supply voltage is high, when the positive-polarity input pulse signal IP changes from low level to high level, the one-shot pulse signal which is the output signal of the pulse width control circuit. The OS transits from the high level to the low level. The output A of the delay circuit 3 is the delay circuit 3 with respect to the input pulse signal IP.
The transition from the low level to the high level is performed while maintaining the delay time difference of 1, and the high level is maintained for a predetermined time. Along with this, the potential of the node B also interlocks with the output A. The potential of the node B is set higher than the threshold voltage of the NMOS transistor.

Similarly, even after the input pulse signal IP transits from the high level to the low level, the output A of the delay circuit 3 transits from the high level to the low level while maintaining the delay time difference of the delay circuit 3. At this time, since the gate input of the NMOS transistor 10 used as normally-on is a high voltage, the current capability is high, and the potential of the node B is the output signal A.
And becomes a potential exceeding the threshold voltage of the NMOS inside the NOR circuit 2. Therefore, the output OS of the pulse width control circuit is the one-shot pulse signal OS whose pulse width is the time from the transition of the input pulse signal IP from the low level to the high level until the transition of the node B from the high level to the low level. Become.

Next, as shown in FIG. 2B, when the input pulse signal IP changes from low level to high level when the power supply voltage is low, as in the case of high voltage, the pulse width control circuit operates. The one-shot pulse signal OS which is an output signal makes a transition from a high level to a low level. Also,
The output A of the delay circuit 3 transits from low level to high level while maintaining the delay time difference of the delay circuit 3. Similarly, even after the input pulse signal IP transits from the high level to the low level, the output A of the delay circuit 3 transits from the high level to the low level while maintaining the delay time difference of the delay circuit 3. Here, an NMOS that functions as a normally-on
The 10-transistor has low current capability because the gate electrode input is low voltage, the potential of the node B does not follow the output A, and changes only to a potential that does not exceed the threshold voltage of the NMOS inside the NOR circuit 2. . Therefore, the NOR circuit 2 is not controlled at the node B, and the pulse width of the one-shot pulse signal OS, which is the output signal of the pulse width control circuit, is determined by the transition time of the input pulse signal IP.

The NMO functioning as a normally-on
As described above, the S transistor 20 is provided for preventing the floating of the node B and stabilizing the level.
A disadvantage of providing this is that a current flows while the node B is generating a pulse, but this normally-on transistor NMOS2
The current capacity of 0 is so small that it can be ignored.
That is, if the current capability is large, the current characteristic itself may be deteriorated by an excessive shoot-through current.
This is because such a problem does not occur if the current capacity is small like the transistor 20.

According to the above-described present embodiment, the same pulse width control circuit does not affect the one-shot pulse width during high voltage operation, and does not affect the one-shot pulse width during low voltage operation more than necessary. It is possible to control so that it does not spread. The reason is that normally-on
This is because the potential of the node B is controlled by utilizing the change in the current capability of the transistor NMOS10 and the route of the signal line that determines the width of the one-shot pulse is changed. As a result, the power supply voltage is, for example, 4.6V, 3.0V, 1.7.
The one-shot pulse widths obtained as the output signals when using V are 8.0 nS, 9.0 nS, 10.
It can be set to 1 nS, and the one-shot pulse width when the power supply voltage is a low voltage such as 1.7 V can be shortened by 4.6 nS as compared with the above-mentioned conventional example (14.7 nS). In short, high speed operation at low voltage can be realized.

FIG. 3 is a pulse width control circuit diagram showing a second embodiment of the present invention. As shown in FIG. 3, in the present embodiment, the delay circuit 3 formed by two-stage inverters is used.
A circuit composed of NMOSs 11 and 21, a delay circuit 4 similarly composed of a two-stage inverter, a circuit composed of NMOSs 12 and 22, and a 3-input NOR 2 are provided.
The 3-input NOR 2 inputs the input pulse signal IP from the input pulse signal source 1 and the potentials of the nodes B and D, and the NMOSs 11 and 12 are the NMOS 1 of FIG. 1 described above.
0, and NMOS21 and 22 are the same as NMOS20.
It is a transistor whose current capacity is much smaller than that of the NMOS transistors 11 and 12. The difference from FIG. 1 described above is that the NMOS 11 that functions as a normally-on transistor,
The current supply capacity of 12 is NMOS11> NMOS12. Here, the NMOS 21 and 22 are NMOS
It is desirable that the relationship between 11 and 12 be the same.

In FIG. 3, the input pulse signal IP from the input pulse signal source 1 is supplied to the NOR circuit 2 and the delay circuit 3 which is an inverter train. The output A of the delay circuit 3 is supplied to a node B via a normally-on transistor NMOS11 having a gate electrode input as a power source. The node B branches into three, the first of which is NOR.
The second circuit is connected to the circuit 2, the second circuit is connected to the input of the delay circuit 4, and the third circuit is connected to the GND via the normally-on transistor NMOS21 whose power source is the gate electrode input. further,
The output C of the delay circuit 4 is connected to the node D via the normally-on transistor NMOS12 which uses the gate electrode input as a power source similarly to the delay circuit 3. This node D
Is connected to GND via a NOR circuit 2 and a normally-on transistor NMOS22 whose power source is the gate electrode input. These normally-on transistors NMO
The S11 and the NMOS 12 are manufactured by changing the gate length or the channel width, and the relationship of the current capability is [N
Current capability of MOS11]> [Current capability of NMOS12]
Set to. Therefore, the relationship between the potentials at node B and node D is
There is always a relation of [potential of node B]> [potential of node D].

By forming this relationship, when the power supply voltage becomes low, the potential of the node D first does not exceed the threshold voltage of the NMOS transistor inside the NOR circuit 2, and the NOR circuit 2 is not at the node D. It is not controlled but is controlled by the node B. Then, when the power supply voltage further decreases, the potential of the node B becomes a potential that does not exceed the threshold voltage of the NOR circuit 2, and the NOR circuit 2 is not controlled at the node B and is determined by the transition time of the input pulse signal IP. Like

The threshold voltage of the NMOS transistor forming the NOR circuit 2 and the threshold voltage of the NMOS transistor forming the delay circuit 4 are the same. If the current capability of the normally-on transistor 11 is <normally-on
If there is a relation of the current capacity of the transistor 12, the power supply voltage becomes a low voltage and the potential of the contact B becomes the NOR circuit 2.
The delay circuit 4 also stops operating when the threshold value of the NMOS transistor forming the delay circuit 4 becomes equal to or less than the threshold value. As a result, the output corresponding to the input pulse IP, that is, the pulse width of the OS cannot be controlled in multiple stages. Therefore, the current capability of the normally-on transistor 11 must be larger than that of the normally-on transistor 12.

Here, the case where the delay circuits have two stages like the delay circuits 3 and 4 has been described, but the number of stages of the delay circuits is not limited, and there are n (n is an even number of 2 or more) stages of delay circuits. A combination of normally-on transistors may be arranged. In the case of such n stages, the delay time of each delay circuit does not need to be the same and can be set freely.

When a plurality of normally-on transistors are arranged, the current capability of the normally-on transistors becomes smaller from the side closer to the input stage of the input pulse signal IP toward the input stage of the NOR circuit 2. Must be set. The reason is that the path for determining the pulse width of the one-shot pulse signal needs to be sequentially changed from the output side by setting the potentials that do not exceed the threshold voltage of the NOR circuit 2 in ascending order of the current capability.

As described above, in the present embodiment, by combining the plurality of delay circuits 3 and 4, the normally-on transistors 11 and 12, and the NMOS transistors 21 and 22 having extremely small current capability, the one-shot pulse width is increased. Can be controlled in multiple stages, and high speed operation with a low voltage source can be realized as in the above-described embodiment.

FIG. 4 is a pulse width control circuit diagram showing a third embodiment of the present invention. As shown in FIG. 4, in the present embodiment, as in the first embodiment, the input pulse signal IP from the input pulse signal source 1 is supplied to the NOR circuit 2, and the input pulse signal IP is also input. And a delay circuit 3 which is an inverter array. This delay circuit 3
The output A of the NMOS transistor 1 is connected in parallel with the gate electrode inputs of the outputs d1, d2, d3 and d4 of the decoding circuit 5 supplied with the external input signals IN1 and IN2.
Connected to node B via 3, 14, 15, 16 and NO
It is supplied to the R circuit 2. Further, the node B is a normally-on transistor NMOS23 which uses the gate electrode input as a power source.
Is connected to GND via. These NMOS transistors 13, 14, 15 and 16 have different gate lengths or channel widths and have different current capabilities. The outputs d1, d2, d3, d4 of the decoding circuit 5 are
Depending on the combination of the external input signals IN1 and IN2, one of the output signals is selected to have a high level, and one of the NMOS transistors 13 to 16 to which the high level has been input is selected.

As a result, it becomes possible to arbitrarily select the NMOS transistors having different current capacities by the control from the outside, and, for example, the NMOS transistors can be selected at the time of inspection / evaluation after manufacturing.
By adjusting the transistor, the optimum one-shot pulse width can be obtained, and high speed operation with a low voltage source can be realized.

Incidentally, here, the NMOS transistor 13,
Although the circuit for selecting any one of 14, 15, 16 has been described, the NMOS transistors 13, 14, 15, 16 are selected.
A similar effect can be obtained by arbitrarily setting a plurality of selected states and adjusting the current capability. Further, when the NMOS transistors 13, 14, 15, 16 are arbitrarily set to a plurality of selected states, it is possible to obtain the same effect even if the NMOS transistors 13, 14, 15, 16 have the same current capability. Become.

FIG. 5 is a pulse width control circuit diagram showing a fourth embodiment of the present invention. As shown in FIG. 5, in the present embodiment, the NAND circuit 6 for supplying the negative input pulse IP to one input terminal to determine the pulse width of the one-shot pulse signal OS, and the input pulse IP. A first PMOS which is connected between a delay circuit 3 for delaying for a predetermined time and an output terminal A of the delay circuit 3 and the other input terminal B of the NAND circuit 6 and supplies a GND potential to a gate to perform a normally-on operation. It is connected between the transistor 17 and the other input terminal B of the NAND circuit 6 and the power supply VCC to supply a GND potential to the gate for normally-on operation, and has a current supply capacity smaller than that of the first PMOS transistor 17. Second PMOS transistor 24
And is configured to control the pulse width of the one-shot pulse signal OS by changing the current supply capacity of the first PMOS transistor 17 according to the power supply voltage VCC.

Such a pulse width control circuit is shown in FIG.
The NOR circuit 2 is replaced by the NAND circuit 6,
Further, the NMOS transistors 10 and 20 are replaced with the PMOS transistors 17 and 24, respectively, and the input pulse IP is changed from the positive polarity to the negative polarity, and the operation principle is the same.

FIGS. 6A and 6B are timing charts of various signals at high voltage and low voltage in FIG. 5, respectively. As shown in FIGS. 6A and 6B, the input pulse I
The potentials at points P, A, and B and the polarity of the one-shot pulse OS are only opposite to the polarities shown in FIGS. 2 (a) and 2 (b), and the signal timing and the like are the same. The description is omitted.

[0046]

As described above, the pulse width control circuit of the present invention uses the NOR logic or NAND logic of the path for directly supplying the input pulse and the path for supplying the input pulse through the delay circuit and the normally-on transistor. Take N
Since the path for determining the width of the one-shot pulse can be changed by changing the current capability of the normally-on transistor having the OR circuit or the NAND circuit, the one-shot pulse width during high voltage operation is affected. It is possible to control the one-shot pulse width at the time of low voltage operation and to realize high speed without applying the above.

[Brief description of drawings]

FIG. 1 is a pulse width control circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of various signals at high voltage and low voltage in FIG.

FIG. 3 is a pulse width control circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a pulse width control circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a pulse width control circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a timing chart of various signals at high voltage and low voltage in FIG.

FIG. 7 is a diagram showing a conventional pulse width control circuit and its operation timing.

FIG. 8 is a pulse width control circuit diagram showing another conventional example.

[Explanation of symbols]

1 input pulse signal source 2 NOR circuit 3,4 delay circuit 5 Decoding circuit 6 NAND circuit 10-16, 20-23 NMOS transistors 17,24 PMOS transistor IP input pulse signal OS one-shot pulse signal

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 3/00 H03K 5/00

Claims (7)

(57) [Claims] 1. A NOR for supplying an input pulse to one input end to determine the pulse width of a one-shot pulse signal.
A circuit, a delay circuit for delaying the input pulse for a predetermined time, an output terminal of the delay circuit and the N
A first NMOS transistor connected between the other input terminals of the OR circuit to supply a power supply voltage to the gate to perform a normally-on operation and the other input terminal of the NOR circuit and ground, and a power supply voltage to the gate And a second NMOS transistor having a current supply capacity smaller than that of the first NMOS transistor for supplying a normally-on operation.
A pulse width control circuit for controlling the pulse width of the one-shot pulse signal by changing the current supply capability of a MOS transistor. 2. The rising of the input pulse and the first and second NMOS transistors when the power supply voltage is a high voltage.
When the power supply voltage is low due to the fall of the delay pulse at the node to which the transistor is connected, the path of the signal line that determines the pulse width of the one-shot pulse signal is provided by the rise and fall of the input pulse. The pulse width control circuit according to claim 1, which is changed. 3. The delay circuit, the first NMOS
A circuit including a transistor and the second NMOS transistor is connected in cascade in a plurality of stages, and the output of each stage is
The current supply capacity of each NMOS transistor connected to the input of the OR circuit and connected to the delay circuit of each of the stages is sequentially reduced, and the pulse width of the one-shot pulse signal is determined stepwise according to the power supply voltage. The pulse width control circuit according to claim 1. 4. The pulse width control circuit according to claim 3, wherein the delay circuit of each stage has a delay time arbitrarily set. 5. The first NMOS transistor is formed by connecting in parallel a plurality of NMOS transistors having different current supply capacities, and one NMOS transistor is formed by an external input signal.
The pulse width control circuit according to claim 1, wherein the transistor is arbitrarily selected. 6. A NOR for supplying an input pulse to one input terminal to determine the pulse width of a one-shot pulse signal.
A circuit, a delay circuit for delaying the input pulse for a predetermined time, a decode circuit for expanding a plurality of external inputs different from the input pulse, an output terminal of the delay circuit and the other input terminal of the NOR circuit Connected to a plurality of NMOS transistors for normally-on operation by supplying the expanded output of the decoding circuit to the gate, and the other input terminal of the NOR circuit and the ground, and supplying a power supply voltage to the gate. And a normally-on operation, and another NMOS transistor having a current supply capacity smaller than that of the plurality of NMOS transistors,
A pulse width control circuit for controlling the pulse width of the one-shot pulse signal by changing the current supply capacity by selecting a plurality of arbitrary NMOS transistors in combination by the external input. 7. A NAN for supplying an input pulse to one input end to determine the pulse width of a one-shot pulse signal.
A D circuit, a delay circuit for delaying the input pulse for a predetermined time, and a connection between the output terminal of the delay circuit and the other input terminal of the NAND circuit, and a GN at the gate.
First PMO for supplying normally-on operation by supplying D potential
A second transistor, which is connected between the S transistor and the other input terminal of the NAND circuit and a power supply, supplies a GND potential to the gate to perform a normally-on operation, and has a current supply capacity smaller than that of the first PMOS transistor. Of P
A pulse width control circuit comprising a MOS transistor, wherein the pulse width of the one-shot pulse signal is controlled by changing the current supply capacity of the first PMOS transistor according to the power supply voltage.