KR100331263B1 - Osillator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator of a semiconductor device, which is commonly connected to a gate and a drain of an input terminal, and which detects a rising level of an input signal and controls it to a voltage having a predetermined level. An input signal level controller comprising a second transistor connected in parallel and having a gate and a source connected in common and detecting a falling level of the input signal and controlling the voltage to a predetermined level; and a source and a first transistor of the first transistor of the input signal level controller. An inverter connected to the drain of the two transistors and inverting a signal delaying the input signal by a predetermined delay; and a logic gate for generating a clock signal having a predetermined period with respect to the input signal by logically combining the signal output from the inverter with the input signal Equipped. Therefore, the present invention can adjust the period of the clock signal without using a plurality of inverters, such as the inverter chain of a conventional ring oscillator, and can reduce the power consumption required for this.

Description

Oscillator of Semiconductor Device {OSILLATOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an oscillator of a semiconductor device oscillating with a clock signal having a predetermined period.

In general, the oscillator adjusts the input signal at predetermined periods in the semiconductor device to generate a clock signal or to serve as a filter for controlling the noise of the clock signal.

1 is a block diagram showing a basic structure of a conventional ring oscillator. In general, an oscillator includes a delay unit 10 for delaying an input signal by a predetermined time and a logic for logically combining the output of the delay unit 10 and an input signal. The gate 12 is provided. In this case, the logic gate 12 may use a NAND gate or an exclusive OR gate, and in this configuration, the NAND gate is used.

2A to 2B are circuit diagrams illustrating a ring oscillator using a general inverter chain and an operation timing diagram thereof.

The ring oscillator illustrated in FIG. 2A employs an inverter chain 20 in which a plurality of inverters are arranged in a row as a delay unit to enable clock noise filtering, and a delay signal A output through the inverter chain 20. And a logic gate 22 for negative logic multiplying the input signal IN.

In the ring oscillator having the inverter chain 20, the input signal IN is delayed for a predetermined time through the inverter chain 20, and the delayed signal A and the input signal IN are connected to the logic gate 22. ) Generates a clock signal OUT which becomes a low level only when both signals are high level. Accordingly, the clock signal OUT is delayed for a predetermined time with respect to the input signal IN and has a different period.

However, the oscillator having the above structure has to increase the total oscillator size because the number of inverters in the inverter chain 20 must be increased when the fan out of the output stage is increased. This increases overall power consumption and hassles in designing the size of the inverters that make up the inverter chain to adjust the cycle of the output clock signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide an oscillator for a semiconductor device that oscillates with a clock signal having a predetermined period and has low power consumption by implementing a simple circuit configuration instead of an inverter chain in order to solve the problems of the prior art. have.

1 is a block diagram showing the basic structure of a conventional ring oscillator,

2a to 2b is a circuit diagram showing a ring oscillator using a typical inverter chain and its operation timing diagram,

3 is a circuit diagram showing an oscillator of a semiconductor device according to the present invention;

4 is an operation timing diagram of the oscillator shown in FIG. 3.

* Description of the symbols for the main parts of the drawings *

30: input signal level control unit

32: inverter

34: logic gate

In order to achieve the above object, an apparatus of the present invention is an oscillator oscillating to generate a clock signal of a predetermined period with respect to an input signal. A first transistor controlled by a voltage, and a second transistor connected in parallel to an input terminal with respect to the first transistor, a gate and a source connected in common, and a second transistor configured to detect a falling level of the input signal and control the voltage to a predetermined level. A logic combination of an input signal level control unit, an inverter connected to the source of the first transistor and the drain of the second transistor of the input signal level control unit to invert a signal delayed by a predetermined delay, and a signal and an input signal output through the inverter To generate a clock signal with a predetermined period for the input signal. It is characterized by including the.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an oscillator of a semiconductor device according to the present invention, which is connected in parallel to an input terminal of a first transistor (NMOS1) for detecting a rising level of an input signal and to an input terminal of the first transistor. An input signal level control unit 30 including a second transistor PMOS1 for detecting a falling level, an inverter 32 inverting a predetermined delayed signal B of the input signal level control unit 30, and an inverter 32 The logic gate 34 is configured to generate a clock signal OUT having a predetermined period without a time delay with respect to the input signal IN by negatively multiplying the signal C outputted through the input signal IN.

In this case, the first transistor NMOS1 of the input signal level controller 30 is an NMOS, and the second transistor PMOS1 is a PMOS. In the first transistor NMOS1, a gate and a drain are commonly connected to the input signal IN terminal, and a substrate and a source are commonly connected to the inverter 32. In addition, the second transistor PMOS1 has a device structure in which a gate, a source, and a substrate are commonly connected to an input signal IN terminal.

4 is an operation timing diagram of the oscillator illustrated in FIG. 3.

Referring to this, the present invention implements an optimized delay circuit having an input signal level controller and an inverter instead of an inverter chain having a delay circuit function in a conventional ring oscillator structure that generates a clock signal or serves as a clock noise filter. A desired clock signal can be generated.

First, referring to the input signal level controller 30 newly implemented in the present invention, the first and second transistors NMOS1 and PMOS1 disposed between the input signal IN terminal and the inverter 32 are connected to the inverter 32. Generates a control voltage B that is about the threshold voltage level of the transistors (not shown) constituting the circuit. Accordingly, the input signal level controller 30 of the present invention generates a clock signal OUT for delaying the input signal IN by utilizing the RC delays of the first and second transistors NMOS1 and PMOS1.

More specifically, the input signal level controller 30 turns on the first transistor NMOS1 when the input signal IN is at a high level. Then, since the Vds values, which are the voltages of the drain and the source of the NMOS, are generally the same as the Vgs values of the gate and the source, the voltage value of the Vds at the time of saturation becomes a value limiting the threshold voltage value of the NMOS transistor.

In addition, the present invention increases the threshold voltage of the NMOS by connecting the substrate bias of the first transistor NMOS1 to the input terminal of the inverter 32. Referring to FIG. 4, the signal B applied to the inverter 32 while the input signal IN is at the high level is stepped up to about 2.5V.

Therefore, in order to be limited to the threshold voltage of the transistor constituting the inverter 32, the first transistor NMOS1 of the present invention must determine the threshold voltage magnitude with reference to the following equation.

In this case, Vsb is a substrate bias, Vto is a threshold voltage when Vsb is 0, r is a constant representing a substrate bias effect, and φ _b is a substrate potential.

Therefore, as shown in Equation 1, the first transistor NMOS1 of the present invention can increase the level of the control signal B supplied into the inverter 32 by connecting the substrate bias voltage to the input terminal of the inverter 32. In addition, the control signal B can be adjusted to be limited to the threshold voltage of the transistor in the inverter 32, thereby reducing the overall power consumption. In addition, when the length of the first transistor NMOS1 is increased, it is easy to control the effect on delay.

Meanwhile, the second transistor PMOS1 of the input signal level controller 30 of the present invention operates relative to the first transistor NMOS1 and controls the low level of the input signal IN. That is, while the input signal IN is at the low level, the second transistor PMOS1 is turned on so that a voltage drop of Vds gradually occurs with respect to the substrate bias, so that the level of B, the control signal applied to the input terminal of the inverter 32, is about 0.4. Will fall to V.

Then, the C signal, which is the output of the inverter 32, receives a signal B applied according to the switching of the first or second transistors NMOS1 and PMOS1 and inverts it. That is, the inverter 32 inverts the input signal IN and outputs a signal C which is delayed by a predetermined time, and the output has a full swing signal (0 to 5V) which is a voltage level operable at the logic gate 34. .

The output C of the inverter 32 and the input signal are negatively multiplied through the logic gate 34 to obtain a clock signal OUT according to the present invention.

For reference, in order to adjust the period of the clock signal in the oscillator of the present invention, a capacitor is connected between the input signal level controller 30 and the inverter 32. Alternatively, the lengths of the first and second transistors NMOS1 and PMOS1 are increased / shortened, or the lengths of the MOS transistors constituting the inverter 32 are increased / shortened.

As described above, the present invention does not use a plurality of inverters used in the inverter chain of a conventional ring oscillator, but instead implements the delay circuit of the oscillator as an NMOS and PMOS transistor connected in parallel to the input terminal and one inverter. do. This allows the oscillator of the present invention to simply adjust the clock signal period to match the fan-out without increasing the additional inverter even if the fan-out connected to the output stage is increased, and also implements a simple circuit. As a result, power consumption can also be reduced, providing a low power oscillator.

Claims (3)

An oscillator oscillating to generate a clock signal of a predetermined period with respect to an input signal, A gate and a drain are commonly connected to the input terminal, the first transistor detects a rising level of the input signal and controls the voltage to a predetermined level, and the first transistor is connected in parallel to the input terminal, and a gate and a source are commonly connected. An input signal level control unit comprising a second transistor for detecting a falling level of the input signal and controlling the falling level to a predetermined level of voltage; An inverter connected to a source of a first transistor and a drain of a second transistor of the input signal level controller to invert a signal having a predetermined delay from the input signal; And And a logic gate configured to logically combine a signal output through the inverter and the input signal to generate a clock signal having a predetermined period with respect to the input signal. The oscillator of claim 1, wherein both of the first and second transistors of the input signal level controller have a structure in which a substrate and a source are connected in common. The oscillator of claim 1, wherein a period of a clock signal is controlled by connecting a capacitor between the input signal level controller and an inverter.