JP2002111466A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of preventing an unstable state of the circuit when power is turned on with providing respectively power-on reset circuits for each power source voltage even if two or more inputs from external power sources are in usage. SOLUTION: The integrated circuit comprises two or more power-on reset circuits 11, 12 and 13 equipped to output detected signals with detecting that each power source voltage of the power sources VDD, Vref and VDDQ reach to a predetermined detecting reference level Vth with responding respectively to two or more inputs from external power sources VDD, Vref and VDDQ and an inner circuit settled a timing of reset release by either of each output signal from each reset circuit 11, 12 and 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a power-on reset circuit of a semiconductor integrated circuit having a plurality of external power supply inputs.
It is used for synchronous semiconductor memory devices such as M (static semiconductor memory).

[0002]

2. Description of the Related Art There are cases where a plurality of voltage levels are employed as an external power supply input of an integrated circuit. For example, in order to increase the speed of SRAM products, HSTL (High Level) has been used to reduce the voltage level of the interface and reduce power consumption.
Speed Transceiver Logic) is drawing attention.

[0003] This HSTL corresponds to the normal power supply voltage V of the SRAM.
A reference voltage Vref lower than DD is externally input and used in an input buffer, and a power supply voltage VDDQ for an output buffer lower than the power supply voltage VDD is externally input and used in an output buffer.

The reference voltage Vref serves as a criterion for determining "H" / "L" of an input signal in an input buffer.
The input level can be made as small as Vref ± 0.1 V. In the output buffer, by using the power supply voltage VDDQ, the output signal can be made smaller in amplitude than when using the power supply voltage VDD of the SRAM.

Incidentally, a synchronous SRAM uses many register circuits (latch circuits) and may hold indefinite data when an external power supply is turned on. Or a closed loop condition. To solve these problems,
A power-on reset circuit is provided to ensure the initial state of the entire circuit until the power supply voltage reaches a specified value when the power is turned on.

In this case, an SR using a single external power supply
In the AM product, a power-on reset circuit for the power supply voltage VDD may be provided, but in the SRAM product using a plurality of external power inputs as described above, the normal power supply voltage VDD is used.
Even if a power-on reset circuit is provided only for the power supply circuit, the operation of the other circuits to which the power supply voltages Vref and VDDQ are supplied at power-on is not guaranteed, which may cause a malfunction of the circuit. .

[0007]

As described above, the conventional semiconductor integrated circuit is provided with the power-on reset circuit only for the normal power supply voltage VDD when a plurality of external power supply inputs are used. However, there is a problem that the operation of the circuit supplied with a power supply voltage other than the above is not guaranteed when the power is turned on, which may cause a malfunction of the circuit.

The present invention has been made to solve the above-mentioned problems. Even when a plurality of external power supply inputs are used, by providing power-on reset circuits for each power supply voltage, the circuit state can be changed when the power is turned on. An object of the present invention is to provide a semiconductor integrated circuit that can prevent instability.

[0009]

A first semiconductor integrated circuit according to the present invention is provided corresponding to a plurality of external power supply inputs, respectively.
A plurality of power-on reset circuits each of which detects that the power supply voltage of the external power supply input has reached a predetermined detection reference level and outputs a detection signal; and reset release by any one of the output signals of the power-on reset circuits. And an internal circuit for setting the timing.

Here, a logic circuit which generates a reset signal by calculating a logical product of the output signals of the power-on reset circuits and supplies the reset signal to the internal circuit may be further provided.

The second semiconductor integrated circuit of the present invention has a plurality of different values as the detection reference levels of the power supply voltage of the external power supply input, and when the power supply voltage of the external power supply sequentially reaches the plurality of detection reference levels. And a power-on reset circuit for generating a detection signal and outputting at least a first reset signal, and a logical product of at least two of a plurality of detection signals of the power-on reset circuit to obtain a second signal. A logic circuit that outputs a reset signal; and an internal circuit to which the first reset signal is partially supplied and the second reset signal is supplied to another part.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a part of a synchronous SRAM using a plurality of external power supply inputs according to a first embodiment of the present invention.

This synchronous SRAM employs the HSTL described above, and includes a memory circuit, a register circuit (latch circuit).
Normal power supply voltage VDD used in the internal circuit 1 such as
A lower reference voltage Vref for the input buffer 2 and a lower power supply voltage VDDQ for the output buffer 3 are externally supplied as power supply inputs.

Then, three external power supply inputs VDD, Vref
, VDDQ correspond to a predetermined detection reference level (power-on state), and three power-on reset circuits 11, 12, and 13 are provided. The reset release timing of the internal circuit is set by one of the detection signals of the power-on reset circuits 11, 12, and 13.

In this embodiment, each detection signal is ANDed by a logic circuit 16 comprising a three-input NAND circuit 14 and an inverter circuit 15, and the output signal of this logic circuit 16 is used to reset the entire SRAM circuit (not shown). It is used as a reset signal for setting a state, and a reset release timing is set by a signal of the latest detected power-on state among the three external power supply inputs.

In a synchronous SRAM, the main circuits that must be controlled during a reset state immediately after power-on are a clock circuit and an output buffer. According to the power-on reset circuit unit of this example, the clock circuit is reliably reset, and the register circuit (latch circuit) is opened by the clock signal output from the clock circuit, so that the register circuit can store indefinite information. It is possible to prevent the output buffer 3 from being held, and to surely reset the output buffer 3 so as to suppress the passing current when the power is turned on.

FIG. 2 shows an example of a configuration in which one of the plurality of power-on reset circuits 11, 12, and 13 in FIG. 1 is representatively taken out. An example is shown in FIG.

In FIG. 2, a PMOS transistor QP1 whose gate and drain are connected to each other and a resistance element R are connected in series between a power supply node to which an external power supply input is applied and a ground potential (VSS) node. . The connection node A between the PMOS transistor QP1 and the resistance element R is connected to the input node of the CMOS inverter. This CMOS inverter
PMOS transistor between the power supply node and the ground node
QP2 and NMOS transistor QN are connected in series, and their gates are connected to each other. The output node B of the CMOS inverter is connected to a reset output node C via an inverter circuit 21 using the power supply voltage VDD as an operation power supply.

Here, the operation of the power-on reset circuit having the above configuration will be described with reference to FIG. Immediately after the external power input is turned on, the PMOS transistor QP1 turns on, and a current flows to the resistance element R. At the same time, the PMOS transistor QP2 is also turned on, and the output node B of the CMOS inverter becomes "H",
The reset output node C becomes "L". The reset signal of the reset output node C keeps the state of "L" for a certain time α after the power-on.

Further, as the external power supply voltage rises, the potential of the node A also rises, and the potential of the CMOS inverter increases.
The gate voltage VGS of the NMOS transistor QN is equal to the gate threshold Vth
When it becomes higher, the NMOS transistor QN turns on, the output node B of the CMOS inverter goes "L", and the reset output node C goes "H".

FIG. 4 shows an example of the operating characteristics of each of the three power-on reset circuits in FIG. 1 immediately after the power is turned on. Here, reset times t1, t2, and t3 until the power supply input reaches the specified voltage value (detection reference level) in the three power-on reset circuits are indicated by t1, t2, and t3.

The output signal (reset signal) obtained by calculating the logical product of the output signals of the respective power-on reset circuits by the logic circuit 16 in FIG. 1 is "L" immediately after the power is turned on, and during this "L" state. First, the entire SRAM circuit is reset. When the reset signal becomes "H" after the longest reset time t3 among the reset times t1, t2 and t3,
The reset state of the entire SRAM circuit is released, and the normal operation starts.

According to the power-on reset circuit of this embodiment,
The reset state of the entire circuit is released in accordance with the output timing of the power-on reset circuit 13 having the longest reset time t3 among the three power-on reset circuits 11, 12, and 13 to which different external power supplies are applied. Therefore, even if the register circuit, which is often used in the synchronous SRAM, holds indefinite data when the power is turned on, it is possible to prevent a huge current between the power supplies and the occurrence of a closed loop state.

According to the first embodiment, a power-on reset circuit is provided for each of a plurality of external power supply inputs, and the timing for setting the internal circuit to a reset state using the most appropriate reset output is determined. By making the determination, it is possible to prevent a giant current between the power supplies and the occurrence of a closed loop state when the power is turned on.

In this case, even if there is a variation in the input time of a plurality of external power supply inputs and a time difference (for example, γ in FIG. 4) occurs because the power supply voltage reaches the detection reference level,
When all of the plurality of external power supply inputs reach the detection reference level, the reset state of the internal circuit is released, and the internal circuit can be brought into the normal operation state.

<Second Embodiment> FIG. 5 shows a power-on reset circuit of a synchronous SRAM according to a second embodiment of the present invention.

In the second embodiment, similarly to the first embodiment described above with reference to FIG. 1, a power-on reset circuit is provided for each of the three external power supply inputs VDD, Vref, and VDDQ. Although provided, the difference is that some of these power-on reset circuits have a plurality of different detection reference levels.

FIG. 5 shows an example of a configuration in which one of a plurality of power-on reset circuits used in the second embodiment is typically taken out.

This power-on reset circuit is different from the power-on reset circuit described with reference to FIG.
The connection node A between the transistor QP1 and the resistor R
The input nodes of the CMOS inverters 51, 52 and 53 are connected, and the signal of at least one of the output nodes B1, B2 and B3 of the three CMOS inverters 51, 52 and 53 is inverted. An inverter circuit 54 for outputting as a first reset signal, and the output nodes B1, B2, B
3 is different in that a NAND circuit 55 for obtaining a logical product of signals of at least two nodes and outputting the second reset signal is provided, and the others are the same.

In this case, the plurality of CMOS inverters 51,
52 and 53, the respective NMOS transistors QN1 to QN3
Threshold voltages Vth1, Vth2, Vth (only QN1 and QN2 are shown)
3 are configured differently.

The basic operation of the power-on reset circuit of FIG. 5 is the same as the operation of the power-on reset circuit of FIG. 2 described above with reference to FIG. Are different in that they are sequentially detected at different detection reference levels and at least two reset signals are output at different timings.

A part of the SRAM circuit has a reset release timing suitable for its characteristics.
The reset state is released by two reset signals,
For some other circuits in the SRAM circuit, the reset state is released at an appropriate timing according to the characteristics of the circuit, for example, the reset state is released by another reset signal having a reset release timing suitable for the characteristics. Can be canceled. Therefore, the operation when the reset state of the SRAM circuit is released can be further stabilized.

<Third Embodiment> In the second embodiment, a part of a power-on reset circuit provided for each of a plurality of external power supply inputs as shown in the first embodiment is described. As an example, a power-on reset circuit in which a plurality of external power input detection reference levels are set has been described, but the power-on reset circuit of FIG. 5 is provided as a power-on reset circuit corresponding to a single external power input. Even so, the same effect as described above can be obtained.

[0035]

As described above, according to the semiconductor integrated circuit of the present invention, even when a plurality of external power supply inputs are used, by providing the power-on reset circuits for each power supply voltage, the circuit state does not change when the power is turned on. Stability can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a synchronous SRAM using a plurality of external power supply inputs according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration in which one of a plurality of power-on reset circuits in FIG. 1 is typically taken out.

FIG. 3 is a diagram showing an example of operation characteristics of the power-on reset circuit of FIG. 2;

FIG. 4 is a diagram showing an example of operating characteristics of each of the three power-on reset circuits in FIG. 1 immediately after power is turned on.

FIG. 5 shows a synchronous SRA according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a power-on reset circuit section of M.

[Explanation of symbols]

 1 ... input buffer, 2 ... output buffer, 11 ... power-on reset circuit for external power input VDD, 12 ... power-on reset circuit for external power input Vref, 13 ... power-on reset circuit for external power input VDDQ, 14 ... NAND circuit, 15 ... inverter circuit, 16 ... logic circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B015 HH05 JJ11 KB91 NN03 QQ03 5J055 AX57 AX64 BX41 CX10 CX27 EZ07 FX08 FX19 FX37 GX01 GX02

Claims (6)

[Claims] A plurality of power-on reset circuits are provided corresponding to a plurality of external power supply inputs, respectively, and detect that a power supply voltage of the external power supply input has reached a predetermined detection reference level and generate a detection signal. A semiconductor integrated circuit comprising: a reset release timing set by any one of the detection signals of the plurality of power-on reset circuits. 2. The logic circuit according to claim 1, further comprising a logic circuit that outputs a reset signal by calculating a logical product of the detection signals of the plurality of power-on reset circuits and supplies the reset signal to the internal circuit. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein each of said power-on reset circuits has one detection level for a power supply voltage of an external power supply input. 4. At least one of the plurality of power-on reset circuits has a plurality of different values as detection reference levels of a power supply voltage of an external power supply input, and the power supply voltage of the external power supply input has a plurality of detection reference levels. A detection signal is generated by sequentially detecting a time point at which the levels sequentially reach a level, a first reset signal is output based on at least one detection signal, and a second reset signal is obtained by taking a logical product of at least two detection signals. 2. The semiconductor integrated circuit according to claim 1, wherein 5. A power supply voltage of an external power supply input has a plurality of different detection reference levels, and a time when the power supply voltage of the external power supply sequentially reaches a plurality of detection reference levels is detected, and a detection signal is detected. A power-on reset circuit for generating, a reset for outputting a first reset signal based on at least one detection signal of the power-on reset circuit, and obtaining a logical product of at least two detection signals to output a second reset signal A semiconductor integrated circuit, comprising: a signal output circuit; and an internal circuit to which a part of the first reset signal is supplied and another part of which is supplied with the second reset signal. 6. The semiconductor integrated circuit receives a normal power supply voltage as a first external power supply, a reference voltage lower than the normal power supply voltage as a second external power supply, and outputs a third external power supply.
A semiconductor which receives a power supply voltage for an output buffer lower than the normal power supply voltage as an external power supply, uses the second external power supply input as an input buffer, and uses the third external power supply input as an output buffer The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a storage device.