JP2020165848A - Latch array circuit and semiconductor integrated circuit - Google Patents

Abstract

To provide a latch array circuit with which it is possible to prevent the occurrence of a period in which the output of a storage element is indefinite.SOLUTION: The present invention comprises: a plurality of latch circuits arranged in matrix form; a clock control unit for fixing the logic value of respective clock input for each row or each column of the plurality of match circuits, on the basis of a first timing signal the state of which transitions at a first timing that is synchronized to the rising edge of a power-on reset signal, till the first timing; and a data supply unit for fixing the respective data input to a prescribed value for each row or each column of the plurality of latch circuits on the basis of a second timing signal the state of which transitions at a second timing that is slower than the first timing.SELECTED DRAWING: Figure 1

Description

The present invention relates to latch array circuits and semiconductor integrated circuits.

In a system that outputs data from a plurality of blocks using a common bus, a circuit is provided to prevent a logical collision of the bus due to the simultaneous output of data from the plurality of blocks. This circuit takes in, for example, a buffer that outputs data to the bus (for example, a tristate buffer), a control circuit that outputs a control signal for controlling the buffer, and a control signal output from the control circuit and supplies the buffer. It is composed of a plurality of flip-flops as storage elements.

In such a circuit, when the power of the system is turned on, the output of the flip-flop may be indefinite because the flip-flop is before the control signal from the control circuit is taken in. Therefore, a flip-flop with a reset terminal is used as the flip-flop, and a power-on reset signal is input to each reset terminal when the power is turned on. By inputting the power-on reset signal to the power-on reset terminal, the output of the flip-flop is fixed to a predetermined value.

When a flip-flop with a reset terminal is used, the circuit scale and the occupied area of the chip are large because each flip-flop must have a built-in reset function. Therefore, in order to reduce the chip area, a circuit is configured by using a flip-flop having no reset terminal instead of a flip-flop having a reset terminal. In this circuit, a reset clock generation circuit that generates a reset clock signal is provided, and a reset clock signal is input to the clock terminal of a flip-flop that does not have a reset terminal immediately after the power is turned on, so that the flip-flop is flip-flop before normal operation starts. Has taken in a control signal (for example, Patent Document 1).

Japanese Patent No. 3368815

However, since the power-on reset signal and the reset clock signal supplied to the flip-flop as in the prior art rise up reflecting the rise of the power supply voltage, they have to rise to some extent later than the rise of the power supply voltage. Therefore, the output value of the flip-flop is indefinite until the power-on reset signal or the reset clock signal rises. Therefore, the period during which the internal circuit is not reset (initialized) cannot be completely eliminated.

Depending on the type of internal circuit, the existence of such an uninitialized period becomes a serious problem. For example, semiconductor integrated circuits and electronic devices often have built-in test functions that are supposed to be used only by designers, manufacturers, and product suppliers, in addition to the normal functions that are open to users. The test function is installed for the purpose of facilitating analysis when a defect occurs, grasping the operating limit, and sorting out manufacturing defects before shipping the product. As circuits become larger, more multifunctional, and more complex, test functions tend to become more diverse. For this reason, in a semiconductor integrated circuit having a built-in test function, a test mode latch circuit including a storage element group for centrally switching and holding information for setting or canceling the test function and its control circuit is provided as an internal circuit. In many cases.

Further, the large-scale semiconductor integrated circuit has a built-in power supply circuit that generates an internal power supply potential based on the external power supply potential and supplies it to an internal circuit such as a test mode latch circuit. In order to analyze internal circuit defects, grasp operating limits, and sort out manufacturing defects before shipping, the causes derived from the built-in power supply circuit and the causes derived from the internal circuit itself should be determined for such a configuration. A separable test method is essential. In order to realize such a test method, for example, a function of enabling a pseudo internal power supply potential to be separately supplied from the outside in parallel with a normal external power supply potential and a function of forcibly stopping the built-in power supply circuit are tested. It is conceivable to install it in advance. These test functions are supplied and held by the internal power supply potential provided by a dedicated latch provided in the test mode latch circuit, and the power-on reset signal ensures initialization so that unintended test functions are not activated when the power is turned on. Need to be reset.

However, as in the above-mentioned conventional technique, the output value of the flip-flop is indefinite until the power-on reset signal or the reset clock signal rises, and the test mode latch circuit cannot be initialized. Therefore, the test mode forcibly stops the power supply circuit. It is also uncertain whether or not it will be. If the test mode is mistakenly set, the internal power supply potential will not rise when the power supply circuit is stopped, unlike the original operation in which a power-on reset signal is generated based on the rise in the internal power supply potential. The power-on reset signal is not generated forever, and normal operation cannot be started.

Such a power-on reset failure at power-on can occur regardless of whether the test function is used, before or after the product is shipped, and the test mode latch circuit. Depends on whether "H" level is output or "L" level is output by chance, so it appears as an irregular and irreproducible troublesome defect.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a latch array circuit that can prevent the occurrence of a period in which the output of a storage element is indefinite.

The latch array circuit according to the present invention is based on a plurality of latch circuits arranged in a matrix and a first timing signal that transitions at the first timing synchronized with the rise of the power-on reset signal, up to the first timing. During the period, a clock control unit that fixes the logical value of each clock input for each row or column of the plurality of latch circuits, and a second timing signal that transitions at a second timing later than the first timing. Based on this, it is characterized by having a data supply unit that fixes each data input to a predetermined value for each row or column of the plurality of latch circuits.

According to the latch array circuit of the present invention, it is possible to avoid a state in which the output of the storage element becomes indefinite before the power-on reset signal rises.

It is a block diagram which shows the structure of the latch array circuit of Example 1. FIG. It is a block diagram which shows the structural example of the power-on reset circuit used together with the latch array circuit of Examples 1 to 3. It is a waveform diagram of Examples 1 to 3 which shows the internal power potential at the time of power-on and the rise of the input potential VRC shown in FIG. It is a waveform diagram of Examples 1 to 3 which shows the operation of the power-on reset circuit at the time of power-on. It is a waveform diagram of Examples 1 to 3 which shows the operation of the latch array circuit of this Example at the time of power-on. It is a waveform diagram of Examples 1 to 3 which shows the operation of the latch array circuit of this Example at the time of power-on. It is a block diagram which shows the structure of the latch array circuit of Example 2. It is a block diagram which shows the structural example of the power-on reset circuit of Example 2. It is a block diagram which shows the structure of the latch array circuit of Example 3. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail. In the description and the accompanying drawings in each of the following examples, substantially the same or equivalent parts are designated by the same reference numerals.

FIG. 1 is a block diagram showing a configuration of the latch array circuit 100 of this embodiment. The latch array circuit 100 is mounted on an IC chip. The latch array circuit 100 includes a plurality of latch circuits L00, L01, ..., L0n, L10, L11, ..., L1n, ..., Lm0 arranged in a matrix of (m + 1) rows × (n + 1) columns. , Lm1, ..., Lmn (hereinafter, these are also collectively referred to as latch circuits L00 to Lmn).

Each of the latch circuits L00 to Lmn is a transparent type D latch circuit having no reset terminal. That is, each of the latch circuits L00 to Lmn of the input signal input to the data input terminal D during the period when the clock signal input to the clock terminal CK is at the "H" level (that is, the logical value "1"). The output data reflecting the value is output from the output terminal Q. On the other hand, in each of the latch circuits L00 to Lmn, during the period when the clock signal is at the “L” level (that is, the logical value “0”), regardless of the value of the input signal input to the data input terminal D, the conventional latch circuits L00 to Lmn The output data holding the value is continuously output from the output terminal Q.

Further, the latch array circuit 100 includes a delay circuit DLY. The delay circuit DLY receives the input of the inversion start power-on reset signal PORB and outputs the inversion late power-on reset signal POR2B that delays the input. The inverting start power-on reset signal PORB is supplied from a power-on reset circuit provided outside the latch array circuit 100.

Further, the latch array circuit 100 includes (m + 1) AND gate circuits AN0, AN1, ..., ANm provided corresponding to each of the (m + 1) rows of the plurality of latch circuits. Each of the AND gate circuits AN0, AN1, ..., ANm is a 2-input AND circuit. The AND gate circuits AN0, AN1, ..., ANm constitute an input data supply unit 11 that supplies internal input data signals D0 to Dm to the latch circuits L00 to Lmn.

External input data signals DI <0>, DI <1>, ..., DI <m> are input to one of the input terminals of the AND gate circuits AN0, AN1, ..., ANm, respectively. A power-on reset signal POR2B after inverting is commonly input to the other of the input ends of the AND gate circuits AN0, AN1, ..., ANm. The AND gate circuit AN0 outputs a signal of the logical product of the external input data signal DI <0> and the reverse power-on reset signal POR2B as the internal input data signal D0. Similarly, the AND gate circuits AN1 to ANm output a signal of the logical product of the external input data signals DI <1> to DI <m> and the reverse power-on reset signal POR2B as internal input data signals D1 to Dm.

The internal input data signal D0, which is the output signal of the AND gate circuit AN0, is input to each data input terminal D of the latch circuits L00 to L0n arranged in the first line of the latch circuits L00 to Lmn. Similarly, internal input data signals D1 to Dm common to each row are connected to the data input terminals D of the latch circuits L10 to L1n, ..., Lm0 to Lmn arranged in the 2nd to (m + 1) rows. Entered.

Further, the latch array circuit 100 includes an inverter INV0. The inverter INV0 receives the input of the inverted starting power-on reset signal PORB and outputs the inverted starting power-on reset signal POR1.

Further, the latch array circuit 100 includes (n + 1) OR gate circuits OR0, OR1, ..., ORn provided corresponding to each of the (n + 1) rows of the plurality of latch circuits. Each of the OR gate circuits OR0, OR1, ..., ORn is a 2-input OR circuit. The OR gate circuits OR0, OR1, ..., ORn form a clock supply unit 12 that supplies the internal clock signals CK0 to CKn to the latch circuits L00 to Lmn.

External clock signals CKI <0>, CKI <1>, ..., CKI <n> are input to one of the input terminals of the OR gate circuits OR0, OR1, ..., ORn, respectively. The starting power-on reset signal POR1 is commonly input to the other of the input ends of the OR gate circuits OR0, OR1, ..., ORn. The external clock signals CKI <0>, CKI <1>, ..., CKI <n> supplied to the latch array circuit 100 in this embodiment may be pulse-shaped clock signals having a narrow width.

The OR gate circuit OR0 outputs a signal of the logical sum of the external clock signal CKI <0> and the starting power-on reset signal POR1 as the internal clock signal CK0. Similarly, the OR gate circuits OR1, ..., ORn output a signal of the logical sum of the external clock signals CKI <1> to CKI <n> and the starting power-on reset signal POR1 as internal clock signals CK1 to CKn. .. Since the external clock signals CKI <0>, CKI <1>, ..., CKI <n> are pulse-shaped clock signals, the internal clock signals CK0, CK1, ... CKn are also pulse-shaped. It may be a clock signal of.

An internal clock signal CK0, which is an output signal of the OR gate circuit OR0, is input to each clock terminal CK of the latch circuits L00 to Lm0 arranged in the first row of the latch circuits L00 to Lmn. Similarly, internal clock signals CK1 to CKn common to each column are input to the clock terminals CK of the latch circuits L01 to Lm1, ..., L0n to Lmn arranged in the 2nd to (n + 1) columns. To. The latch circuits L00 to Lmn are configured as pulse latch circuits that operate by receiving pulse-shaped internal clock signals CK0, CK1, ..., CKn.

The latch circuit L00 outputs an output signal Q00 from the output terminal Q. Similarly, the latch circuits L01 to Lmn output output signals Q01 to Qmn, respectively. The output signal from each of the latch circuits L00 to Lmn is a value that reflects the value of the internal input data signal input to the clock terminal D during the period when the internal clock signal input to the clock terminal CK is at the “H” level. During the period when the internal clock signal is at the "L" level, the value retains the previous value.

FIG. 2 is a circuit diagram showing a configuration example of a first power-on reset circuit PRC1 that generates an inversion start power-on reset signal PORB. The first power-on reset circuit PRC1 is provided inside the IC chip and outside the latch array circuit 100. The first power-on reset circuit PRC1 receives the supply of the internal power supply potential Vdd from the internal power supply circuit (not shown) provided inside the IC chip, and receives the internal power-on reset signal POR and the inversion start power-on reset signal PORB. To generate. The first power-on reset circuit PRC1 is composed of, for example, a resistance element R1, a capacitance element C1, an inverter INV1 and an inverter INV2.

The resistance element R1 and the capacitance element C1 are connected in series between a node to which the internal power supply potential Vdd is applied and a grounding node. That is, the internal power supply potential Vdd is supplied to one end of the resistance element R1, the ground potential is supplied to one end of the capacitance element C1, and the other ends of the resistance element R1 and the capacitance element C1 are connected to each other.

The input end of the inverter INV1 is connected to the connection node of the resistance element R1 and the capacitance element C1. The inverter INV1 outputs a signal obtained by inverting the input potential VRC, which is the potential of the connection node, as an internal power-on reset signal POR.

The input end of the inverter INV2 is connected to the output end of the inverter INV1. The inverter INV2 outputs an inverted starting power-on reset signal PORB in which the internal power-on reset signal POR is inverted.

FIG. 3A is a waveform diagram showing time changes of the internal power potential Vdd and the input potential VRC when the power of the first power-on reset circuit PRC1 is turned on. FIG. 3B is a waveform diagram showing the time change of the internal power-on reset signal POR and the inversion start power-on reset signal PORB at that time.

First, when the power of an external power supply (not shown) provided outside the IC chip is turned on, the internal power supply potential Vdd starts to rise a little after the external power supply potential starts to rise. Here, the time when the internal power supply potential Vdd starts to rise is shown as the time t0. At this time, due to the presence of the resistance element R1 and the capacitance element C1, the input potential VRC rises further later than the internal power supply potential Vdd.

Assuming that the time when the internal power potential Vdd reaches the logical threshold value VTH of the inverter INV1 is time t1, the input potential VRC has not yet reached the logical threshold value VTH at time t1. Therefore, the inverter INV1 outputs an “H” level internal power-on reset signal POR. The value of this "H" level continues to rise as the internal power potential Vdd rises.

Assuming that the time when the input potential VRC reaches the logical threshold value VTH of the inverter INV1 is time t2, the inverter INV1 outputs an internal power-on reset signal POR of “L” level after time t2. The period from time t1 to time t2 is the power reset period TRST.

The inversion start power-on reset signal PORB is a signal obtained by inverting the internal power-on reset signal POR, and becomes an "L" level until time t2 and an "H" level after time t2. Since the internal power supply potential Vdd is still rising at around time t2, the inversion start power-on reset signal PORB rises as the internal power supply potential Vdd rises. Then, as the internal power supply potential Vdd reaches a predetermined saturation potential, the potential of the inversion start power-on reset signal PORB also becomes constant.

The potential of the internal power-on reset signal POR is unstable while the internal power supply potential Vdd is low, but is substantially the same as the internal power supply potential Vdd, and the input of the inverter INV2 is at the “H” level. Therefore, there is no factor that the current from the internal power supply potential Vdd consistently flows into the output end of the inverter INV2. Therefore, the inversion start power-on reset signal PORB is maintained at the ground potential level relatively early and stably. At least, the inversion start power-on reset signal PORB is surely kept at the "L" level even during an unstable period during which the internal power potential Vdd is rising.

Next, the operation of the latch array circuit 100 of this embodiment will be described with reference to FIGS. 4A and 4B.

FIG. 4A is a waveform diagram showing time changes of the starting power-on reset signal POR1 and the inverting late power-on reset signal POR2B. Here, the starting power-on reset signal POR1 is shown by a solid line, and the inverted late power-on reset signal POR2B is shown by a dashed-dotted line.

The starting power-on reset signal POR1 is a signal output by the inverter INV0 by inverting the inverted starting power-on reset signal PORB, and is a signal obtained by inverting the internal power-on reset signal POR twice. Therefore, the signal waveform of the starting power-on reset signal POR1 is substantially the same as the signal waveform of the internal power-on reset signal POR shown in FIG. 3B. However, since the starting power-on reset signal POR1 is output via the inverter INV2 of the first power-on reset circuit PRC1 and the inverter INV0 of the latch array circuit 100, the signal level starts from the "H" level slightly later than the time t2. Transition to the "L" level.

The inverting late power-on reset signal POR2B is a signal obtained by delaying the inverting early power-on reset signal PORB by the delay circuit DLY. Therefore, the signal waveform of the inverted late power-on reset signal POR2B translates the signal waveform of the inverted early power-on reset signal PORB shown in FIG. 3B to the positive side in the time axis direction (that is, the right side of the paper surface in FIG. 3B). It becomes the waveform that was made. In FIG. 4A, the amount of delay due to the delay circuit DLY is shown as "Tdeli".

In this embodiment, the time t3 at which the power-on reset signal POR2B after inversion rises from the “L” level to the “H” level is delayed so as to be the time after the internal power potential Vdd finishes rising and becomes saturated. The amount Tdeli is set. Therefore, unlike the inversion start power-on reset signal PORB shown in FIG. 3B, the inversion late power-on reset signal POR2B shown in FIG. 4A does not have a period in which it rises together with the internal power supply potential Vdd.

FIG. 4B is a waveform diagram showing time changes of the internal clock signals CK0, CK1, ..., CKn, the internal input data signals D0, D1, ..., Dm, and the output signals Q00, Q01, ..., Qmn. Is. Here, the internal clock signals CK0, CK1, ... CKn are indicated by solid lines, the internal input data signals D0, D1, ..., Dm are indicated by alternate long and short dash lines, and the output signals Q00, Q01, ..., Qmn are indicated by dotted lines. There is.

The internal clock signals CK0, CK1, ..., CKn have the starting power-on reset signal POR1 and the external clock signals CKI <0>, CKI at the pair of input terminals of the OR gate circuits OR0, OR1, ..., ORn. It corresponds to the output signal when <1>, ..., CKI <n> are input respectively. Therefore, during the period when the potential of the starting power-on reset signal POR1 is near the internal power supply potential Vdd (that is, the period on the left side of the drawing), the internal clock signals CK0, CK1, ..., CKn are uniformly set to the "H" level. Become.

On the other hand, in the period after the starting power-on reset signal POR1 transitions to the “L” level (that is, the period on the right side of the drawing), the internal clock signal which is the output of the OR gate circuits OR0, OR1, ..., ORn. CK0, CK1, ..., CKn have the same logic level as the external clock signals CKI <0>, CKI <1>, ..., CKI <n>.

FIG. 4B shows signal waveforms when it is assumed that the external clock signals CKI <0>, CKI <1>, ..., CKI <n> are all at the “L” level. In this case, the internal clock signals CK0, CK1, ..., CKn are signal waveforms that uniformly transition to the “L” level following the falling edge of the starting power-on reset signal POR1.

The internal input data signals D0, D1, ..., Dm have an inverted late power-on reset signal POR2B and an external input data signal DI <0 at the pair of input ends of the AND gate circuits AN0, AN1, ..., ANm. >, DI <1>, ..., DI <m>, respectively, correspond to the output signals when they are input. Therefore, during the period when the potential of the power-on reset signal POR2B after inversion is near the ground potential (that is, the period before the time t3), the internal input data signals D0, D1, ..., Dm are uniformly "L". Become a level.

On the other hand, in the period after the reverse power-on reset signal POR2B transitions to the “H” level near time t3, the AND gate circuits AN0, AN1, ..., The internal input data signal D0, which is the output of ANm, The signal levels of D1, ..., Dm are the same logic levels as the external input data signals DI <0>, DI <1>, ..., DI <m>.

FIG. 4B shows a signal waveform when it is assumed that the external input data signals DI <0>, DI <1>, ..., DI <m> are all at the “H” level. In this case, the internal input data signals D0, D1, ..., Dm are signal waveforms that uniformly transition to the "H" level following the rise of the power-on reset signal POR2B after inversion. If the external input data signals DI <0>, DI <1>, ..., DI <m> include "L" level signals, the corresponding internal input data signals are ". Since it is maintained at the L "level, the signal waveform becomes a signal waveform that sticks to the vicinity of the ground potential and never rises.

The output signals Q00, Q01, ..., Qmn correspond to the output signals of the latch circuits L00, L01, ..., Lmn, which are latch circuits without a reset terminal. Therefore, during the period when the internal clock signals CK0, CK1, ..., CKn are uniformly at the "H" level (that is, the period on the left side of the drawing), the values of the internal input data signals D0, D1, ..., Dm are It is reflected as an output value as it is. As described above, since the internal input data signals D0, D1, ..., Dm are uniformly at the "L" level in the period, as a result, the output signals Q00, Q01, ..., Qmn in the period are uniformly. It becomes "L" level.

On the other hand, in the period after the internal clock signals CK0, CK1, ... CKn uniformly transition to the "L" level (that is, the period on the right side of the drawing), the internal input data signals D0, D1, ... , Even if Dm transitions to the “H” level, the output signals Q00, Q01, ..., Qmn continue to hold the values immediately before that. Therefore, during the period, the output signals Q00, Q01, ..., Qmn are uniformly set to the "L" level.

It should be noted that the time when the internal clock signals CK0, CK1, ..., CKn transition to the "L" level and the time when the internal input data signals D0, D1, ..., Dm transition to the "H" level are almost the same. At the same time, the internal clock signals CK0, CK1, ..., CKn and the internal input data signals D0, D1, ..., Dm are all "H" for a very short period of time due to IC chip manufacturing variations and noise. There is a possibility of becoming a level. During that period, the "H" levels of the internal input data signals D0, D1, ..., Dm can be taken into the latch circuits L00, L01, ..., Lmn, so that the output signals Q00, Q01, ..., A malfunction can occur in which Qmn transitions to the "H" level.

To prevent this, the reverse power-on reset signal POR2B must be reliably maintained at the “L” level until the starter power-on reset signal POR1 has transitioned to the “L” level. The delay circuit DLY of this embodiment is provided for this purpose. That is, the delay circuit DLY delays the inverting first power-on reset signal PORB by a period corresponding to "Tdeli" in FIG. 4A to generate the inverting late power-on reset signal POR2B, so that the first power-on reset signal POR1 becomes ". Until the transition to the L "level is completed, one of the signals supplied to the AND gate circuits AN0, AN1, ..., ANm (that is, the power-on reset signal POR2B after inverting) is surely set to the "L" level. It will be possible to maintain.

With the above configuration, in the latch array circuit 100 of the present embodiment, the output signals Q00, Q01, ..., Qmn of all the latch circuits can be initialized to the "L" level immediately after the power is turned on.

After the time t3, the operation of the first power-on reset circuit PRC1 shown in FIG. 2 at power-on is completed. Therefore, during the subsequent period, the starting power-on reset signal POR1 is at the “L” level and is inverted. The late power-on reset signal POR2B is fixed at the "H" level. Therefore, the internal clock signals CK0, CK1, ..., CKn always have values that directly reflect the external clock signals CKI <0>, CKI <1>, ..., CKI <n> during the period. Further, the internal input data signals D0, D1, ..., Dm are always values that directly reflect the external input data signals DI <0>, DI <1>, ..., DI <m> during the period. ..

As a result, during normal operation, the values to be written to the latch array circuit 100 are input in advance as the external input data signals DI <0>, DI <1>, ..., DI <m>, and then the external clock signal CKI <0>. , CKI <1>, ..., CKI <n> by fixing any one to the "H" level for a short period of time (ie, pulsed) and the rest to the "L" level. Writing can be performed all at once to the latch circuit group of the column corresponding to the "H" level external clock signal (that is, the latch circuit group to receive the supply of the internal clock signal corresponding to the external clock signal).

For example, by setting the external clock signals CKI <1>, ..., CKI <n> to the "L" level and setting the external clock signal CKI <0> to the "H" level for a short period of time, the external input data signal DI The data values input as <0>, DI <1>, ..., DI <m> are written to the latch circuits L00, L10, ..., Lm0 (that is, the latch circuit group in the first row) all at once. , Output signals Q00, Q10, ..., Qm0.

As described above, also in the latch array circuit 100 of this embodiment, the normal operation of the general latch array circuit can be realized. The reason why one of the external clock signals CKI <0>, ..., CKI <n> is set to the "H" level for a short period of time is that the external input data signal DI is set so that the output signal does not change erroneously. This is to allow a timing margin so that the period during which <0>, DI <1>, ..., DI <m> must be controlled can be shortened.

As described above, according to the latch array circuit 100 of this embodiment, it is possible to avoid a state in which the output signal becomes an indefinite value in the period before the internal power-on reset signal POR rises immediately after the power is turned on. Become. This makes it possible to safely initialize the storage element when the power is turned on, even in applications where the output of an indefinite value is particularly problematic.
For example, in the test mode, the internal power supply circuit in the IC chip is forcibly stopped and a pseudo internal power supply potential is separately supplied from the outside. However, the control of the test function for forcibly stopping the internal power supply circuit is performed. As described above, it is possible to safely initialize the storage element when the power is turned on, even for an internal circuit whose application is such that even a short-term output of an indefinite value is unacceptable.

In the latch array circuit 100 of this embodiment, instead of the initialization triggered by the signal transition like the clock input of the flip-flop, it is immediately initialized by the input of the logical value as in the input of the reset signal to the flip-flop with reset. Can be reset.

Further, since the flip-flop with reset and the latch with reset have a relatively large occupied area, the chip area is large and the cost tends to be high, especially in the application of handling a large amount of stored data. On the other hand, in the latch array circuit 100 of the present embodiment, the reset function is not individually built in each storage element as in these circuits, but as shown in FIG. 1, the AND gate circuit AN0, AN1, ..., ANm and OR gate circuits OR0, OR1, ..., ORn are shared among a plurality of latches. Then, in the latch array circuit 100 of this embodiment, as shown in FIG. 1, the internal input data input signals of the latch circuits arranged in the row direction (the horizontal direction on the paper surface in FIG. 1) are common. Further, the internal clock signals of the latch circuits arranged in the row direction (vertical direction on the paper in FIG. 1) are common. Therefore, since the number of signal wirings and the number of drivers for driving the signals can be reduced, the occupied area can be kept small.

Further, the latch array circuit 100 of this embodiment has a configuration and operation that can be easily used in combination with a so-called "pulse dratch technique" in which a latch circuit is operated by using a pulse type clock, and has a smaller occupied area than a flip-flop and a flip-flop. It is possible to realize a timing margin close to that of a flip-flop. Therefore, according to the latch array circuit 100 of this embodiment, it is possible to reduce the occupied area and secure the timing margin at the same time.

Further, in the latch array circuit 100 of this embodiment, even if the circuit has a great influence on the entire internal circuit such as the control of the test function for forcibly stopping the internal power supply circuit, it is built in the internal circuit itself. be able to. Therefore, in a general semiconductor integrated circuit in which the internal power supply potential is lower than the external power supply potential, it is possible to configure the circuit used only in such a test mode with only low withstand voltage elements, thus reducing the chip area. Can contribute.

Next, Example 2 of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the latch array circuit 200 of the second embodiment. The latch array circuit 200 of the present embodiment is different from the latch array circuit 100 of the first embodiment in that it does not have the delay circuit DLY shown in FIG. Other configurations are common to the latch array circuit 100 of the first embodiment.

In this embodiment, the power-on reset signal POR2B after inverting is supplied from the outside of the latch array circuit 200 and the inside of the IC chip. Specifically, in the IC chip of this embodiment, in addition to the first power-on reset circuit that generates the inversion start power-on reset signal PORB as shown in FIG. 2, the inversion late power-on reset signal POR2B is generated. A second power-on reset circuit is provided.

FIG. 6 is a circuit diagram showing the configuration of the second power-on reset circuit PRC2. The second power-on reset circuit PRC2 receives the supply of the internal power supply potential Vdd from the internal power supply circuit (not shown) provided inside the IC chip, and receives the late power-on reset signal POR2 and the reverse late power-on reset signal POR2B. To generate.

The second power-on reset circuit PRC2 uses the resistance element R1 of the first power-on reset circuit PRC1 shown in FIG. 2 as the resistance element R2, the capacitance element C1 as the capacitance element C2, the inverter INV1 as the inverter INV3, and the inverter INV2. Is replaced with an inverter INV4, respectively. The resistance element R2 has a resistance value larger than that of the resistance element R1. Further, the capacitance element C2 has a larger capacitance value than the capacitance element C1.

According to such a configuration, the increase in the potential immediately after the power of the input potential VRC2 (that is, the input potential of the inverter INV3), which is the potential of the connection node between the resistance element R2 and the capacitance element C2, is the input potential of FIG. It is slower than the rise in VRC potential.

As a result, the time when the input potential VRC2 reaches the logical threshold value VTH of the inverter INV3 (that is, the time corresponding to the time t2 in FIG. 3A) is delayed, so that the rise of the output signal of the inverter INV4 is also delayed. In this embodiment, this output signal becomes the power-on reset signal POR2B after inversion.

According to the second power-on reset circuit PRC2 of this embodiment, by setting the resistance value of the resistance element R2 and the capacitance value of the capacitance element C2 to appropriate values, the delay difference shown as “Tdelay” in FIG. 4A can be obtained. A corresponding delay difference can be stably generated after the internal power supply potential Vdd has risen to some extent.

The second power-on reset circuit PRC2 supplies the reverse power-on reset signal POR2B to the AND gate circuits AN0, AN1, ..., ANm of the latch array circuit 200 of FIG. The inverting start power-on reset signal PORB is supplied to the inverter INV0 of the latch array circuit 200 from the first power-on reset circuit PRC1 shown in FIG. The operation of each part of the latch array circuit 200 of this embodiment is the same as the operation of the parts other than the delay circuit DLY of the latch array circuit 100 of the first embodiment.

As described above, according to the present embodiment, the delay circuit DLY can be omitted from the latch array circuit 200, so that the area can be further reduced as compared with the latch array circuit 100 of the first embodiment.

Further, when a plurality of power-on reset circuits are originally used together corresponding to a plurality of internal power supply potentials, the output can be diverted to generate the late power-on reset signal POR2B after inverting. It is not necessary to provide a delay circuit DLY, and the chip area can be reduced.

Next, Example 3 of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the latch array circuit 300 of the third embodiment. The latch array circuit 300 of the present embodiment has an OR gate circuit OR00 instead of the AND gate circuit AN0 shown in FIG. 1, and has a new inverter INV5 and its output signal POR2. Different from.

The inverter INV5 takes the inverting late power-on reset signal POR2B, which is the output signal of the delay circuit DLY, as an input, and outputs the inverting late power-on reset signal POR2 which is further inverted.

An external input data signal DI <0> is input to one of the input ends of the OR gate circuit OR00. A late power-on reset signal POR2 is input to the other end of the input end of the OR gate circuit OR00. The OR gate circuit OR00 outputs a signal of the logical sum of the external input data signal DI <0> and the subsequent power-on reset signal POR2 as the internal input data signal D0. The output internal input data signal D0 is input to the data input terminals D of the latch circuits L00, L01, ..., L0n, which are the latch circuits of the first line.

The OR gate circuit OR00, together with the AND gate circuits AN1 to ANm, constitutes an input data supply unit 31 that supplies internal input data to the latch circuits L00 to Lmn.

Next, the operation of the latch array circuit 300 of this embodiment will be described. Since the late power-on reset signal POR2 is a signal obtained by inverting the inverted late power-on reset signal POR2B, the potential follows the internal power supply potential Vdd after the time t0 (see FIG. 3A) when the internal power supply Vdd starts to rise. To rise. Then, the late power-on reset signal POR2 is reversed near the time t3 (see FIG. 4A) when the late power-on reset signal POR2B rises from the “L” level to the “H” level, and is fixed to the ground potential thereafter. ..

The internal input data signal D0 corresponds to the output of the OR gate circuit OR00, one of which is the late power-on reset signal POR2. Therefore, the potential of the internal input data signal D0 also rises following the internal power supply potential Vdd after the time t0, and is maintained at the “H” level until the time t3.

The latch circuits L00, L01, ..., L0n, which are the latch circuits on the first line, are commonly connected to the data terminal D while the signal (clock input) input to the clock terminal CK is at the "H" level. Continues to capture the value of the input internal input data signal D0. Therefore, among the output signals Q00, Q01, ..., Qmn, only the output signals Q00, Q01, ..., Q0n, which are the output signals of the latch circuits L00, L01, ..., L0n, are internal input data signals. Immediately reflecting the value of D0, it rises with the internal power supply potential Vdd and becomes the "H" level.

As described above, according to the configuration of the latch array circuit 300 of this embodiment, the output signals Q00, Q01, ..., Q0n, which are a part of the output signals Q00, Q01, ... It can be initialized to the "H" level early and relatively stably.

The latch circuit for which the output signal is initialized to the “H” level is not limited to the latch circuits L00, L01, ..., L0n, and the latch circuit group of another line may be the target. .. Further, the output signal may be uniformly initialized to the "H" level for all of the latch circuits L00 to Lmn.

The present invention is not limited to that shown in the above examples. For example, in the above embodiment, the case where the latch circuits L00 to Lmn are arranged in a matrix of (m + 1) rows × (n + 1) columns has been described as an example, but the method of arranging the latch circuits is not limited to this. For example, the number of latch circuits may be arranged less than (n + 1) in only a few rows, or less than (m + 1) in only a few columns.

Further, in the above embodiment, the input data supply unit is composed of a plurality of AND gate circuits, and the reverse power-on reset signal POR2B and the external input data signals DI <0>, DI <1>, ..., DI <m. The case where the logical product with> is supplied to the latch circuits L00 to Lmn as the internal input data signals D0 to Dm has been described as an example. However, the circuit configuration is not limited to this, and at least until a timing later than the time when the inversion start power-on reset signal PORB rises (time t2), the latch circuits L00 to Lmn (in the third embodiment, the latch circuits in a specific row are used. It may be configured to supply "L" level internal input data to the (excluding latch circuit).

Further, in the above embodiment, the external clock signals CKI <0>, CKI <1>, ..., CKI <n> and the internal clock signals CK0, CK1, ..., CKn are pulsed clock signals having a narrow width. The case where it is assumed to be used in combination with the so-called pulse dratch technology has been described as an example. However, when it is easy to secure a timing margin during normal operation, for example, in applications where high-speed operation is not required, the clock signal does not have to be limited to a pulse shape.

Further, in the first and third embodiments, the configuration in which the delay circuit DLY is provided inside the latch array circuit has been described as an example, but unlike this, the delay circuit DLY is arranged at another location outside the latch array circuit and inside the IC chip. You may.

100,200,300 Latch array circuit 11,31 Input data supply unit 12 Clock supply unit L00 to Lmn Latch circuit AN0 to ANm AND Gate circuit OR0 to ORn OR Gate circuit INV0 to INV5 Inverter DLY delay circuit PRC1 First power-on reset circuit R1, R2 Resistance element C1, C2 Capacitive element PRC2 Second power-on reset circuit OR00 OR gate circuit

Claims (10)

Multiple latch circuits arranged in a matrix and
Based on the first timing signal that transitions at the first timing synchronized with the rising edge of the power-on reset signal, each clock input of each of the rows or columns of the plurality of latch circuits until the first timing. A clock control unit that fixes the logical value and
A data supply unit that fixes each data input to a predetermined value for each row or column of the plurality of latch circuits based on a second timing signal that transitions at a second timing later than the first timing.
A latch array circuit characterized by having. The latch array circuit according to claim 1, wherein each of the plurality of latch circuits is a latch circuit having no reset function. The latch array circuit according to claim 1, wherein the second timing signal is a signal obtained by delaying a signal based on the power-on reset signal. The latch array circuit according to claim 3, wherein the delay time of the second timing signal is equal to or longer than the hold time of each of the plurality of latch circuits. The clock control unit includes a first logic gate circuit group including a plurality of logic gate circuits provided for each row or column of the plurality of latch circuits by inputting an external clock signal and the first timing signal. ,
Until the first timing, the clock inputs of the plurality of latch circuits are controlled for each row or column based on the first timing signal, and after the first timing, the rows are based on the external clock signal. The latch array circuit according to any one of claims 1 to 4, wherein the clock inputs of the plurality of latch circuits are controlled for each row or row. The data supply unit includes a second logic gate circuit group including a plurality of logic gate circuits provided for each row or column of the plurality of latch circuits by inputting external data and the second timing signal.
Until the second timing, the data input of the plurality of latch circuits is controlled row by row or column by column based on the second timing signal, and after the second timing, row by row based on the external data. The latch array circuit according to any one of claims 1 to 5, wherein the data input of the plurality of latch circuits is controlled for each column. The data supply unit fixes the data input of at least one row or column of the plurality of latch circuits to a value different from the predetermined value until the second timing, the second logic gate. The latch array circuit according to claim 6, further comprising at least one logic gate circuit different from the logic gate circuit of the circuit group. The one according to any one of claims 1 to 7, wherein the clock control unit supplies a pulsed clock signal as a clock input of the plurality of latch circuits in a period after the first timing. Latch array circuit. The latch array circuit according to any one of claims 1 to 8.
An internal power supply circuit that generates an internal power supply voltage based on the external power supply voltage,
Including
A semiconductor integrated circuit characterized in that at least one of the outputs of the plurality of latch circuits of the latch array circuit is a signal used for controlling a test mode function for forcibly stopping the operation of the internal power supply circuit. The latch array circuit according to any one of claims 1 to 8.
Multiple power-on reset circuits that generate multiple power-on reset signals that transition at different timings,
Including
A semiconductor integrated circuit characterized in that the clock control unit and the data supply unit of the latch array circuit use the plurality of power-on reset signals as the first timing signal and the second timing signal.

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