JPH0210912A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To obtain an FF circuit able to prevent malfunction and implement stable FF operation by using an edge of a data change point so as to invalidate a clock signal if a data and a clock is in contention with each other. CONSTITUTION:A data signal D1 is inputted to a clock input CK of two FFs 2, 3 provided newly in in-phase and opposite phase. Q outputs of each are ANDed by an AND circuit 7 and given to its own reset terminal R. An AND circuit 8 ANDs an AND output of the circuit 7 and an existing clock signal and its resulting AND output is given to a clock input CK of the existing FF1. Then an FF4 is provided newly to avoid double clocks to invalidate a pulse for nearly a half period of a clock when one clock pulse comes. Through the constitution above, malfunction is prevented by invalidating a clock signal by using an edge of a data change point if a data and a clock are competed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a flip-flop circuit, and particularly to a flip-flop circuit that does not malfunction even when a logic circuit network is designed without considering set-up time and hold time. Regarding.

[Conventional technology]

Figure 5 shows a conventional flip-flop (hereinafter referred to as F/F)
FIG. 2 is a circuit diagram showing an example of a circuit.

In FIG. 5, D is data and CK is clock.

S is a set signal, and R is a reset signal. This F/F circuit performs the operation shown in FIG. In this circuit, if the data is constant and only the clock changes, the F/
F reads the data and the output is determined.

[Problem to be solved by the invention]

In conventional F/F circuits, depending on the circuit specifications, data and clock may be input at timings that do not change at the same time, or may be input at timings that conflict with each other. If it was input, the output would be unstable and cause malfunction.

As shown in FIG. 7, when data is changed just before the clock is input, the data must not be changed within a certain period of time from the clock change time. This time is the setup time t. T is calling. Therefore, if the data has changed before this time based on the tarokku change time, the data will definitely be read, but
This set-up time t. If t is short, the output may become undefined.

Also, as shown in Figure 8, when data is changed immediately after the clock is input, the data must not be changed within a certain period of time from the clock change time, and this time is called hold time jhold. There is. Therefore, if the data changes after this time has elapsed based on the clock change time, the data will be reliably read, but if this hold time is short, the output may become unstable.

In other words, if data and clocks are input at conflicting timings, the output becomes unstable and malfunctions occur, so it is necessary to take timing into consideration in circuit design or in actual use. In actual use, even if the clock and data are used in timing conflict, the clock signal can be disabled for a short time before and after the data changes, that is, during the sum of the set-up time and hold time, to maintain a stable F. An object of the present invention is to provide an F/F circuit that can perform a /F operation.

[Means to solve the problem]

The F/F circuit of the present invention is a logic circuit having a flip-flop circuit in which data input and clock input are input at competing timings, and in which a plurality of pulse generation circuits different from a regular clock signal are used for the clock of the flip-flop. A regular tarok signal and a regular data signal are independently supplied to the clocks of the plurality of pulse generating circuits, and the output signal of the pulse generator is supplied to the flip-flop circuit together with the regular clock signal. Ru.

〔Example〕

Next, this embodiment will be explained using the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, in the conventional circuit, data signals are input into the clock inputs of two newly provided F/Fs in the same phase and in opposite phase.Then, the AND of the ζ-outputs of these two F/Fs is performed.
At the same time as connecting the own reset, and this AN
The D output is further ANDed with the existing clock signal and connected to the clock input of the existing F/F circuit, and when one clock is input, an additional F/F is connected to disable the clock signal for a certain period of time. The other points are similar to the conventional circuit.

Next, the operation of the first embodiment will be explained.

First, when the data signal D1 is changed from "L" to "°H゛°," it hits the tarok of F/F2 (- becomes L II and also enters its own reset input, F/F2 is reset and the output Q is also It becomes H'.

On the other hand, since the clock of F/F3 is not struck, the count remains at "H". Therefore, the output of the AND gate 7 changes from H to L and then to H. Therefore, when the output of the AND gate 7 is in the "L" state, even if a tarok signal is input, it is invalid.

Similarly, if date D1 changes from H to L, F
/F3's (- changes from "H" to "L" and then "H''', and the output of F/F2 (- remains H", so AN
The output of D gate 7 also changes from “H” to “L II” and then °゛H.
Changes to ``. Therefore, the output of AND gate 7 is “L”
When in the state, the clock signal is disabled.

Here the clock pulse width is normally set up.

Since this is larger than the hold time width, there is a risk of double clocking as shown in FIG. Therefore, when one clock pulse is input, the F/F 4 constitutes a pulse generating circuit for making the pulse invalid for about half the period of the clock.

In other words, when CK1 goes from L II to “H”, F/F4
The output q- of F/F4 changes from “H” to “
Since it becomes L'' and is also included in its own reset input, it becomes F.
/F4 is reset and the output q- becomes H'' again. However, the clock signal is invalidated after CK rises, the sum of set-up and hold times, and the minimum pulse width has elapsed. .

As can be seen from FIG. 3, since the waveforms of point A, CK, and point B are ANDed, the clock waveform at point 0 must be at least as long as the minimum pulse width.

Route a (DI~D) and route b (D1~D) shown in Figure 1
2 F/F ~ A point), route c (DI ~ 3 F/F ~ A
The delay time at point) must satisfy the following relational expression. That is, as can be seen from the time chart shown in Fig. 3, t pda t pdb t pd7≧thold
”・・・(1) t, .+d+t−□≦tw
・・・・・・(2)t9db匈tpda
...The relational expression (3) holds true. Here, j9da is the delay time from beam to D, tpdb is the delay time from Dl to point A via F/F2, and tpd7 is the delay time of AND gate 7, and tpdc is the delay time from beam to F/F2. This is the delay time from F3 to point A.

Further, tw is the sum of the delay time of the AND gate 5 and the delay time σ1 from the reset of the F/F 2, or the sum of the delay time of the AND gate 6 and the delay time σ1 from the reset of the F/F 3.

Furthermore, the point B falls after CK rises is tw+jwm+. More time is required.

This t□1o indicates the minimum pulse width.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the sum of the set-up and hold times is adjusted using an AND gate and the delay time from the set of F/F 2 or 3 to the Q output, and the pulse generation circuit is installed in the F/F to prevent double clocks. This is the same as the first embodiment except that the output Q of F4 is entered into its own set.

〔Effect of the invention〕

As explained above, the F/F circuit of the present invention provides a pulse circuit as a set-up and hold time-free F/F circuit, thereby eliminating the edge of a data change point when data and clocks are in conflict. This has the effect of preventing malfunctions by invalidating the clock signal.

Therefore, by registering a circuit as shown in FIG. 1 as one F/F, there is an effect that even if set-up and hold times are overlooked during design, they can be reliably checked during logic verification.

[Brief Description of the Drawings] Figure 1 is a logic circuit diagram showing a first embodiment of the present invention, and Figure 1 is a logic circuit diagram showing a first embodiment of the present invention.
The figure is a circuit diagram showing the second embodiment of the present invention, Figures 3 and 4 are time charts showing the operation of the F/F circuit of the present invention, and Figure 5 is a circuit diagram showing the second embodiment of the present invention.
The figure is a circuit diagram showing a conventional example, and Figure 6 is the F shown in Figure 5.
FIG. 7 is a time chart showing the setup time, and FIG. 8 is a time chart showing the hold time. 1-4...F/F, 5-13...AND circuit, 14
...Inverter circuit, D...Data, CK...Clock, R...Reset, S...Set, D+...1 F/F data,
C.K. ...1 F/F clock, tset...set-up time, jhold...hold time, tpd, L
...Delay time from Dl to D, t pdb...D
, the delay time from 2 to point A via F/F, tp
dc...Delay time from Dl to point A via F/F 3, j +>d7...Delay time of 7 gates, j
wain...minimum pulse width.

Claims (1)

[Claims] A logic circuit having a flip-flop circuit to which data input and clock input are input at conflicting timings, the flip-flop clock being provided with a plurality of pulse generation circuits different from a regular clock signal, and the plurality of pulse generation circuits A flip-flop circuit characterized in that a regular clock signal and a regular data signal are independently supplied to the clock, and an output signal of the pulse generator is supplied to the flip-flop circuit together with the regular clock signal.