JPH07260899A - Signal timing adjusting circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous function due to alteration of in the variation of each logic state among a plurality of signals. CONSTITUTION:When the logic state changes in each input signal I1,..., I3, corresponding logic state variation detection signals enter into an H state. Even it more than one logic state variation detection signals E1,..., E3 enter into the H state within a predetermined timing adjusting time interval, one timing adjusting clock signal ECK is outputted. Consequently, even if the logical state changes in a plurality of signals within the timing adjusting time interval, input signals Ia1,..., Ia3 are outputted at same timing.

Description

Detailed Description of the Invention

[0001]

The present invention relates to, for example, an LSI (large
Suitable for use as an input circuit of a semiconductor integrated circuit such as a scale integrated circuit) and to prevent malfunction of an internal circuit due to a subtle mutual change in the order of change of each logic state between a plurality of signals. The present invention relates to a signal input timing adjustment circuit capable of performing the above.

[0002]

2. Description of the Related Art Logic circuits built in a semiconductor integrated circuit such as an LSI can be roughly classified into combinational circuits and sequential circuits. This combination circuit performs a predetermined logical operation only with the current input and outputs the logical operation result. On the other hand, in the sequential circuit, the output is not determined only by the current input, but is determined depending on the input and the past history of the sequential circuit. Therefore, the sequential circuit includes means for storing the past history of the input and the past history of the sequential circuit, that is, a flip-flop or a latch.

Further, in such a sequential circuit, there is a circuit in which the operations of a plurality of flip-flops are operated in synchronization with a common clock signal. Such a circuit is called a synchronous sequential circuit and is widely used. Such a synchronous type sequential circuit has advantages such as easier timing design and the like than an asynchronous type sequential circuit.

[0004]

However, the LSI
In the input circuit of the semiconductor integrated circuit such as or the like, or the external circuit thereof, the internal circuit may malfunction due to a subtle mutual change in the order of change of each logic state between a plurality of signals. For example, malfunction may occur in the above-mentioned synchronous sequential circuit in the internal circuit.

For example, there is a circuit in which one signal is generated at the same time as the other signal, or is generated earlier by a very small time, and the generation order of these signals is changed due to some difference in conditions. It may end up. When such an order change occurs, even if the time difference between these signals is extremely small, a circuit using these signals may malfunction.

For example, a case where a predetermined tester device is used to test the operation of an actual LSI while inputting a test pattern from its input / output pins, and a case where a test is performed by simulation before manufacturing the LSI. In the above, changes in operating conditions may occur. As a result, the order of changes in the respective logic states may be exchanged between a plurality of signals input to the LSI. In such a case, a malfunction may occur even if the mutual time intervals at which the change in the logic state of the signal occurs is extremely small.

For example, when performing a test while inputting a test pattern to an actual LSI, a timing variation of a signal input to the LSI of a tester device that generates a test pattern (hereinafter referred to as a tester skew)
Is, for example, ± 1.5 ns. In this case, a maximum of the plurality of signals input to the LSI as the test pattern,
A variation of (1.5 + 1.5 = 3 nS) will occur.

Therefore, between a plurality of signals that are close to each other within a time interval of 3 nS, there is a possibility that the change order of each logic state may be changed due to changes in various test conditions. For example, due to changes in the unnecessary capacitance of the probe used to input signals to the input / output pins of the LSI,
There is a risk that the order of such changes in the logical state may be changed.

FIG. 7 is a circuit diagram showing an example of a circuit using a conventional flip-flop. In FIG. 7, a total of five D-type flip-flops FF1 to FF5 are used, which is an example of a synchronous sequential circuit.

These flip-flops FF1 to FF5
Are connected in series for each data input D and each data output Q. The data input signal ID is input to the data input D of the D-type flip-flop FF1. Further, the data output signal OD is output from the data output Q of the D-type flip-flop FF5.
Is being output.

Further, the D-type flip-flops FF1 and F
In F2 and FF5, each clock input C
The clock signal CKa is input to K. The clock signal CKb is input to the clock input CK of each of the flip-flops FF3 and FF4.

In the circuit shown in FIG. 7, when the clock signal CKa rises and the clock signal CK rises.
It is possible that the rising edge of b is operated at the same timing.

However, due to some cause, for example, when the clock signals CKa and CKb are independently input from the outside of the LSI by the tester as described above, variations in the input signal as described above, that is, tester skew, There is a possibility that a slight deviation of the rising timing may occur between the clock signals CKa and CKb. In this case, each D-type flip-flop FF1
There is a risk of malfunction that data captured and held by FF5 at the rising edge of the signal input to each clock input CK is different.

The present invention has been made to solve the above-mentioned conventional problems, and can prevent malfunction of an internal circuit due to a subtle mutual change in the order of change of each logic state between a plurality of signals. It is an object of the present invention to provide a signal timing adjustment circuit that can be performed.

[0015]

According to the present invention, a first input flip-flop to which a first input signal is input is input to its data input, and a second input flip-flop to which a second input signal is input to its data input. A first input signal change detection circuit that detects a change in the logic state of the data input of the first input flip-flop, and a second detection circuit that detects a change in the logic state of the data input of the second input flip-flop.
When a change in the logic state is detected in at least one of the input signal change detection circuit and the first input signal change detection circuit or the second input signal change detection circuit, the detection is delayed by a predetermined timing adjustment time width Tα. And a timing adjustment clock signal generation circuit for outputting a timing adjustment clock signal CKα which is transmitted by transmitting the timing adjustment clock signal CKα to the respective clock inputs of the first input flip-flop and the second input flip-flop. By doing so, the above-mentioned problems are achieved.

In the signal timing adjusting circuit, the first input signal change detecting circuit compares the data input and the data output of the first input flip-flop by comparing the logic states of the data input and the data output. The second input signal change detection circuit detects a change in the logic state, and the second input signal change detection circuit compares the logic states of the data input and the data output of the second input flip-flop to determine the logic of the data input. By detecting the change of the state, the above-described object is achieved, and the first input flip-flop and the second input flip-flop are provided in response to the detection of the change of the logical state transmitted by the timing adjustment clock signal CKα. The input flip-flop is designed to operate more reliably.

[0017]

In the conventional logic circuit, which has no problem in the normal logic simulation, this is actually built into the LSI, and the tester device as described above is connected to the input / output pin thereof while inputting the test pattern. Upon testing, various circuit operating problems were sometimes found.

The inventor has found that one of the causes is the influence of the tester skew as described above. Due to such tester skew, the clock signal CKa as described above with reference to FIG.
That is, the order of the change of the logic state of the clock signal and the change of the logic state of the clock signal CKb is changed.

In view of the above points, the present invention provides:
When a signal timing adjustment circuit is provided in the input part of an LSI or the like, and when a plurality of signals approach each other within a time shorter than a predetermined timing adjustment time width Tα and a logic state change occurs, these logic state changes are the same. It is decided that it should occur at the time. Therefore, in the signal timing adjustment circuit, the timing adjustment time width Tα
The changes in the logic states of a plurality of signals that have come close to each other are timing-adjusted as changes in the logic state at the same time and are input to the internal circuit.

On the other hand, in the signal timing adjustment circuit of the present invention, regarding the change of each logic state between a plurality of signals having a time interval longer than the timing adjustment time width Tα, the respective logic states are changed. It is determined that the time of change is independent. Therefore, with respect to the change of the logic state between a plurality of signals having these time intervals, the timing is not adjusted, that is, the timing of the change of the logic state is not matched, and the signal is directly input to the internal circuit. ing.

As described above, according to the present invention, even if a subtle mutual change occurs in the order of change of each logical state between a plurality of signals, the internal circuit is adjusted by the signal timing adjustment as described above. Can be prevented from malfunctioning. Even if such a signal timing adjusting circuit of the present invention is provided, if the timing of the change in the logic state between the signals is far from the timing adjusting time width Tα, no timing adjustment is made. The provision of the signal timing adjusting circuit has very little influence on the timing, and is basically zero.

[0022]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a signal timing adjusting circuit used in the LSI of the first embodiment to which the present invention is applied.

In FIG. 1, symbols I1 to I3 are L
It is the name of an input signal input from outside the SI and the name of a terminal for inputting a signal. Reference numerals B1 to B3 are input buffers used when such a signal is input.
Composite input flip-flops IF1 to IF3 are provided next to the input buffers B1 to B3. These composite input flip-flops IF1 to IF3 output the data input signals Ia1 to Ia3 to the internal circuit according to the input data input signals I1 to I3, respectively. The composite input flip-flops IF1 to IF3 each include an input flip-flop and an input signal change detection circuit to which the present invention is applied.

Further, these composite input flip-flops IF
1 to IF3 output logic state change detection signals E1 to E3, which output detection of changes in the logic state of the input data input signal, respectively. These logic state change detection signals E1 to E3 are input to the timing adjustment clock signal generation circuit G to which the present invention is applied.

The timing adjustment clock signal generation circuit G
Is one of the decoding input flip-flops IF1 to IF1.
When a change in the logic state is detected in the data input signal input to each of the IF3, the detection is delayed by the timing adjustment time width Tα in accordance with the logic state change detection signals E1 to E3 which transmit the detection. The timing adjustment clock signal ECK to be transmitted is output.

FIG. 2 is a circuit diagram of the composite input flip-flop used in the first embodiment.

As shown in FIG. 2, the composite input flip-flops IF1 to IF3 (hereinafter collectively referred to as composite input flip-flops IFi) are composed of a D-type flip-flop FF and an exclusive OR logic gate G1. I'm going.

The D-type flip-flop FF corresponds to the first input flip-flop or the second flip-flop to which the present invention is applied. Further, the exclusive OR logic gate G1 is a first input signal change detection circuit or a second input signal change detection circuit to which the present invention is applied. That is, the code F serves as the first input signal change detection circuit or the second input signal change detection circuit. The exclusive OR logic gate G1 is
The logic state of the data input D and the data output Q of the D-type flip-flop FF is compared, and the logic state of the data input D is detected based on the difference.

Even if the logic state of the data input D changes, if the signal input to the clock input CK of the D-type flip-flop FF does not rise, the logic state of the data output Q naturally changes. do not do. Therefore, such data input D and data output Q
The change in the logic state of the data input D is detected based on the difference in the logic state between and.

Therefore, in such a composite input flip-flop IFi, first, when the logic state of the data input D changes, the logic state change detection signal E1.
˜E3 (generally referred to as logic state change detection signal Ei) becomes H state. In the composite input flip-flop IFi, the timing adjustment clock signal E
When CK rises, the data input D is taken in and held in the D-type flip-flop FF. Further, the logic states thus captured and held are the same as the data input Ia1.
It is output as Ia 3 (collectively referred to as data input Iai).

FIG. 3 is a circuit diagram of the timing adjustment clock signal generation circuit used in the first embodiment.

As shown in FIG. 3, the timing adjustment clock signal generating circuit G shown in FIG.
It is composed of a logic gate G2, an AND logic gate G3, a predetermined number of buffer gates G4, and an inverter G5.

The OR logic gate G2 has three inputs and the composite input flip-flops IF1 to IF3.
The logic state change detection signals E1 to E respectively output by
Input 3 independently. Therefore, when the detection of the change in the logic state is transmitted to any of the corresponding data inputs I1 to I3 by any of these logic state change detection signals E1 to E3, the clock signal output from the OR logic gate G2. EC becomes H state.

The clock signal EC is output as the timing adjustment clock signal ECK while being transmitted through the AND logic gate G3, the buffer gate G4 and the inverter gate G5. These AND logic gate G3, buffer gate G4 and inverter gate G5
Constitutes a kind of oscillator circuit.

The signal delay time due to the AND logic gate G3, the buffer gate G4 and the inverter gate G5, which are used in a predetermined number, is significantly larger than the signal delay time at the OR logic gate G2 and the composite input flip-flop IFi. It's getting longer. If the total delay time of the AND logic gate G3, the predetermined number of buffer gates G4, and the inverter gate G5 is Tβ, the timing adjustment time width Tα
Can be approximately expressed as (Tα = 2 × Tβ).

FIG. 4 is a time chart showing the operation of the first embodiment.

In this time chart, it is assumed that all the logical states of the input signals I1 to I3 have changed within the timing adjustment time width Tα.
Further, in particular, it is assumed that the change in the logic state of the input signal I1 occurs first.

First, at time t ₁ in FIG. 4, the input signal I1 falls. Along with this, the time
Immediately after t ₁ , the logic state change detection signal E1 rises. This is the composite input flip-flop IF1.
This is because the change of the logic state is detected in the data input D of the exclusive OR logic gate G1 included in the.

After a relatively short time from the time t ₁ ,
At t ₂ , the clock signal EC rises. this is,
This is because the logic state change detection signal E1 rises and the output of the OR logic gate G2 rises.

The time between the time t ₁ and the time t ₂ is shown to be relatively long on this time chart, but it is an extremely short time, and the timing adjustment time width is Even if compared with Tα, it is a negligible short time.
Further, in the present embodiment, the timing adjustment time width Tα is the time from time t ₂ to time t ₆ , but basically,
It can also be considered as the time from time t ₁ to time t ₆ .

Then, at time t ₃ , the input signal I3 rises. Along with this, immediately after the time point t _3, the logic state change detection signal E3 is rising. This is because the change in the logic state of the input signal I3 is detected by the exclusive OR logic gate G1 included in the composite input flip-flop IF3.

Then, at time t ₄ , the input signal I2
Is falling. Further, immediately after the time t _4, the logic state change detection signal E2 is rising. The rise of the logic state change detection signal E2 is because the change of the logic state of the input signal I2 is detected by the exclusive OR logic gate G1 included in the composite input flip-flop IF2.

Even if the logic state change detection signal E3 rises immediately after the time t ₃ or the logic state change detection signal E2 rises immediately after the time t ₄ , the clock signal is already generated. EC has risen and there is no further change in logic state.

After the delay time Tβ from the time t ₂ ,
That is, at time t ₅ , the timing adjustment clock signal E
CK falls. Along with this, the output of the AND logic gate G3 shown in FIG. 3 becomes the L state. The AND
By the output of the logic gate G3 becomes L state, after the delay time T [beta, i.e. at time t _6, the timing adjustment clock signal ECK is that raises.

When the timing adjustment clock signal ECK rises at the time t _{6, the} D-type flip-flops FF included in the composite input flip-flops IF1 to IF3 respectively have the same time, that is, at the time t ₇ . The logic state input to the data input D of is captured and held. That is, at this time t ₇ , the change of the logic state of the input signals I1 to I3 whose change timings of the logic state are close to each other and shifted from each other at the same timing is caused by the corresponding composite input. The flip-flops IF1 to IF3 are taken in and held in the D-type flip-flop FF at the same timing. This is accompanied, immediately after the time t _7, the input signal I1~
The input signals Ia1 to Ia3 change at the same timing according to the respective logic states of I3.

As described above, according to the first embodiment, two or more signals among the input signals I1 to I3 change their logic states when approaching within the timing adjustment time width Tα. In this case, the timing of the change of the logic state is adjusted, and the corresponding input signal I is obtained at the same timing.
It is output as a1 to Ia3.

Further, when only one change in the logical state of these input signals I1 to I3 occurs independently in timing, after the timing adjustment time width Tα, respectively, the corresponding input signal Ia. It is output as 1 to Ia 3.

Therefore, according to the third embodiment, even if there is a subtle mutual change in the order of the change of the respective logic states among the plurality of the input signals I1 to I3, such mutual change is caused. If it is within the timing adjustment time width Tα, it is possible to effectively prevent malfunction of the internal circuit by synchronizing the change timing.

FIG. 5 is a circuit diagram of a part of the LSI of the second embodiment to which the present invention is applied.

As shown in FIG. 5, combinational circuit portions N1 and N2 are built in the LSI of the second embodiment. A predetermined logic circuit is configured in each of the combinational circuit units N1 and N2.

The input / output portions of the combinational circuit portions N1 and N2 are flip-flop circuits FF which are also used as scan registers in the scan path test.
B1 to FFB (k + m + r) are provided. These flip-flop circuits FFB1 to FFB (k + m + r)
With respect to, the clock signals CKa and CKb are used in a mixed manner as a clock used when shifting as the scan register.

Therefore, these clock signals CKa and C
Depending on the rise timing of Kb, there is a risk that a malfunction may occur during the shift of the bit data. However, in the second embodiment, the malfunction is effectively prevented by applying the present invention.

FIG. 6 is a circuit diagram of a signal timing adjusting circuit to which the present invention is applied in the second embodiment.

As shown in FIG. 6, in the second embodiment, the signal timing adjusting circuit is used for the clock signals CKa and KCb.

In the second embodiment, as compared with the first embodiment shown in FIG. 1, the number of the composite input flip-flops IFi is reduced by one and two are used. is there. Regarding the timing adjustment clock signal generating circuit G, in the first embodiment, the OR logic gate G2 has three inputs as shown in FIG. 3, whereas the timing adjustment clock signal used in the present invention is the same. The OR logic gate G2 included in the signal generation circuit G
Is one that has two inputs.

As shown in FIG. 6, the clock signal C
In order to obtain Ka and CKb, in the second embodiment,
Clock signals CKa 'and CKb' are input from the outside of the LSI. These clock signals CKa 'and CKb'
Is input to the signal timing adjusting circuit, the rising timings approaching each other within the timing adjusting time width Tα are adjusted to the same timing, and output as the clock signals CKa and CKb.

As described above, according to the second embodiment, it is possible to eliminate a subtle deviation in the order of changes in the respective logic states between the clock signals CKa 'and CKb', and the shift register can be used. It is possible to prevent the malfunction of the flip-flop circuits FF1 to FF (k + m + r) when operated.

The signal timing adjusting circuit shown in FIG. 6 of the present embodiment can be used for generating the clock signals CKa and CKb of FIG. Accordingly, the D as described above in FIG.
It is also possible to effectively prevent malfunction of the type flip-flops FF1 to FF5.

[0060]

As described above, according to the present invention,
It is possible to obtain an excellent effect that it is possible to effectively prevent a malfunction of the internal circuit due to a subtle mutual change in the order of change of each logic state between a plurality of signals.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a signal timing adjustment circuit used in an LSI of a first embodiment to which the present invention is applied.

FIG. 2 is a circuit diagram of a composite input flip-flop used in the signal timing adjustment circuit of the first embodiment.

FIG. 3 is a circuit diagram of a timing adjustment clock signal generation circuit used in the signal timing adjustment circuit of the first embodiment.

FIG. 4 is a time chart showing the operation of the signal timing adjustment circuit of the first embodiment.

FIG. 5 is a circuit diagram of a part of an LSI according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a signal timing adjustment circuit of the LSI of the second embodiment.

FIG. 7 is a circuit diagram showing an example of a circuit using a conventional D-type flip-flop.

[Explanation of symbols]

I1 to I3 ... Input signal (target of signal timing adjustment) IS1 to ISk ... Input signal Ia1 to Ia3 ... Input signal (generated by signal timing adjusting circuit) B1 to B3, IB1 to IBk ... Input Buffers IFi, IF1 to IF3 ... Composite input flip-flops FF, FF1 to FF5 ... D-type flip-flop G ... Timing adjustment clock signal generation circuit G1 ... Exclusive OR logic gate G2 ... OR logic gate G3 ... AND logic gate G4 ... Buffer gate G5 ... Inverter gates E1 to E3 ... Clock signals ECK ... Timing adjustment clock signals N1, N2 ... Combination circuit section FFB1 to FFB (k + m + r) ... Flip-flop circuits (also used as scan registers) CKa ', CKb' ... Clocks Signal (input from outside Things) CKa, CKb ... clock signal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location // H03K 5/156 Z H03K 5/00 K

Claims (2)

[Claims] 1. A first input flip-flop having a data input to which a first input signal is input, a second input flip-flop having a data input to which a second input signal is input, and the first input flip-flop. A first input signal change detection circuit for detecting a change in the logic state of the data input of the second input flip-flop, a second input signal change detection circuit for detecting a change in the logic state of the data input of the second input flip-flop, When a change in the logic state is detected by at least one of the first input signal change detection circuit and the second input signal change detection circuit, the detection is performed by a predetermined timing adjustment time width Tα.
And a timing adjustment clock signal generating circuit for outputting a timing adjustment clock signal which is transmitted after being delayed only by the timing adjustment clock signal. The timing adjustment clock signal is supplied to the respective clock inputs of the first input flip-flop and the second input flip-flop. A signal timing adjustment circuit characterized by being adapted to be input. 2. The logic state of the data input according to claim 1, wherein the first input signal change detection circuit compares the logic states of the data input and the data output of the first input flip-flop. The second input signal change detection circuit compares the logical states of the data input and the data output of the second input flip-flop to determine the logical state of the data input. A signal timing adjusting circuit characterized by detecting a change.