JP2853752B2 - Transmission line length measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line length measuring apparatus for measuring a transmission line length from a reflected waveform obtained by transmitting a pulse to a transmission line having an open end, and more particularly to an integrated circuit having a plurality of test pins. In a test apparatus, etc., a transmission line length suitable for highly accurate measurement of a transmission line length from a test pattern output / test result determination circuit installed corresponding to the test pin to an input / output pin of a circuit under test. It relates to a measuring device.

[0002]

2. Description of the Related Art In a timing correction necessary for maintaining the test timing accuracy of an integrated circuit test apparatus, a test pattern output / test result judgment circuit installed corresponding to a test pin of the integrated circuit test apparatus performs a test. One of the main processing items is to correct a timing error caused by a variation between test pins in a transmission line length to an input / output pin of a circuit.

Conventionally, in measuring such a transmission line length, a method as described in Japanese Patent Application No. 62-309326 has been used. An example of this prior art will be described with reference to FIG.

In FIG. 4, two phase difference detection circuits 10
1 and 102, respectively, the transmission line 10 to be measured
0 is set to the far-end open state, and the input terminals A1 and B1 of one of these two phase difference detection circuits 101 and 102, respectively.
And a pulse signal S1 having a constant repetition cycle
And a reference pulse signal S2 whose repetition period is slightly different from that of the pulse signal S1 is input to the other input terminals A2 and B2. On the other hand, the phase difference detection circuit 101 compares the phase difference between the signals supplied to the two input terminals A1 and A2 at the timing of the first rising edge of the stepped reflected wave appearing at the input terminal A1. The other phase difference detection circuit 102 compares the phase difference between the signals supplied to the two input terminals B1 and B2 at the timing of the second rising edge of the stepped reflected wave appearing at the input terminal B1.

The phase difference information signals S3 and S4 from the phase difference detection circuits 101 and 102 are supplied to an exclusive OR gate 103, and the gate output S5 and the reference pulse signal S2 are supplied to an AND gate 104. Only when the phase difference signals S3 and S4 do not match, the AND gate 104 outputs the reference pulse signal S2 as valid. By counting the effective pulse signal S6 by the counter 105, the time difference between the first and second rising edges of the stepped reflected wave is obtained, and the value of this time difference is divided into two to divide the propagation delay in the round trip of the transmission line. Was considered time.

[0006]

The above-mentioned state where the phase difference information signals S3 and S4 of the phase difference detection circuits 101 and 102 do not coincide with each other is caused by the rising edge portions of the phase difference information signals S3 and S4. And a mismatch state at each falling edge portion. For example, when the phase difference is detected at the rising edges of the input signals A1 and B1, the rising edges of the phase difference information signals S3 and S4 correspond to the rising edges of the reference pulse signal S2 and the rising edges of the input signals A1 and B1. Occurs when crossing.
On the other hand, each falling edge of the phase difference information signals S3 and S4 corresponds to the falling edge of the reference pulse signal S2 as the input signal A1.
And when the rising edge of B1 crosses.

The phase difference between the rising edges and the phase difference between the falling edges of the phase difference information signals S3 and S4 are both equal to the propagation delay time 2T when reciprocating the transmission line.
And the repetition periods t, t + of the pulse signals S1 and S2
dt, and ideally 2T is (t + Δt)
It is equal to the value expanded by / Δt times.

However, an actual phase difference detection circuit has a unique detection sensitivity characteristic, and the lower the detection sensitivity is, the more errors occur in the phase difference.

Therefore, the phase difference detection circuits 101 and 10
If the detection sensitivity characteristic of No. 2 has a difference between the detection between the rising edge and the rising edge and the detection between the rising edge and the falling edge, more errors are caused by the detection result of the phase difference between the edges having lower detection sensitivity. As a result, the above measurement method has a problem that this error is inevitably included.

For example, if the circuit described in Japanese Patent Application No. 62-299037 is applied to the above-described phase difference detection circuit, if the current semiconductor technology is used, the detection of a phase difference between a rising edge and a rising edge will require several picoseconds. Although a detection sensitivity of seconds can be realized, the detection of a phase difference between a rising edge and a falling edge is inferior in principle in sensitivity, and poses a problem in measurement accuracy.

Further, in the above-mentioned prior art, since the number of reference pulse signals repeated only for one cycle of the mismatch period between the two phase difference information signals corresponds to twice the transmission line length, Counting the number of reference pulse signals repeated only for one cycle of the non-coincidence period, or accurately grasping the number of reference pulse signals counted in the non-coincidence period of both phase difference information signals There is a need. However, there is no function to realize this, and there has been no other way but to control the number of input signal pulses of the phase difference detection circuit by additional means.

An object of the present invention is to solve the conventional problems and to provide a highly accurate and high-performance transmission line length measuring device.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a transmission line length measurement for measuring a transmission line length from a reflected waveform obtained by sending a pulse to a transmission line having an open end. In the apparatus, a staircase wave having a constant repetition cycle due to the far-end opening and a reference pulse signal whose repetition cycle is slightly different from the staircase wave are input as input signals, and threshold values for the two input signals are independently set. Controllable, a first phase difference detection circuit that selectively detects a phase shift between both input signals for each rising edge or falling edge due to the traveling wave component of the staircase wave, and the staircase wave,
The reference pulse signal is input as an input signal, and a threshold value for the two input signals can be independently controlled, and a phase between both input signals at each rising edge or falling edge due to the reflected wave component of the staircase wave A second phase difference detection circuit for selectively detecting a shift, wherein the staircase wave is input as a common two input signal, and a threshold value for the two input signals can be independently controlled; A third phase difference detection circuit for selectively detecting a phase shift between a rising edge or a falling edge of a wave component and a traveling wave component, and each of the first, second, and third phase difference detection circuits From the first, second and third phase difference information signals from the first phase difference information signal and the second phase difference information signal, Phase shift occurring in the downstream part A phase difference signal extraction circuit for selectively extracting any one of the first and second phase difference information signals after a request signal is input from the outside and the request signal is input. A reference pulse gate circuit that validates the reference pulse signal within a period corresponding to minutes and only during a phase shift period extracted by the phase difference signal extraction circuit, and a counter that counts an output signal from the reference pulse gate circuit. , Is provided.

[0014]

According to the present invention, the timing of the edge of the stepped waveform in which the reflected wave is superimposed on the traveling wave and the timing of the edge of the reflected wave are individually set to a repetition period slightly different from the stepped waveform. The timing of the traveling wave edge is compared with the timing of the reference pulse, and the phase polarity of the edge of the traveling wave and the edge of the edge of the reflected wave are detected at the same time. Out of the mismatched state between the phase difference information signal obtained and the phase difference information signal obtained by comparing the timing of the reflected wave and the reference pulse, either of the mismatched state between the rising edge or the falling edge of the two phase difference information signals One of which is selectively extracted, and after the measurement request signal is input from the outside, the reference pulse signal is generated for one cycle of the extracted mismatch period. By counting, timing difference of the reflected wave edge with the traveling wave edge, i.e. measuring the length of the transmission line.

Therefore, the detection sensitivity of the phase difference detection circuit is
Even if detection between edges of the same polarity is different from detection between edges of the opposite polarity, only the highly sensitive detection result can be used as the measurement result, so that the characteristics of the phase difference detection circuit can be fully utilized. Thus, the transmission line length can be measured with high accuracy. In addition, the count value corresponding to the transmission line length can be obtained without control of the number of pulses of the input signal.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the basic circuit configuration of the present invention. FIG. 2 is a time chart illustrating signals at various parts of the embodiment of the basic circuit configuration of the present invention shown in FIG. An embodiment will be described below with reference to both drawings.

At the rising edge of the staircase wave RF obtained by opening the far end of the transmission line 100 with the transmission delay time T,
The first edge, ie, the edge due to the traveling wave, is a, and the second edge, ie, the edge due to the reflected wave, is b. These edges a and b have a timing shift of 2T.

In FIG. 1, reference numerals 1, 2, and 3 are phase difference detection circuits capable of controlling the threshold value of an input signal. Both signals are applied to the phase difference detection circuit 1 as input signals to be measured in order to compare the phase difference between the rising edge a of the traveling wave and the rising edge of the timing comparison pulse PR. Here, as shown in FIG. 2, an intermediate level of a rising edge due to a traveling wave and an intermediate level of a timing comparison pulse PR are set as reference level inputs VR11 and VR12 for determining an input signal threshold, respectively. .

Both signals are added to the phase difference detection circuit 2 as input signals to be measured in order to compare the phase difference between the rising edge b of the reflected wave and the rising edge of the timing comparison pulse PR. Here, as shown in FIG. 2, reference level inputs VR21 and VR21 for determining the threshold value of the input signal.
As 22, the intermediate level of the rising edge due to the reflected wave and the intermediate level of the timing comparison pulse PR are set, respectively.

Similarly, in order to compare the phase difference between the rising edge a due to the traveling wave and the rising edge b due to the reflected wave, the staircase signal is added to the phase difference detection circuit 3 as a common input signal to be measured. Can be Here, as shown in FIG. 2, a reference level input VR3 for determining an input signal threshold value
The intermediate level of the rising edge due to the traveling wave and the intermediate level of the rising edge due to the reflected wave are set as 1 and VR32.

As shown in FIG. 2, the phase difference detection circuits 1 and 2 output a high level as positive phase difference information when the timing of the timing comparison pulse PR is later than the other timing, and In the case of NRZ (Non Ret), a low level is output as negative phase difference information.
(urn Zero), and outputs an inverted signal Q− of the phase difference information signal Q +.

On the other hand, the operation of the phase difference detection circuit 3 is the same as that of the phase difference detection circuit 1 or 2, and the rising edge timing due to the reflected wave is later than the rising edge timing due to the traveling wave. As the phase difference information, a high level NRZ signal is constantly output to Q + and a low level NRZ signal is output to Q−.

Here, the repetition periods of the staircase wave RF and the timing comparison pulse PR are t and t + dt, respectively.
And the difference between the repetition periods of both signals is dt
Therefore, the phase relationship between the two signals is shifted by dt every cycle. Accordingly, the period of each of the output signals Q + and Q− of the phase difference detection circuits 1 and 2 is t + dt (t + d
t) / dt times, and the phase difference detection circuit 1
, And the phase relationship between the output signals Q + and Q− of the phase difference detection circuit 2 are the same as the period, except for the time difference 2 between the edge a due to the traveling wave and the edge b due to the reflected wave.
T is expanded by (t + dt) / dt times.

Next, reference numeral 4 denotes a phase difference signal extraction circuit. As an embodiment of the phase difference signal extracting circuit 4, FIG.
In this example, NOR gates 41, 42, 43, 44 and 45 are used. Hereinafter, the configuration and operation of this phase difference signal extraction circuit will be described.

The NOT logic of each of the output signal Q + of the phase difference detection circuit 1 and the output signal Q− of the phase difference detection circuit 2 and the output signal Q− of the phase difference detection circuit 1 and the output signal Q + of the phase difference detection circuit 2 The sum is taken by logic gates 41 and 42. As shown in FIG. 2, the output of the logic gate 41 is a period during which a timing difference between the falling edges of the output signal Q + of the phase difference detection circuit 1 and the output signal Q + of the phase difference detection circuit 2 occurs. Only a high level occurs. As shown in FIG. 2, the output of the logic gate 42 is only for a period during which a timing difference between rising edges between the output signal Q + of the phase difference detection circuit 1 and the output signal Q + of the phase difference detection circuit 2 occurs. High level occurs.

Further, for example, the output of the logic gate 41, the output signal Q + of the phase difference detection circuit 3, and the logic gate 4
2 and the output signal Q− of the phase difference detection circuit 3 are NORed by the logic gates 43 and 44, the circuit 3
The output of the logic gate 43 is fixed at a low level because a high level is constantly output to the output signal Q +. On the other hand, as shown in FIG. 2, the output signal Q- of the circuit 3 has a low level steadily output, so that the output of the logic gate 44 is an inverted signal of the output of the logic gate 41, ie, the phase difference. A low level is generated only during a period in which the timing difference between the falling edge between the output signal Q + of the detection circuit 1 and the output signal Q + of the phase difference detection circuit 2 occurs, and this period can be extracted. Therefore, when the logical gate 45 further performs a NOR operation on the output of the logical gate 43 and the output of the logical gate 44, the output signal Q + of the phase difference detection circuit 1 is changed by the logical gate 45 as shown in FIG. It is possible to extract only a period in which a timing difference between rising edges between the output signal Q + of the phase difference detection circuit 2 and the rising edge occurs.

By reversing the connection between the output signals Q + and Q- of the phase difference detection circuit 3, the output of the logic gate 45 becomes
A low level is generated only during a period in which a timing difference between falling edges between the output signal Q + of the phase difference detection circuit 1 and the output signal Q + of the phase difference detection circuit 2 occurs, and this period can be extracted. Therefore, in the detection characteristics of the phase difference detection circuits 1 and 2, even if the detection sensitivity between the rising edge and the detection sensitivity between the rising edge and the falling edge is different, the output signal Q + of the phase difference detection circuit 3 According to the selection of the connection method between Q and Q-, it is possible to extract only information of components having high detection sensitivity, thereby enabling highly accurate phase difference detection.

Next, reference numeral 5 indicates a reference pulse gate circuit, and this circuit 5 is a logic circuit 5 having a configuration as shown in FIG.
1 and a NOR gate 52. The configuration and operation of this reference pulse gate circuit will be described below using one embodiment shown in FIG.

The reference pulse gate circuit 5 comprises a logic circuit 51 comprising reset priority set reset flip-flops 53 and 54, a toggle flip-flop 55 with forced reset, and OR gates 56 and 57, and a NOR gate 52. I have.

Here, it is assumed that flip-flops 53, 54 and 55 all sense rising edges of clock input to determine output signals Q and QB. First, as shown in FIG. 2, these flip-flops 53, 54 and 55 are initialized by a reset signal RST.

When the measurement request signal T1 goes high, the QB output of the flip-flop 53 receiving this signal T1 goes low. As shown in FIG. 2, the QB output and the Q + signal of the phase difference detection circuit 1 are applied to the clock terminal of the toggle flip-flop 55 via the OR gate 57. Since the QB output of the toggle flip-flop 55 is inverted at the rising edge of the Q + signal of the phase difference detection circuit 1, the QB output of the toggle flip-flop 55 becomes high level again at the second rising edge of the Q + signal of the phase difference detection circuit 1. Flip to This QB output is supplied to the set terminal of the flip-flop 54, and the Q output is inverted to a high level. This Q output is supplied to the reset terminal of the flip-flop 53 via the OR gate 56 together with the reset signal RST. Therefore, this flip-flop 53
Is reset, and the subsequent toggle flip-flop 55
Clock input is prohibited.

Thus, the QB output of the toggle flip-flop 55 outputs a signal in which only one cycle of the Q + output of the phase difference detection circuit 1 becomes high immediately after the application of the measurement request signal T1. When the QB output, the timing comparison pulse PR and the output of the NOR gate 45 are supplied to the NOR gate 52, an output as shown in FIG. 2 is obtained.

As long as the staircase wave RF and the timing comparison pulse PR are continuously input, the phase difference information signal extracted by the phase difference signal extraction circuit 4 is the output signal Q + or Q− of the phase difference detection circuits 1 and 2. It is repeated in the signal cycle.

Therefore, for example, in a reference pulse gate circuit 5 as shown in FIG.
When 1 is applied, after the application, the logic circuit 51 extracts only one cycle of the Q + output of the phase difference detection circuit 1,
If the logical OR of the extracted output signal, the phase difference information signal from the phase difference signal extraction circuit 4 and the timing comparison pulse PR is taken by the logic gate 52, the Q of the phase difference detection circuit 1
It is possible to extract the pulse of the timing comparison pulse PR which is transmitted during only one cycle of the period in which the timing difference between the rising edge between the + output and the Q + output of the phase difference detection circuit 2 occurs.

Therefore, the counter 6 further sets the logic gate 5
2 is counted, and if the counted value is N, a timing difference occurs between the rising edges of the Q + output of the phase difference detection circuit 1 and the Q + output of the phase difference detection circuit 2. This period can be recognized as N times the period (t + dt) of the timing comparison pulse PR.

As described above, the phase relationship between the output signals Q + and Q- of the phase difference detection circuit 1 and the output signals Q + and Q- of the phase difference detection circuit 2 depends on the edge a due to the traveling wave and the reflected wave. The time difference 2T from the edge b is (t +
dt) / dt, the following equation holds.

2T × (t + dt) / dt = N × (t + dt) From this, the value to be measured, ie, the transmission line length T, is the period difference dt between the measured value N and the set input signal as shown in the following equation.
Can be determined by:

T = N × dt / 2 In the above description, the time difference between the rising edge a of the staircase wave RF and the edge b due to the reflected wave is determined to obtain the transmission line through which the staircase wave RF has propagated. Although the embodiment of the present invention has been described for obtaining the length T, the transmission line length T can be similarly obtained by obtaining the time difference between the edge a due to the traveling wave and the edge b due to the reflected wave at the falling edge of the staircase wave RF. Can be requested. In such a case, if a circuit for comparing the phase difference between the falling edges of the input signal is used as the phase difference detection circuits 1, 2, and 3 in the above description, the transmission line length T can be determined in exactly the same procedure. You can ask.

Alternatively, a circuit capable of selectively controlling the phase difference comparison between the falling edges and the phase difference between the rising edges of the input signal may be used as the phase difference detection circuits 1, 2, and 3.

Factors governing the measurement accuracy include the repetition period stability of the input staircase wave RF and timing pulse signal PR, and the above-described detection sensitivity characteristics of the phase difference detection circuits 1, 2, and 3. For the former, the frequency resolution is 1 Hz and the frequency stability is 1 × 10
^If a commercially available synthesizer having a performance of about ^-11 / min is used, for example, a repetition frequency of 50 MHz ± 1 Hz
(5000000 ± 1Hz) and 50.002000M
If the frequency is set to Hz ± 1 Hz (5002000 ± 1 Hz), the resolution can be set to 0.8 ps ± 0.0004 ps. Regarding the latter, as described above, for example,
If the circuit described in Japanese Patent Application Laid-Open No. 2-299037 is applied to a phase difference detection circuit, detection sensitivity of several picoseconds can be realized by using current semiconductor technology. Therefore, the present invention can realize the transmission line length measurement in which both the measurement resolution and the time accuracy are on the order of picoseconds.

[0042]

As is apparent from the above description, according to the present invention, even if the detection sensitivity of the phase detection circuit differs between the edges of the same polarity and between the edges of the opposite polarity, the phase difference detection circuit can be used. The characteristics can be used to the maximum and the transmission line length can be measured with high accuracy. In addition, according to the present invention, the count value corresponding to the transmission line length can be obtained reliably without controlling the number of pulses of the input signal.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a basic circuit configuration of a transmission line length measuring device according to the present invention.

FIG. 2 is a time chart illustrating an operation principle of the transmission line length measuring device according to the present invention.

FIG. 3 is a circuit block diagram showing one embodiment of a circuit configuration applicable to a reference pulse gate circuit in the present invention.

FIG. 4 is a circuit block diagram illustrating an example of a conventional technique.

[Explanation of symbols]

Reference Signs List 100 Transmission line RF Step wave obtained by opening the far end PR Timing comparison pulse a Rising edge due to traveling wave of step wave RF b Rising edge due to reflected wave of step wave RF 1,2,3 Phase difference detection circuit 4 Phase difference Signal extraction circuit 5 Reference pulse gate circuit 6 Counter VR11, VR12 Reference level inputs VR21, VR22 for determining input signal threshold of phase difference detection circuit 1 Reference level inputs VR31, VR31 for determining input signal threshold of phase difference detection circuit 2 VR32 Reference level input for determining the input signal threshold value of the phase difference detection circuit 3 Q + Phase difference information signal of the phase difference detection circuit Q− Logically inverted signal 41, 42, 43, 44 of the phase difference information signal Q + of the phase difference detection circuit , 45, 52 NOR gate 51 Logic circuit 53, 54 Reset priority set reset flip-flop 55 Toggle flip-flop with forced reset 56, 57 OR gate RST Reset signal T1 Measurement request signal 101, 102 Phase difference detection circuit 103 Exclusive OR gate 104 AND gate 105 Counter

Claims (1)

(57) [Claims] 1. A transmission line length measuring apparatus for measuring a transmission line length from a reflected waveform obtained by transmitting a pulse to a transmission line having a far end open, comprising: A reference pulse signal whose repetition cycle is slightly different from the staircase wave is input as an input signal, and the threshold values for the two input signals can be controlled independently,
A first phase difference detection circuit for selectively detecting a phase shift between both input signals at each rising edge or falling edge of the staircase wave due to a traveling wave component; and the staircase wave and the reference pulse signal are input. The signals are input as signals, and the threshold values for the two input signals can be independently controlled, and the phase shift between the two input signals is selectively detected at each rising edge or falling edge due to the reflected wave component of the staircase wave. A second phase difference detection circuit, and the staircase wave are input as two common input signals, the thresholds for the two input signals can be controlled independently, and the reflected wave component and the traveling wave component of the staircase wave A third phase difference detecting circuit for selectively detecting a phase shift between rising edges or between falling edges of the first and second and third phase difference detecting circuits. Second and third Based on the phase difference information signal, one of a phase shift period occurring at a rising portion of the first phase difference information signal and the second phase difference information signal, and a phase shifting period occurring at a falling portion A phase difference signal extracting circuit for selectively extracting one of the first and second phase difference information signals after a request signal is input from the outside and the request signal is input; A reference pulse gate circuit that validates the reference pulse signal within a period and only during a phase shift period extracted by the phase difference signal extraction circuit, and a counter that counts an output signal from the reference pulse gate circuit. A transmission line length measuring device, characterized in that: